Semiconductor device and operating method thereof

Abstract

The invention provides a semiconductor device and an operation method thereof. The operation method of the semiconductor device including an NOR flash memory and an NAND flash memory is improved. The flash memory comprises an NOR type flash memory, an NAND type flash memory, a controller and an internal bus, wherein the NOR type flash memory and the NAND type flash memory are connected with the controller through the internal bus. The controller controls the NOR-type flash memory, or the NOR-type flash memory and the NAND-type flash memory, based on an instruction received from the outside.

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a NOR type flash memory and a NAND type flash memory. Background Art

[0002] In recent years, the number of flash memories equipped with serial interfaces that achieve high-speed input / output of data with a small number of terminals is increasing. For example, there is a standard serial peripheral interface (SPI) that requires an 8-bit command code and a 24-bit address.

[0003] NOR flash memory is equipped with a function of continuously inputting and outputting data in a so-called burst mode or page mode. Figure 1 As shown in (A), when the chip select signal / CS becomes low active, the column address automatically increments when the read command and address are input from the external terminal in synchronization with the serial clock signal, and the read data is sequentially output from the external terminal in synchronization with the serial clock signal. In the programming operation, when the programming command and address are input from the external terminal, the column address automatically increments, and the programming data input from the external terminal in synchronization with the serial clock signal is programmed into the storage cell. This continuous reading or continuous writing is terminated by making the chip select signal / CS high (Patent Document 1: Japanese Patent No. 6232109).

[0004] On the other hand, in order to achieve compatibility with NOR serial flash memory, memory equipped with a serial interface has also been put into practical use. In the case of continuous reading in NAND flash memory, when a continuous read command and address are input from an external terminal, the data read from the page of the storage cell array is retained in the page buffer / read circuit, the column address is automatically incremented, and the data retained in the page buffer / read circuit is output from the external terminal in synchronization with the serial clock signal.

[0005] Figure 1(B) represents a timing diagram of the continuous read operation of the NAND flash memory. The chip select signal CS becomes active at a low level, and an 8-bit page data read command (for example, "13h") and a 16-bit page address PA (for selecting the block and the row address of the page) are input. After a delay (latency) equivalent to the time when the data of the selected page of the storage cell array is transmitted to the page buffer / read circuit, an 8-bit read command and a 16-bit address (this is an empty dummy address) for continuous read are input. The NAND flash memory enters a continuous read mode by inputting these series of commands and addresses. The input page address PA is automatically incremented, and the read page data is serially output to the outside in synchronization with the serial clock. During the period when the chip select signal CS is at a low level, that is, during the period of continuous read mode, the flash memory does not need to input a page data read command and a page address PA.

[0006] NOR flash memory can be read at high speed by random access and has excellent durability or retention characteristics, so it is suitable for storing boot code or firmware for system startup. On the other hand, the programming time per byte of NOR flash memory is several dozen times longer than that of NAND flash memory, and the power consumption during programming is also large, so it cannot be said to have excellent retention.

[0007] Therefore, a stacked flash memory in which a NOR flash memory chip (die) and a NAND flash memory chip (die) are stacked has been put into practical use. Figure 1 (A) Figure 1 As shown in (B), the host device enables either the NOR flash memory or the NAND flash memory according to the chip selection signal CS, for example, programming large-capacity data into the NAND flash memory and programming small-capacity data that needs to be read at high speed into the NOR flash memory.

[0008] However, the conventional stacked flash memory operation method requires selecting each of the NOR flash memory and the NAND flash memory to operate, which complicates the processing on the host device side. There is a demand for an improvement in the stacked flash memory operation method. Summary of the invention

[0009] An object of the present invention is to solve such conventional problems, to integrate NAND type flash memory without reducing the performance of NOR type flash memory, and to improve the operation of semiconductor devices.

[0010] The semiconductor device of the present invention includes: an input / output circuit; a NOR-type flash memory and a NAND-type flash memory connected to the input / output circuit via an internal bus; and a controller that controls the operation of the NOR-type flash memory and the NAND-type flash memory according to instructions received from the input / output circuit.

[0011] In the operating method of the semiconductor device including the NOR flash memory and the NAND flash memory of the present invention, the controller of the NOR flash memory controls the operation of the NOR flash memory and the NAND flash memory based on the command received via the input / output circuit.

[0012] According to the present invention, since the actions of the NOR flash memory and the NAND flash memory are controlled based on the instructions received from the input / output circuit, the NOR flash memory and the NAND flash memory can cooperate or even collaborate, which reduces the processing of the host device and improves the convenience of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 (A) is a timing diagram of the continuous read operation of the NOR flash memory. Figure 1 (B) is a timing diagram of the continuous read operation of the NAND flash memory;

[0014] Figure 2 is a block diagram of the overall structure of a stack-type flash memory according to an embodiment of the present invention;

[0015] Figure 3 is a diagram of the internal structure of a stack-type flash memory according to an embodiment of the present invention;

[0016] Figure 4 is a timing diagram of a stacked flash memory according to an embodiment of the present invention when dual mode writing / reading is performed;

[0017] Figure 5 and Figure 6 is a diagram of a programming operation in the stack-type flash memory of the present embodiment;

[0018] Figure 7 is a diagram of a read operation in the stack-type flash memory of the present embodiment;

[0019] Figure 8 and Fig. 9 It is a diagram showing another structural example of the stack-type flash memory according to an embodiment of the present invention.

[0020] Description of Figure Numbers

[0021] 10: Stacked Flash Memory / Flash Memory

[0022] 20: External bus

[0023] 30: Host device

[0024] 100: NOR flash memory

[0025] 110: NOR type storage cell array / NOR type array / NOR memory array

[0026] 120: X-DEC

[0027] 130:SA / WA

[0028] 140: Buffer

[0029] 150: Y-DEC

[0030] 200: NAND flash memory

[0031] 210: NAND type memory cell array / memory cell array / NAND type memory array / NAND type array

[0032] 220: X-DEC

[0033] 230: Page Buffer / SA

[0034] 240: Cache register

[0035] 250: Y-DEC

[0036] 260, 300, 300A: Controller

[0037] 310: NOR control

[0038] 320: NAND control

[0039] 330: Input / Output Circuit

[0040] 400: Internal bus

[0041] P0: Select page / starting page / page

[0042] P1, P2, P3: Page / Select Page

[0043] P4, P5: Page

[0044] t0-t7: time DETAILED DESCRIPTION

[0045] The semiconductor device of the present invention includes at least one NOR flash memory and at least one NAND flash memory as different types of flash memories. The semiconductor device includes a package structure formed by stacking a chip formed with the NOR flash memory and a chip formed with the NAND flash memory.

[0046] like Figure 2 As shown, the stacked flash memory 10 of the embodiment of the present invention is connected to the host device 30 via the external bus 20. The stacked flash memory 10 includes a NOR flash memory 100, a NAND flash memory 200, a controller 300, and an internal bus 400. The NOR flash memory 100, the NAND flash memory 200, and the controller 300 are connected to each other via the internal bus 400, and data can be transmitted between them via the internal bus 400. The external bus 20 is not particularly limited, and is, for example, SPI, quad SPI, or octal SPI. When the external bus 20 corresponds to SPI, the internal bus 400 also corresponds to SPI.

[0047] The stacked flash memory 10 includes, but is not limited to, a stack of a chip (or die) having a NOR flash memory 100 and a controller 300 and a chip (or die) having a NAND flash memory 200. The stacked chips are electrically connected to each other, for example, a conductive pad formed on the surface of one chip is directly or indirectly connected to a conductive pad formed on the surface of another chip via a conductive member. Alternatively, electrical connection between chips can be achieved by passing a conductive member between the stacked chips.

[0048] The stacked flash memory 10 includes a package (e.g., resin seal or ceramic seal, etc.) for accommodating the stacked chips. The package includes external terminals for providing an electrical interface between the internal chips and the outside. The external terminals include, for example, a ball grid array (BGA) or a land grid array (LGA) formed on the back of the package, and the external terminals may include data input / output terminals, address terminals, clock terminals, control terminals, power supply terminals, etc.

[0049] The host device 30 outputs instructions (commands), addresses, clock signals, control signals, etc. to the stacked flash memory 10 via the external bus 20, so that the stacked flash memory 10 performs a desired operation. The instructions used by the host device 30 are instructions in accordance with the specifications of the NOR flash memory. The host device 30 uses the stacked flash memory 10 as a NOR flash memory, issues programming instructions, read instructions, and delete instructions for the NOR flash memory, and operates the NAND flash memory 200 in a place invisible to the user.

[0050] Figure 3 1 is a diagram showing the internal structure of the stacked flash memory 10 of the present embodiment. The NOR flash memory 100 includes the following components: a NOR storage cell array 110, in which a plurality of storage cells are connected in parallel between a bit line and a source line; a row address decoder (X-Decoder, X-DEC) 120, which selects / drives a word line based on a row address; a SA / WA (Sense Amplifier / Write Amplifier) ​​130, which reads data from a storage cell or writes data in a storage cell; a buffer 140, which holds data of one page received from an input / output circuit 330 during a programming operation and transmits data selected based on a column address to the SA / WA 130; and a column address decoder (Y-Decoder, Y-DEC) 150, which selects a bit line based on a column address.

[0051] The NOR flash memory 100 is equipped with a function of continuously inputting / outputting data, and can read or program data in units of pages. The page unit is not particularly limited and can be set arbitrarily, for example, 256 bytes. The buffer 140 of the NOR flash memory 100 can store data of one page, and during the programming operation, the buffer 140 holds the data received via the input / output circuit 330. The data held in the buffer 140 is selected based on the column address of the Y-DEC 150, and the selected data is transmitted to the SA / WA 130, and the SA / WA 130 programs the selected storage cell of the selection bit based on the transmitted data.

[0052] The NAND flash memory 200 includes the following components: a NAND cell array 210, which is connected in series so that a plurality of memory cells arranged in a matrix form a NAND string; an X-DEC 220, which selects / drives a block and a word line based on a row address; a page buffer / SA (sense amplifier) ​​230, which holds data read from a selected page of the memory cell array 210, or holds data to be programmed in a selected page; a cache register 240, which transfers data to and from the page buffer / SA 230 (for example, in units of 1 / 2 pages); a Y-DEC 250, which selects a bit line based on a column address; and a controller 260, which is connected to an internal bus 400. In addition, although not shown here, the stacked flash memory 10 may include a voltage generation circuit or a clock generation circuit, etc., which generates voltages required for reading, programming, and erasing data.

[0053] The controller 300 includes a NOR control 310 and a NAND control 320, and the controller 300 is connected to an input / output circuit 330 via an internal bus 400. The input / output circuit 330 is connected to a host device 30 via an external bus 20, and receives commands, addresses, data, etc. from the host device 30. In addition, the input / output circuit 330 is connected to a NOR flash memory 100 and a NAND flash memory 200 via the internal bus 400.

[0054] The input / output circuit 330 corresponds to SPI, more preferably corresponds to a four-wire SPI or an eight-wire SPI, and data transmission in the external bus 20 and the internal bus 400 is performed in synchronization with a clock signal.

[0055] The input / output circuit 330 includes an input / output terminal, a clock terminal, etc., and performs data input / output in synchronization with the rising edge and / or falling edge of the clock signal supplied to the clock terminal. During the programming operation, the data obtained via the input / output circuit 330 is provided to the NOR flash memory 100 or the NAND flash memory 200 via the internal bus 400, so that the NOR flash memory 100 or the NAND flash memory 200 can be programmed.

[0056] The controller 300 controls the operation of the NOR flash memory 100 or the NAND flash memory 200 based on the command received from the host device 30, and further controls the data transfer of the internal bus 400. The NOR control 310 controls the operation of the NOR flash memory 100, and the NAND control 320 controls the operation of the NAND flash memory 200. More specifically, the NOR control 310 controls the operation of the NOR flash memory 100 such as reading, programming, and erasing based on the command received via the input / output circuit 330, or causes the NAND control 320 to generate an internal command or internal address for controlling the NAND flash memory 200 based on a specific command received from the input / output circuit 330.

[0057] When the specific command from the host device 30 corresponds to a command including programming of the NAND flash memory 200, the NOR control 310 causes the NAND control 320 to generate an internal command and an internal address for programming the NAND flash memory 200, and provides the generated internal command and internal address to the controller 260 of the NAND flash memory 200 via the input / output circuit 330 and the internal bus 400. The NAND control 320 refers to a look-up table (LUT) to generate an internal address corresponding to the address received from the host device 30. In response to the received internal command, the controller 260 of the NAND flash memory 200 programs the data received via the input / output circuit 330 and the internal bus 400 into the selected page of the NAND memory array 210.

[0058] In addition, when the specific command corresponds to a command including reading of the NAND flash memory 200, the NOR control 310 causes the NAND control 320 to generate an internal command and an internal address for reading the NAND flash memory 200, and provides the generated internal command and internal address to the controller 260 of the NAND flash memory 200 via the input / output circuit 330 and the internal bus 400. In response to the received internal command, the controller 260 of the NAND flash memory 200 outputs the data read from the selected page of the NAND memory array 210 to the external bus 20 via the internal bus 400 and the input / output circuit 330.

[0059] When the stacked flash memory 10 receives a command (instruction) according to the NOR flash memory from the host device 30, the NOR control 310 controls the NOR flash memory 100 in response to the command and / or controls the NAND flash memory 200 via the NAND control 320. For example, when programming data such as a boot code or firmware into the stacked flash memory 10, the host device 30 issues a specific instruction (such as a continuous write instruction or a page mode write instruction, etc.), address, and data.

[0060] When receiving a specific command from the host device 30 via the input / output circuit 330, the NOR control 310 controls the program of the NOR flash memory 100, and issues an internal command and an internal address for programming the NAND flash memory 200 from the NAND control 320. The NOR flash memory 100 writes the data received from the input / output circuit 330 into the NOR array 110, and the NAND flash memory 200 writes the data received from the input / output circuit 330 into the NAND array 210 in parallel with the writing of the NOR flash memory 100 or separately.

[0061] When reading data such as boot data or firmware from the stacked flash memory 10, the host device 30 issues a specific command (for example, a continuous read command or a page mode read command, etc.) and an address. When receiving a specific command from the host device 30 via the input / output circuit 330, the NOR control 310 controls the reading of the NOR flash memory, and the NAND control 320 issues an internal command and an internal address for reading the NAND flash memory 200. The NOR flash memory 100 outputs the data read from the NOR array 110 through the input / output circuit 330, and the NAND flash memory 200 outputs the data read from the NOR flash memory or read from the NAND array 210 alone through the input / output circuit 330.

[0062] Next, an example of continuously programming data into the stack type flash memory 10 of this embodiment will be described. Figure 4 is the timing diagram for programming data, Figure 5 , Figure 6 This is to explain the action migration of NOR flash memory and NAND flash memory. Tpgm_NOR is the programming time of one page of NOR flash memory, Tpgm_NAND is the programming time of two pages of NAND flash memory, and Tread is the data reading time from NAND flash memory to NOR flash memory.

[0063] Assume that one page of the NOR flash memory 100 is 256 bytes and one page of the NAND flash memory 200 is 2K bytes. That is, one page of data in the NAND flash memory 200 is equivalent to eight pages of data in the NOR flash memory 100 .

[0064] During the programming operation, the NOR flash memory 100 stores 256 bytes of data in the buffer 140, and programs the data read from the buffer 140 in units of bits, bytes, or words into the selected storage cells of the selected page. On the other hand, the NAND flash memory 200 stores 2K bytes of data in the cache register 240 and the page buffer / SA 230, respectively, and programs the data held in the page buffer / SA 230 into the selected page in units of pages. Therefore, the NAND flash memory can be programmed at high speed, and the programming time per unit bit of the NOR flash memory 100 is much greater than that of the NAND flash memory 200.

[0065] When the controller 300 receives a command and an address from the host device 30 via the input / output circuit 330, it continuously writes data to the NOR flash memory 100 and the NAND flash memory 200 in page mode. In the continuous writing, for example, the row address at the beginning of the NOR flash memory 100 is specified, and then the row address and the column address are automatically generated by the counter. The row address of the NAND flash memory 200 is automatically generated by the NAND control 320 or the controller 260. The end of the continuous writing is, for example, toggling the CS / signal in the same way as before (see Figure 1 (A)), or the end instruction of continuous writing is input into the stack type flash memory 10.

[0066] When the continuous writing operation starts, data is taken in from the external bus 20 via the input / output circuit 330. Figure 4 During the period from time t0 to t1, data of two pages of the NAND flash memory 200 is taken in from the input / output circuit 330. The taken in data is sequentially stored in the buffer 140 of the NOR flash memory 100 via the internal bus 400, and in parallel, is also sequentially stored in the cache register 240 of the NAND flash memory 200. When the cache register 240 stores data of one page, the data of the one page is transferred to the page buffer / SA 230, and the data of the next page is loaded.

[0067] The data stored in the buffer 140 is transmitted to the SA / WA 130 in bit units or in multi-bit units, and the SA / WA 130 programs the received data into the selected storage cell (one or more bits) of the selected page P0. Figure 5 At time t1, if Figure 5 As shown in (B), the loading of two pages of data from the external bus 20 to the cache register 240 of the NAND flash memory 200 is completed.

[0068] When the data loading from the external bus 20 is completed at time t1, the NAND flash memory 200 programs the stored data of two pages during the period from time t1 to time t2. Figure 5 (C). The first one page of data held in the page buffer / SA 230 is programmed into the selected page P0 of the NAND array, and then the data held in the cache register 240 is transferred to the page buffer / SA 230, and the data is programmed into the selected page P1. While the NAND flash memory 200 is being programmed, the page P0 is programmed in the NOR flash memory 100.

[0069] During the period from time t2 to time t3, the next two pages of data are loaded into the NAND flash memory 200. Figure 5 At time t3, when data loading is completed, programming of page P0 in the NOR flash memory 100 is completed. Figure 5 (E) in.

[0070] During the period from time t3 to time t4, the NAND flash memory 200 programs the stored data of two pages. Figure 5 In (F), data is programmed in the selected pages P2 and P3 of the NAND array 210. The programming of the NAND flash memory 200 at the end of time t4 is shown in FIG. Figure 6 (A) in.

[0071] When programming is completed immediately at time t4, in order to program page P1 of the NOR flash memory 100 during time t4-t5, the data of page P0 of the NAND flash memory is read out and the read data is programmed into page P1 of the NOR flash memory 100. Figure 6(B). The data of the selected page P0 of the NAND memory array is read out to the page buffer / SA 230, and then the read data is transferred to the cache register 240. The data of page P0 maintained in the cache register 240 includes data of 8 pages of pages P0 to P7 of the NOR flash memory 100. The controller 260 selects 256 bytes of data of column address 257 to column address 512 of the cache register 240 via the Y-DEC 250, and outputs the 256 bytes of data to the internal bus 400. The NOR flash memory 100 sequentially stores the 256 bytes of data received from the internal bus 400 in the buffer 140, and then transfers the selected data of the buffer 140 to the SA / WA 130 via the Y-DEC 150, and programs it in the selected storage cell of page P1 of the NOR memory array.

[0072] At time t5, the data transfer to the buffer 140 is completed. The situation at this time is shown in FIG. Figure 6 In (C), the data held in the page buffer / SA 230 and the cache register 240 of the NAND flash memory 200 are reset, and preparation is made for loading the next two pages of data.

[0073] During the period from time t5 to time t6, data for the next two pages is loaded from the external bus 20 to the NAND flash memory 200. Figure 6 During this period, the NOR flash memory 100 is programming page P1. During the period between time t6 and t7, the NAND flash memory 200 programs the loaded 2 pages of data into pages P4 and P5. Figure 6 At time t7, the programming of page P5 in the NAND flash memory 200 is completed, and at approximately the same time, the programming of page P1 in the NOR flash memory 100 is completed. Figure 6 (F).

[0074] In this way, data read from the NAND flash memory 200 is programmed in the page P1 and subsequent pages of the NOR flash memory 100 . Figure 4This is a timing diagram when programming the data of two pages of page P0 and page P1 programmed in the NAND flash memory 200 into the NOR flash memory 100. The clock signal based on SPI is 100MHz, and data output is synchronized with the data terminal ready (Data Terminal Ready, DTR) (rising edge and falling edge). When it is assumed that Tpgm_NOR ≒ 0.7ms and Tread = 400us, in the stacked flash memory 10 of this embodiment, the time Ta required to program 16 pages (NOR_Page0 ~ Page15) in the NOR flash memory 100 is

[0075] Ta≒(400us×16)+0.7ms<8ms.

[0076] On the other hand, in the conventional stack type flash memory, the time Tb required to program 16 pages in the NOR type flash memory is

[0077] Tb≒16×0.7ms=11.2ms.

[0078] In this way, during the programming operation, data is stored in the NAND type flash memory that can be programmed at high speed and used as a cache memory, thereby significantly shortening the time required for programming the NOR type flash memory.

[0079] like Figure 6 As shown, if data of six pages of pages P0 to P5 programmed into the NAND flash memory 200 are programmed into the NOR flash memory 100, 48 pages of data are programmed into the NOR flash memory 100. The larger the data size programmed into the NOR flash memory 100, the greater the reduction in the time required for programming.

[0080] Thus, according to the present embodiment, the NOR flash memory and the NAND flash memory cooperate or even collaborate. During the programming operation, data is loaded into the NOR flash memory 100 and the NAND flash memory 200, the data programmed in the NAND flash memory 200 is read out therefrom, and the read data is programmed into the NOR flash memory 100. Therefore, compared with the case of programming data into a NOR flash memory unit, the programming time can be greatly shortened.

[0081] Next, the operation of continuously reading data from the stack type flash memory 10 of this embodiment will be described. Figure 4As shown, the NOR flash memory 100 stores NOR_Page0 to Page15 (1 page is 256 bytes, and NOR_Page0 to Page15 corresponds to 2 pages, Page P0 and Page P1, of the NAND flash memory), and the NAND flash memory 200 stores Page P0 to Page P63 (1 page is 2K bytes). Pages P0 to P63 correspond to, for example, data of one block of the NAND memory array, and the read data is, for example, 1Mb (128K bytes) of boot data. The controller 300 manages the addresses of NOR_Page0 to Page15 stored in the NOR flash memory and the addresses of Pages P0 to P63 stored in the NAND flash memory, for example, with reference to the LUT.

[0082] Figure 7 (A) is a timing diagram for continuously reading data from page P0 to page P63. Figure 7 (B)~ Figure 7 (E) is a diagram for explaining the operation transition of the NOR type flash memory and the NAND type flash memory.

[0083] When the controller 300 receives a continuous read command of the NOR specification from the host device 30, the controller 300 controls the continuous read of the NOR flash memory 100 and the NAND flash memory 200 respectively according to the command. First, the NOR flash memory 100, when the address received from the host device 30 or the address to be read is predetermined, sequentially and continuously reads 4K bytes of data of 16 pages from NOR_Page0 to NOR_Page15 from the NOR memory array 110 based on the predetermined address. As described above, NOR_Page0 to Page15 correspond to 4K bytes of Page P0 and Page P1 of the NAND flash memory.

[0084] The unit read out from the NOR memory array 110 may be in bit units, byte units, word units, or any other units. X-DEC 120 generates row addresses for reading out NOR_Page0 to Page15. In addition, Y-DEC 150, for example, automatically increments the address counter to generate column addresses 0 to 255 for reading out NOR_Page0. When the reading of NOR_Page0 is completed, the address counter is reset again to generate column addresses 0 to 255 for continuously reading out NOR_Page1. The data read out from the NOR memory array 110 may be temporarily stored in the buffer 140, or may be output to the input / output circuit 330 via the internal bus 400 without being stored in the buffer 140.

[0085] While NOR flash memory 100 continuously reads NOR_Page0 to Page15, NAND flash memory 200 in the ready state selects page P2 of NAND memory array 210 via X-DEC 220 and reads page P2. After transferring the data of page P2 to cache register 240, next page P3 is selected and page P3 is read. Figure 7 (B) in.

[0086] When the continuous reading of NOR_Page0 to Page15 by the NOR flash memory 100 is completed, the reading of Pages P2 to P63 by the NAND flash memory 200 is then performed.

[0087] For example, when the SPI-based clock signal is 100MHz and synchronized with DTR for data reading, Figure 7 As shown in (A), the time required to read 4KB of NOR_Page0 to Page15 from the NOR flash memory 100 is about 40us. The read time is roughly equal to or slightly greater than the delay of the array read of the NAND flash memory 200. Therefore, while the NOR flash memory 100 is continuously reading NOR_Page0 to Page15, the NAND flash memory 200 ends the array read of page P2 and sets the data of page P2 in the cache register 240 via the page buffer / SA 230.

[0088] In this way, immediately after the continuous reading of 4 KB (2×2 KB) of NOR_Page0 to Page15 by the NOR flash memory 100 is completed, the continuous reading of Page P2 starts from the NAND flash memory 200. Figure 7 In (C). After that, the NAND flash memory reads out pages P3 to P63 in sequence. Figure 7 (D) Figure 7 (E) in.

[0089] If the time required to read one page of the NAND flash memory is set to 40us, the time required for the NAND flash memory 200 to continuously read 62 pages from P2 to P63 is 40us×62=2480. As a result, the time required to continuously read 64 pages is 40us+(40us×62)≒2.6ms.

[0090] The continuous reading according to this embodiment substantially cancels out the array reading delay of the NAND flash memory, and thus enables high-speed reading compared to the case where 64 pages of data are continuously read from a single NAND flash memory.

[0091] In the embodiment, an example is shown in which a part of the data loaded from the external bus into the NOR flash memory 100 is programmed and the remaining data is programmed by the NAND flash memory 200. For example, when the stack flash memory 10 is not used, or through background processing, the data programmed into the NAND flash memory 200 can be copied into the NOR flash memory 100. The NAND flash memory 200 can retain a backup of the data written into the NOR flash memory 100, and data requiring reliability such as boot data can be guaranteed.

[0092] In the above embodiment, an example of programming in the stacked flash memory 10 is described, and in reading, data can be read from each of the NOR flash memory 100 or the NAND flash memory 200. For example, as in the past, the boot data programmed into the NOR flash memory 100 can be read at high speed through SPI. The buffer 140 functions to pass data or bypass data so as not to affect the reading speed.

[0093] like Figure 3 As shown, the input / output circuit 330 is connected to the controller 300 via the internal bus 400, but is not limited thereto. Figure 8 As shown, the controller 300A may include an input / output circuit 330, and the controller 300A may be connected to the external bus 20. Figure 3 As shown, the NAND flash memory 200 is configured to include a controller 260, but as shown in FIG. Figure 8 As shown, the controller 300A can also directly control the NAND flash memory 200 via the input / output circuit 330. The internal command and internal address generated by the NAND control 320 are provided to the NAND flash memory 200 via the input / output circuit 330 and the internal bus 400.

[0094] Furthermore, in the embodiment, the NOR flash memory 100 is configured to include a buffer 140 for storing programming data, but the buffer 140 may also be configured as Fig. 9 The data read out from the NAND flash memory 200 is held in the buffer 140 of the input / output circuit 330, and the data is provided from the input / output circuit 330 to the NOR flash memory 100 via the internal bus 400. Figure 6As shown in time t5-t6, since data needs to be loaded from the external bus 20 to the NAND flash memory 200, the input / output circuit 330 provides the data taken from the external bus 20 to the NAND flash memory 200 via the internal bus 400 without interfering with the buffer 140.

[0095] In the above embodiment, an example of programming boot code or firmware in a stacked flash memory is shown, but this is an example, and the size or type of data to be programmed is not particularly limited. The storage capacity of the NOR flash memory 100 or the NAND flash memory 200 can be appropriately selected according to the data to be programmed or the use environment. In addition, the data size of one page of the NOR flash memory 100 or the data size of one page of the NAND flash memory 200 shown in the above embodiment is an example, and these data sizes can be appropriately changed according to the operation design of the stacked flash memory.

[0096] Although preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A semiconductor device comprising: Input / output circuits; A NOR type flash memory and a NAND type flash memory are connected to the input / output circuit via an internal bus; as well as The controller controls the operations of the NOR type flash memory and the NAND type flash memory based on the instruction received from the input / output circuit.

2. The semiconductor device according to claim 1, wherein The controller programs data received from the input / output circuit into both the NOR-type flash memory and the NAND-type flash memory.

3. The semiconductor device according to claim 1, wherein The controller programs data received from the input / output circuit into the NAND type flash memory during programming of data received from the input / output circuit into the NOR type flash memory.

4. The semiconductor device according to claim 1, wherein The controller reads data programmed into the NAND type flash memory and programs the read data into the NOR type flash memory.

5. The semiconductor device according to claim 1, wherein According to the continuous programming instruction, data are continuously programmed into the NOR type flash memory.

6. The semiconductor device according to claim 1, wherein After the controller reads out the first page of the NOR type flash memory according to the continuous read instruction, it reads out a second page that is continuous after the first page from the NAND type flash memory.

7. The semiconductor device according to claim 6, wherein: While the read data of the first page is being output, array read of the second page is performed.

8. The semiconductor device according to claim 1, wherein The controller receives an instruction to the NOR type flash memory from the input / output circuit, and generates an instruction to the NAND type flash memory according to the instruction. The controller receives an address to the NOR type flash memory from the input / output circuit, and generates an address to the NAND type flash memory according to the address.

9. The semiconductor device according to claim 1, wherein: A chip formed with the NOR type flash memory is stacked with a chip formed with the NAND type flash memory.

10. An operating method of a semiconductor device, the semiconductor device comprising a NOR type flash memory and a NAND type flash memory, The controller of the NOR type flash memory controls the operations of the NOR type flash memory and the NAND type flash memory based on a command received via an input / output circuit.

11. The operation method according to claim 10, wherein: The controller programs data received from the input / output circuit into both the NOR-type flash memory and the NAND-type flash memory.

12. The operation method according to claim 10, wherein: The controller programs data received from the input / output circuit into the NAND type flash memory during programming of data received from the input / output circuit into the NOR type flash memory.

13. The operation method according to claim 10, wherein: The controller reads data programmed into the NAND type flash memory and programs the read data into the NOR type flash memory.

14. The operation method according to claim 13, wherein: The controller, after programming the data received from the input / output circuit into the NAND type flash memory, reads data from the NAND type flash memory and provides the read data to the NOR type flash memory.

15. The operation method according to claim 13, wherein: When the unit of one page of the NOR type flash memory is M bytes and the unit of one page of the NAND type flash memory is M×k, After the programming of the first page of the NOR type flash memory is completed, the controller programs the first page and subsequent pages of the NOR type flash memory based on the data read from the NAND type flash memory, wherein k is a positive integer.

16. The operation method according to claim 15, wherein: The controller selectively reads data corresponding to the subsequent page from data read from a selected page of the NAND flash memory when programming the subsequent page of the NAND flash memory.

17. The operation method according to claim 16, wherein: The controller loads data of a next page to be programmed from the input / output circuit to the NAND flash memory during programming of the subsequent page.

18. The operation method according to claim 10, wherein: After the controller reads out the first page of the NOR type flash memory according to the continuous read instruction, it reads out a second page that is continuous after the first page from the NAND type flash memory.

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