Method for generating compiler instruction scheduling model based on processor description file

Abstract

The invention discloses a method for generating a compiler instruction scheduling model based on a processor description file, and relates to the technical field of processor design. According to the method for generating the compiler instruction scheduling model based on the processor description file, the information of each instruction is extracted by automatically scanning and analyzing the processor design result file, and the LLVM compiler is automatically created according to the requirements of the processor scheduling model in the compiler and the collected information; the model generation speed can be greatly improved, and the problem that errors are likely to occur due to manual participation can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of processor design, and in particular to a method for generating a compiler instruction scheduling model based on a processor description file. Background Art

[0002] The compiler is a key module in the processor design process. Whenever the processor design changes, the compiler needs to be regenerated. The correct instruction scheduling model can assist the compiler to correctly complete instruction scheduling and generate better performance code. Most existing solutions rely on manual reading of the processor instruction manual, manual analysis of dependencies and completion of the scheduling model implementation, which is time-consuming and prone to errors. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a method for generating a compiler instruction scheduling model based on a processor description file.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A method for generating a compiler instruction scheduling model based on a processor description file, comprising:

[0006] Obtaining a processor design result file; the processor design result file stores processor design information and interface functions;

[0007] Initialize entry variables based on the interface function;

[0008] Taking the initialized entry variable as the entry, obtaining all instructions in the current processor, and traversing the instructions one by one;

[0009] Analyze the hardware behavior corresponding to each instruction traversed to obtain instruction description information;

[0010] Processing instruction description information in the compiler instruction scheduling model according to the requirements of the LLVM compiler to generate scheduling related code;

[0011] The scheduling-related code is integrated into the LLVM compiler source code to rebuild the LLVM compiler.

[0012] Optionally, the interface function restores the processor design information stored in the processor design result file to the memory.

[0013] Optionally, the processor design information restored to the memory is represented in the form of a structure and a doubly linked list.

[0014] Optionally, the structure is a C language structure.

[0015] Optionally, the interface function is farm_create_core.

[0016] Optionally, the initialized entry variable includes multiple member variables, and each member variable corresponds to a type of processor design information.

[0017] A computer-readable storage medium stores a computer program; the computer program is used to implement the above-mentioned method for generating a compiler instruction scheduling model based on a processor description file.

[0018] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0019] The method for generating a compiler instruction scheduling model based on a processor description file provided by the present invention can greatly improve the speed of model generation and avoid error-prone problems caused by manual participation by automatically scanning and analyzing the processor design result file, extracting information of each instruction, and automatically creating an LLVM compiler according to the requirements of the processor scheduling model in the compiler and the collected information. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A flowchart of a method for generating a compiler instruction scheduling model based on a processor description file provided by the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In the process of regenerating the compiler, it is necessary to be able to automatically regenerate an instruction scheduling model that matches the processor, provide the compiler with the resource usage of the instructions, assist the compiler to correctly complete the instruction scheduling, and generate code with better performance. By automatically generating the scheduling model, the time-consuming and error-prone problems caused by manual reliance can be avoided. In the processor design process, the definition of resources has a fixed format and is limited. Similarly, the definition and usage of resources in the instructions also have a fixed format. The instruction scheduling model specified in the compiler is also a fixed format. Therefore, it is entirely possible to implement a tool to automatically analyze the processor design result file, convert it, and generate the scheduling model required by the compiler. Based on this, the purpose of the present invention is to provide a method for generating a compiler instruction scheduling model based on a processor description file, which can greatly improve the speed of model generation and avoid the error-prone problems caused by manual participation.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Input: The processor design result file is a dynamic link library file, assuming its name is core.so. The processor design information is represented in the form of a structure (C language structure) and a doubly linked list and stored in the so file. The so file also provides a series of interfaces (functions). The tool designed in this solution will load the so file and call the interfaces it provides to restore the processor design information of the so file to the memory. In the memory, the processor design information is also stored and represented in the form of a structure and a doubly linked list for easy retrieval.

[0026] Based on this, Figure 1 As shown, the method for generating a compiler instruction scheduling model based on a processor description file provided by the present invention includes:

[0027] Step 100: Obtain the processor design result file. In this step, the core.so file is loaded through the dynamic link library loading function provided by the operating system.

[0028] In actual application, mycore=dlopen(core.so) / / dlopen function can be used. mycore=dlopen(core.so) / / dlopen function is a dynamic link library loading function provided by the operating system.

[0029] After loading, core.so will provide an interface function farm_create_core. By calling this interface, the processor design information contained in core.so can be restored to the memory, making it easier to retrieve the processor design information in subsequent steps.

[0030] core_create=dlsym(mycore,"farm_create_core")

[0031] farm_t farm=core_create()

[0032] The interface function mentioned in this step refers to farm_create_core. The interface function farm_create_core is designed and implemented by Xinyihui, and is not provided by the operating system or other modules. The processor design information restored to the memory exists in the form of a structure and a doubly linked list.

[0033] Step 101: Initialize entry variables based on the interface function. Based on the description of step 100 above, the information retrieval entry is the farm variable of farm_create_core, which is a structure containing multiple member variables, each of which corresponds to a type of processor design information, and its inst member stores information related to the processor's instructions.

[0034] Step 102: Using the initialized entry variable as the entry, obtain all instructions in the current processor, and traverse the instructions one by one. For example, using the farm variable initialized in step 101 as the entry, obtain all instructions in the current processor through farm->inst, and traverse them one by one.

[0035] Step 103: Parse the hardware behavior corresponding to each instruction obtained by the traversal to obtain instruction description information. In this step, for each instruction obtained by the traversal in step 102, the corresponding hardware behavior is parsed to obtain instruction description information. For example, for the LW instruction (memory load instruction), its hardware behavior description is shown in Table 1.

[0036] Table 1LW instruction hardware behavior description table

[0037] Line Number Instruction hardware behavior description code 1 inst"LW""rd"(i32)(ret)"rs1"(u32)"immI"(i32):{ 2 rs1(32)useat1; 3 immI(32)useat1; 4 rd(32)defat3; 5 }

[0038] Among them, the first line represents: the instruction name is LW, and three operands rd, rs1 and immI are required. Among them, operand rd is i32 signed 32-bit integer and is the output operand after the instruction is executed, operand rs1 is u32 unsigned 32-bit integer type, and operand immI is a signed 32-bit integer.

[0039] Line 2 represents: The LW instruction requires the input operand rs1 at the first stage of its execution.

[0040] Line 3 represents: The LW instruction requires the input operand immI at the first stage of its execution.

[0041] The fourth line means that the LW instruction will write the memory data to the output register only at the third stage of its execution. That is, the result of this instruction will be generated only at the third clock cycle. Before that, other instructions that need to use the result of the LW instruction must wait.

[0042] The farm->inst bidirectional list stores all instructions, and each instruction is attached with the above definition information.

[0043] Step 104: Process the instruction description information according to the requirements of the LLVM compiler to generate scheduling related codes.

[0044] In the actual application process, this step will process the instruction description information obtained in the above step 103, and generate the following code required by the compiler (i.e., scheduling-related code) according to the requirements of the LLVM compiler:

[0045] DefLW_ITT:IICClass<IIC_ah_3_1_1>

[0046] Among them, LW represents the LW instruction, 3 represents that the result of the LW instruction can only be generated in the third clock cycle of the execution of the instruction, and the two 1s represent that the two inputs required for the execution of the LW instruction must be ready in the first clock cycle.

[0047] For each instruction, the instruction hardware behavior description is analyzed and then the corresponding LLVM compiler code is generated.

[0048] Step 105: Integrate the scheduling related code into the LLVM compiler source code to rebuild the LLVM compiler.

[0049] In actual application, by integrating the scheduling-related code automatically generated in step 104 into the LLVM compiler source code and then rebuilding the LLVM compiler, the compiler can automatically obtain the function of scheduling instructions according to the characteristics of the current processor.

[0050] Among them, for compilers that lack scheduling information and cannot perform instruction scheduling, the following instruction sequences will be generated, which are functionally correct but have suboptimal performance:

[0051] lw t0,t1,32

[0052] addi t0,t0,1

[0053] addi t2,t2,2

[0054] addi t3,t3,3

[0055] During actual execution, there is a pause of 2 cycles between the first and second instructions, because the result of the LW instruction cannot be generated until the third clock cycle, and the second instruction must wait for 2 clock cycles.

[0056] For a compiler that can perform instruction scheduling by obtaining scheduling information, the following functionally correct and performance-optimal instruction sequence will be generated:

[0057] lw t0,t1,32

[0058] addi t2,t2,2

[0059] addi t3,t3,3

[0060] addi t0,t0,1

[0061] While the last instruction is waiting for t0, the other two instructions can be executed first.

[0062] Based on the above description, the present invention can greatly improve the speed of model generation and avoid error-prone problems caused by manual participation by automatically collecting and classifying instruction resource usage information and automatically generating a corresponding scheduling model according to compiler requirements.

[0063] Furthermore, in processor design, the definition of resources has a fixed format, and the number of resources is not infinite. Similarly, the use of resources by instructions is also described in a fixed format, and there is no randomness. Therefore, the above steps 100 to 103 can comprehensively collect information and generate the instruction scheduling model required by the compiler.

[0064] In addition, the method for generating a compiler instruction scheduling model based on a processor description file provided above is implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0065] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0066] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for generating a compiler instruction scheduling model based on a processor description file, characterized in that: include: Get the processor design result file; The processor design result file stores processor design information and interface functions; Initialize entry variables based on the interface function; Taking the initialized entry variable as the entry, obtaining all instructions in the current processor, and traversing the instructions one by one; Analyze the hardware behavior corresponding to each instruction traversed to obtain instruction description information; Process the instruction description information to generate scheduling related code according to the requirements of the LLVM compiler; The scheduling-related code is integrated into the LLVM compiler source code to rebuild the LLVM compiler.

2. The method for generating a compiler instruction scheduling model based on a processor description file according to claim 1, characterized in that: The interface function restores the processor design information stored in the processor design result file to the memory.

3. The method for generating a compiler instruction scheduling model based on a processor description file according to claim 2, characterized in that: The processor design information restored to the memory is represented in the form of a structure and a doubly linked list.

4. The method for generating a compiler instruction scheduling model based on a processor description file according to claim 3, characterized in that: The structure is a C language structure.

5. The method for generating a compiler instruction scheduling model based on a processor description file according to claim 1, characterized in that: The interface function is farm_create_core.

6. The method for generating a compiler instruction scheduling model based on a processor description file according to claim 1, characterized in that: The initialized entry variables include a plurality of member variables, each of which corresponds to a type of processor design information.

7. A computer-readable storage medium, characterized in that: A computer program is stored; the computer program is used to implement the method for generating a compiler instruction scheduling model based on a processor description file as described in any one of claims 1-6.

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