RISC-V CPU architecture supporting storage and calculation integrated cache

Abstract

The invention provides an RISC-VCPU architecture for supporting storage and calculation integrated cache by adopting a storage and calculation integrated arbiter. The RISC-VCPU architecture comprises a sequential pipeline processor, a storage and calculation integrated data cache, an instruction cache and the storage and calculation integrated arbiter. According to the invention, the sequential pipeline processor with a traditional sequential pipeline structure is adopted, the storage and calculation integrated arbiter is designed, and the sequential pipeline processor is optimized and combined with the instruction cache and the storage and calculation integrated data cache, so that the pipeline processing efficiency is improved, and the energy consumption is reduced; therefore, the RISC-V CPU with higher performance and lower power consumption is realized.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a RISC-V CPU architecture supporting storage-computing integrated cache. Background Art

[0002] With the development of artificial intelligence, the demand for computing power in science and technology has been continuously increasing, and the traditional von Neumann system has gradually been unable to meet such a huge demand for computing power. In the von Neumann architecture, the processor and memory are two distinct individuals, and data is constantly interacting between them. Frequent data exchanges will lead to useless power consumption and unnecessary delays, which is the von Neumann bottleneck, which is a key factor limiting computer performance. Therefore, the storage-computing technology was proposed. As a memory, it has both a storage function mode and additional computing power, and it has quickly attracted widespread attention from academia and industry. However, most storage-computing memories only support some operations, such as only supporting Boolean logic operations, multiplication and accumulation operations, and multi-bit multiplication operations, which are difficult to support all processor operations. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a high-performance, low-power RISC-V CPU, which adopts a sequential pipeline structure and uses a designed integrated storage and computing arbitrator to perform inter-module interaction between the sequential pipeline processor and the integrated storage and computing data cache, thereby realizing the movement of part of the instructions to the memory for execution, reducing the back and forth movement of data between the processor and the memory, thereby improving the processor performance and reducing power consumption.

[0004] In order to solve the above problems, the present invention provides a RISC-V CPU architecture supporting storage-computation integrated cache, including a sequential pipeline processor, a storage-computation integrated data cache, an instruction cache, and a storage-computation integrated arbitrator; the sequential pipeline processor adopts the RISC-V instruction set, and its structure is divided into a five-level pipeline structure: instruction fetch, decoding, execution, memory access / storage and calculation, and write back; the instruction cache adopts a low-order cross prefetch instruction cache, which is composed of multiple columns of storage, and instructions are continuously stored in adjacent bodies, and at the same time, it is equipped with a prefetch function, and the instruction cache is used to receive the instruction fetch signal transmitted by the sequential pipeline processor to fetch the instruction and return the instruction to the sequential pipeline processor; the storage-computation integrated arbitrator is used to control and interact between the sequential pipeline processor and the storage-computation An integrated data cache is provided, and the instruction fetch structure of the instruction cache and the sequential pipeline processor are adjusted to support the operation of the storage-computing integrated arbitrator. If the instruction returned to the sequential pipeline processor is a memory access instruction, the storage-computing integrated arbitrator can obtain the memory access address of the memory access instruction and decode the next n instructions of the current instruction corresponding to the memory access instruction, and judge whether a storage-computing integrated operation is needed according to the decoding result and the memory access address. If it is determined that a storage-computing integrated operation is needed, the storage-computing integrated arbitrator selects to store the data of the instruction that needs to be stored-computing integrated as storage-computing data, and passes it to the storage-computing integrated data cache.

[0005] The present invention adopts a sequential pipeline processor with a traditional sequential pipeline structure, designs a storage-computation integrated arbitrator, cooperates with an instruction cache and a storage-computation integrated data cache to optimize the sequential pipeline processor, merges instructions that can be merged, thereby improving pipeline processing efficiency and reducing energy consumption, thereby achieving a RISC-V CPU with higher performance and lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Attached Figure 1 Shown is the overall architecture diagram of the RISC-V CPU architecture supporting storage and computing integrated cache as described in this specific implementation method.

[0007] Attached Figure 2 Shown is a structural diagram of the instruction cache adapted to the storage-computing integrated arbiter in this specific implementation.

[0008] Attached Figure 3 Shown is a circuit structure diagram of the storage-computing integrated arbiter in this specific implementation manner. DETAILED DESCRIPTION

[0009] The specific implementation of the RISC-V CPU architecture supporting storage-computation integrated cache provided by the present invention is described in detail below with reference to the accompanying drawings.

[0010] Figure 1The figure shows the overall architecture of the RISC-V CPU architecture supporting the integrated storage and computing cache described in this specific implementation, which includes four parts: a sequential pipeline processor, a storage and computing integrated data cache (CIM D-Cache), an instruction cache (I-Cache), and a storage and computing integrated arbiter (CIM Arbiter). The sequential pipeline processor of this specific implementation adopts the RISC-V instruction set.

[0011] The sequential pipeline processor of this specific implementation adopts a traditional sequential pipeline structure, and its structure is divided into a five-level pipeline structure: instruction fetch, decoding, execution, memory access (storage calculation), and write back. According to the needs of the sequential pipeline processor and the requirements of timing delay, the pipeline length can be lengthened or shortened. The specific implementation can merge or split the pipeline stages by itself. Specifically, the sequential pipeline processor includes: an instruction counter (PC Control), a branch predictor (Branch Predictor), an instruction queue (Inst Queue), a decoder (Decoder), a register file (RegFile), an arithmetic logic unit (ALU), a jump module (Branch), a floating point calculation unit (FPU), a multiplication and division module (MuVDiv), a storage control module (MemCtrl), a control and status register (CSR), a data selector (Data Mux), and registers (Reg) between each level. The specific working principle can refer to the working principle of a traditional sequential pipeline structure processor.

[0012] In the instruction fetching stage of the sequential pipeline processor, the instruction cache (I-Cache) that interacts with the sequential pipeline processor adopts a low-order cross prefetch cache. Its structure is as follows Figure 2 As shown, the I-Cache adopts a low-order cross structure, consisting of multiple columns of storage, and the instructions are continuously stored in adjacent bodies, and it also has a pre-fetch function. The instruction cache is used to receive the instruction fetch signal transmitted by the sequential pipeline processor to fetch the instruction and return the instruction to the sequential pipeline processor.

[0013] When accessing a data block (Data Block) in the I-Cache, the branch predictor (BranchPredictor) takes out the single or multiple data blocks behind it and puts them into the I-Cache. Of course, since there are branch instructions in RISC-V instructions, and the prediction rate of our branch predictor cannot be guaranteed to be 100% correct, when the prediction fails, it will cause the wrong instruction to enter the I-Cache. If the subsequent storage and computing integrated arbiter (CIM Arbiter) uses the wrong instruction passed by the I-Cache, a flush operation is required, which will delay a certain clock cycle, but as long as the accuracy of the branch prediction is ensured, the flushing will not occur frequently.

[0014] I-Cache adopts low-order cross-prefetch cache, and chooses whether to read the next block of the block where the current instruction is located, or more, at the same time according to the accuracy of the branch predictor. That is, if the branch predictor has a very strong prediction ability, it can choose to read the instructions of multiple subsequent blocks of the block where the current instruction is located at the same time, so that the data passed to the CPU contains more instructions; if the branch predictor has a general prediction ability, only the data of the block where the current instruction is located is passed, so that the data passed to the CPU contains only 4 instructions (if an I-Cache block stores 4 instructions).

[0015] The instruction cache (I-Cache) receives the instruction fetch signal transmitted by the sequential pipeline processor, takes out the current instruction, puts it into the current instruction (Current Inst) part, and takes out the remaining instructions in the block where the current instruction is located, and puts them into the predicted instruction (Predictive Inst) part according to the instruction sequence (assuming that an I-Cache block can store 4 instructions, and the current instruction is the second one in the block, then the second one is taken into the Current Inst part, and the third and fourth ones are taken into the Predictive Inst part in sequence). Furthermore, whether to select multiple cache blocks (Cache Block) can be determined based on the accuracy of the branch predictor design and implementation. If the prediction accuracy is high, all instructions in the next block of the current cache block can be additionally selected and taken out together, and placed in the Predictive Inst part in the order of instructions (that is, the fifth, sixth, seventh, and eighth instructions are taken out together and placed in the Predictive Inst part). Finally, the I-Cache passes the instructions of the Current Inst part and the Predictive Inst part to the processor core (CPU core) of the sequential pipeline processor (for example, placed in the instruction queue (Inst Queue)).

[0016] like Figure 1 As shown, the sequential pipeline processor receives the current instruction and subsequent predicted instructions returned by the instruction cache (I-Cache), and the current instruction flows into the decoding stage in sequence. The decoder in the decoding stage can determine the type of instruction based on the RISC-V opcode of the RISC-V instruction set. If the instruction is not a memory access (load) instruction, no storage operation is required. If the instruction is a load instruction, it means that a storage operation may be performed. At this time, a storage-computation arbitrator is required to make an arbitration judgment.

[0017] The storage-computing integrated arbitrator is used to control and interact with the sequential pipeline processor and the storage-computing integrated data cache, and adjust the instruction cache and the instruction fetch structure of the sequential pipeline processor to support the operation of the storage-computing integrated arbitrator; if the instruction returned to the sequential pipeline processor is a memory access instruction, the storage-computing integrated arbitrator can obtain the memory access address of the memory access instruction and decode the next n instructions of the current instruction corresponding to the memory access instruction, and determine whether a storage-computing integrated operation is required based on the decoding result and the memory access address. If it is determined that a storage-computing integrated operation is required, the storage-computing integrated arbitrator selects the data of the instruction that needs to be stored in the storage-computing integrated operation as storage-computing data, and passes it to the storage-computing integrated data cache.

[0018] like Figure 3 The figure shows the circuit structure diagram of the integrated computing and storage arbiter in this specific implementation. The integrated computing and storage arbiter (CIM Arbiter) mainly includes the following parts: adder, simple decoder (Simple Decoder), comparator array, control module (Control), multiplexer (MUX). The integrated computing and storage arbiter is used to control and interact with the sequential pipeline processor and the integrated computing and storage data cache (CIM D-Cache), and adjust the design of the instruction cache (I-Cache) and the instruction fetch structure of the sequential pipeline processor to support the operation of the integrated computing and storage arbiter, thereby realizing the CPU equipped with the integrated computing and storage cache, achieving a higher energy efficiency ratio, and thus improving chip efficiency.

[0019] If the current instruction is not a load instruction, it means that the memory will not be accessed, and the Enable signal of the storage-computation arbitrator is set to 0 through the AND gate. If the current instruction is a load instruction, the storage-computation arbitrator obtains the memory access address (addr) of the current instruction through the adder. The simple decoder decodes the next n instructions (Next_Insts) of the current instruction, and the decoding result and addr are passed to the comparator array and control module to determine whether a storage-computation operation is required, and if a storage-computation operation is required, which instruction is required, and the data of the instruction is stored as storage-computation data (CIM Data) through the multiplexer, and passed to the storage-computation data cache (CIM-D-Cache) for operation.

[0020] The storage-computing arbiter receives data transferred by the decoder. If the instruction is not a memory access instruction, the data 0 is passed to one input of the AND gate, and the output of the AND gate must be 0. The data of the AND gate is connected to the Enable signal, and the Enable signal is pulled low, and the storage-computing operation will not be performed. If it is a memory access instruction, the data 1 is passed to one input of the AND gate. At this time, whether the output signal Enable of the AND gate is 1 depends on the other input of the AND gate (from the control module).

[0021] The subsequent instructions (hereinafter collectively referred to as Next_Insts) passed back by the I-Cache are passed to the simple decoder (Simple Decoder) in the storage and computing integrated arbitrator together with the data passed by the register file (RegFile). The operands and types of Next Insts are decoded and passed to the comparator array. A comparison value in the comparator array is the output of the adder, that is, the memory access address of the current instruction (Current Inst).

[0022] Assume that the CIM-D-Cache we need to carry supports the in-memory Boolean OR operation. That is, the OR operation can be performed inside the memory. (The same applies to AND, XOR, IMC, etc.). The OR instruction, also known as the OR instruction, allows the user to perform a logical "OR" operation on one or more input signals. As long as one of the signals is true, the output signal is true. The ORI instruction, also known as the OR inverse instruction or the NOT instruction, outputs a false signal only when all input signals are false.

[0023] The comparator array result output of the storage-computation arbitrator has priority. First, compare the next instruction following the current instruction (Current Inst). Assuming that the Current Inst is recorded as the i-th instruction, first compare the i+1th instruction to determine whether the i+1th instruction uses the register written back to the register file (RegFile) by the Current Inst. If it does, determine whether the type of the i+1th instruction is an OR or ORI instruction. If so, determine whether the register written back to the register file by the i+1th instruction is the same as the i-th instruction. If they are the same, the i+1th instruction can be merged into the current instruction (the i-th instruction), that is, the current instruction needs to perform a storage-computation operation.

[0024] If the i+1th instruction uses the register in the register stack written back by Current Inst, but it is not an operation instruction supported by our storage-computation data cache (the operation instructions supported by CIM-D-Cache here are OR and ORI instructions), then the storage-computation operation cannot be performed, and the subsequent i+2, i+3, ..., i+n instructions do not need to be compared (the comparison result is meaningless).

[0025] Finally, the data of the instructions that can be merged are stored in the storage and computing data (CIM Data) of the storage and computing arbitrator through the multiplexer (MUX) of the storage and computing arbitrator, and are transmitted to the memory access level of the sequential pipeline processor through the pipeline together with the Enable signal, and are transmitted to the storage and computing data cache (CIM-D-Cache) through the memory access structure.

[0026] By adding a storage-computing integrated arbiter and a storage-computing integrated data cache, when the sequential pipeline processor runs to a load-type instruction and detects that the instruction is followed by n related instructions, the following n related instructions can be moved together to the storage-computing integrated data cache for execution. In terms of time, it is equivalent to completing n+1 instructions in the time of using 1 instruction, which significantly improves CPU performance and power consumption.

[0027] The advantage of the RISC-V CPU architecture supporting storage-computing integrated cache designed in the present invention is that it can support and carry the storage-computing integrated cache, utilize the in-memory computing characteristics of the storage-computing integrated data cache and the customized instruction cache and storage-computing integrated arbiter to merge instructions that can be merged, thereby improving the pipeline processing efficiency and reducing energy consumption, and according to the supported operation type of the storage-computing integrated memory that needs to be carried, the adaptation can be completed by simply adjusting the comparison module in the arbitrator.

[0028] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A RISC-V CPU architecture supporting storage and computing integrated cache, characterized in that: It includes a sequential pipeline processor, a storage-computing integrated data cache, an instruction cache, and a storage-computing integrated arbitrator; The sequential pipeline processor adopts the RISC-V instruction set, and its structure is divided into a five-level pipeline structure: instruction fetch, decoding, execution, memory access / storage calculation, and write back; The instruction cache adopts a low-order cross pre-fetch instruction cache, which is composed of multiple columns of storage, and the instructions are continuously stored in adjacent bodies. At the same time, it is equipped with a pre-fetch function. The instruction cache is used to receive the instruction fetch signal transmitted by the sequential pipeline processor to fetch the instruction and return the instruction to the sequential pipeline processor; The storage-computing integrated arbitrator is used to control and interact with the sequential pipeline processor and the storage-computing integrated data cache, and adjust the instruction cache and the instruction fetch structure of the sequential pipeline processor to support the operation of the storage-computing integrated arbitrator. If the instruction returned to the sequential pipeline processor is a memory access instruction, the storage-computing integrated arbitrator can obtain the memory access address of the memory access instruction and decode the next n instructions of the current instruction corresponding to the memory access instruction, and determine whether a storage-computing integrated operation is required based on the decoding result and the memory access address. If it is determined that a storage-computing integrated operation is required, the storage-computing integrated arbitrator selects the data of the instruction that needs to be stored in the storage-computing integrated operation as storage-computing data, and passes it to the storage-computing integrated data cache.

2. The RISC-V CPU architecture according to claim 1, characterized in that: When accessing a certain data block in the instruction cache, the branch predictor of the sequential pipeline processor can fetch a single or multiple data blocks following the data block and put them into the instruction cache.

3. The RISC-V CPU architecture according to claim 1, characterized in that: When the instruction cache receives the instruction fetch signal transmitted by the sequential pipeline processor, it can take out the current instruction and put it into the current instruction part, and take out the instructions that follow the current instruction in the remaining instructions of the block where the current instruction is located, and put them into the predicted instruction part according to the instruction order, and transmit the instructions of the current instruction part and the predicted instruction part to the sequential pipeline processor.

4. The RISC-V CPU architecture according to claim 1, characterized in that: The sequential pipeline processor receives the current instruction and multiple subsequent predicted instructions returned by the instruction cache, and the current instruction flows into the decoding stage in sequence. The decoder of the sequential pipeline processor determines the type of instruction based on the RISC-V opcode of the RISC-V instruction set. If the instruction is a memory access instruction, the storage-computing integrated arbitrator is required to perform arbitration judgment.

5. The RISC-V CPU architecture according to claim 1, characterized in that: The storage-computing integrated arbitrator includes: an adder, a simple decoder, a comparator array, a control module, and a multiplexer; if the instruction returned to the sequential pipeline processor is a memory access instruction, the storage-computing integrated arbitrator can obtain the memory access address of the memory access instruction through the adder, and the simple decoder can decode the subsequent n instructions of the current instruction corresponding to the memory access instruction, and the decoding result and the memory access address are passed to the comparator array and the control module to determine whether a storage-computing integrated operation is required. If it is determined that a storage-computing integrated operation is required, the data of the instruction that needs to be stored and calculated is stored as storage-computing data through the multiplexer of the storage-computing integrated arbitrator, and is passed to the storage-computing integrated data cache through the memory access structure of the sequential pipeline processor.

Images