RISC-V context switching optimization method, equipment and medium

Abstract

The invention discloses an RISC-V context switching optimization method and device and a medium, and belongs to the technical field of processors. The method comprises the steps of executing a current task based on the computing core; when a context switching operation is triggered, determining the residual space of the register stack based on the numerical value of the stack top register; judging whether the register stack can store the current task or not based on the residual space and the current task; if not, storing the current task based on the memory; if yes, storing the current task based on the register stack; and executing a replacement task based on the computing core, and switching back to the current task through the stack top register when the replacement task is completed. According to the method, the effect of improving the context switching speed in the RISC-V is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of processors, and in particular to a RISC-V context switching optimization method, device and medium. Background Art

[0002] Due to its modularity, scalability and open source features, the RISC-V instruction set architecture can flexibly add different extended instruction sets to implement the computing core of the CPU or GPU, and has shown great application potential in many computing fields such as embedded RISC-V context switch optimization systems, personal computers, servers and GPU acceleration devices. In the CPU architecture, context switching occurs in scenarios such as software interrupts, hardware interrupts, hardware failures or task scheduling, saving the state of the current process and then loading the state of another process to continue execution. In the GPU architecture, context switching also occurs in scenarios such as interrupt processing, task scheduling, thread scheduling or thread synchronization. Whether it is the CPU or the GPU, context switching occurs frequently during program execution.

[0003] The stacks in the prior art are all defined in the memory. The data push operation is to save the data in the general register to the memory stack, and the data pop operation is to load the data from the memory stack to the general register. The read and write speed of the general register is basically close to the frequency of the computing core, but the read and write speed of the memory is much lower than the frequency of the computing core. Limited by the propagation speed of electrical signals in semiconductor materials, the higher the frequency of the computing core, the greater the speed gap. If the context switching speed is not fast enough, it will have a great impact on the program's response speed, overall performance, overall energy consumption and user experience.

[0004] Therefore, how to improve the context switching speed in RISC-V becomes a technical problem that needs to be solved urgently. Summary of the invention

[0005] The embodiments of the present application provide a RISC-V context switching optimization method, device and medium to solve the following technical problem: how to improve the context switching speed in RISC-V.

[0006] In the first aspect, an embodiment of the present application provides a RISC-V context switch optimization method, characterized in that it is applied to a RISC-V context switch optimization system, the RISC-V context switch optimization system includes a computing core and a memory, the computing core includes a control unit, a register stack, a top register, a general register and an arithmetic logic unit, and the method includes: executing the current task based on the computing core; when the context switch operation is triggered, determining the remaining space of the register stack based on the value of the top register; judging whether the register stack can save the current task based on the remaining space and the current task; if not, storing the current task based on the memory; if so, storing the current task based on the register stack; executing a replacement task based on the computing core, and switching back to the current task through the top register when the replacement task is completed.

[0007] In one implementation of the present application, when a context switch operation is triggered, before determining the remaining space of the register stack based on the value of the top register of the stack, the method also includes: monitoring interrupt signals, exception signals or task scheduling instructions based on the control unit to determine whether to trigger the execution context switch; monitoring the current task based on a preset behavior prediction module to determine future behavior characteristics; and adjusting the remaining space of the register stack based on the prediction result and the current task.

[0008] In one implementation of the present application, the current task is monitored based on a preset behavior prediction module to determine future behavior characteristics, specifically including: collecting execution data of the current task; wherein the execution data includes instruction execution frequency, memory access mode and I / O operation; processing the execution data based on the behavior prediction module to identify the behavior pattern of the current task; determining the future behavior characteristics of the current task based on the behavior pattern; wherein the future behavior characteristics include execution time, replacement tasks and occupied stack size.

[0009] In one implementation of the present application, the remaining space of the register stack is adjusted based on future behavior characteristics and the current task, specifically including: based on the future behavior characteristics and the current task, evaluating the demand for the register stack of the current task in the subsequent execution process; comparing the demand with the remaining space of the register stack to determine the registration difference, and determining the adjustment method based on the registration difference; wherein the adjustment method includes expansion adjustment and compression adjustment; when the adjustment method is expansion adjustment, the remaining space of the register stack is expanded based on the registration difference; when the adjustment method is compression adjustment, the remaining space of the register stack is compressed based on the registration difference.

[0010] In one implementation of the present application, the method further includes: after the adjustment mode is executed, updating the value of the top register of the stack.

[0011] In one implementation of the present application, before processing the execution data based on the behavior prediction module to identify the behavior pattern of the current task, the method also includes: obtaining context switching data, and preprocessing the context switching data to construct a training set, a test set, and a validation set; wherein the preprocessing includes: data cleaning, feature extraction, and standardization processing; training a preset deep neural network based on the training set; validating the trained deep neural network based on the validation set and the test set, and outputting it as a behavior prediction module when the accuracy is greater than a preset behavior threshold.

[0012] In one implementation of the present application, when a context switching operation is triggered, the remaining space of the register stack is determined based on the value of the top register, specifically including: reading the current value of the top register to determine the top address of the register stack; obtaining the base address of the register stack; calculating the difference between the top address and the base address to determine the usage of the register stack; and calculating the remaining space of the register stack based on the total capacity and usage of the register stack.

[0013] In one implementation of the present application, a replacement task is executed based on a computing core, and when the replacement task is completed, the current task is switched back through a stack top register, specifically including: executing the replacement task based on the computing core, and monitoring whether a context operation is triggered; when the replacement task is completed and it is necessary to switch back to the current task, saving the context information of the replacement task; locating the storage location of the context information of the current task based on the value of the stack top register to restore the context information of the current task to the technical core; executing the current task based on the technical core until the current task is completed or a context switching operation is triggered.

[0014] In the second aspect, an embodiment of the present application also provides a RISC-V context switching optimization device, characterized in that the device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can: execute the current task based on the computing core; when the context switching operation is triggered, determine the remaining space of the register stack based on the value of the top register of the stack; determine whether the register stack can save the current task based on the remaining space and the current task; if not, store the current task based on the memory; if so, store the current task based on the register stack; execute a replacement task based on the computing core, and switch back to the current task through the top register of the stack when the replacement task is completed.

[0015] In a third aspect, an embodiment of the present application further provides a RISC-V context switching optimized non-volatile computer storage medium storing computer executable instructions, characterized in that the computer executable instructions are configured to: execute the current task based on the computing core; when the context switching operation is triggered, determine the remaining space of the register stack based on the value of the top register; determine whether the register stack can save the current task based on the remaining space and the current task; if not, store the current task based on the memory; if so, store the current task based on the register stack; execute a replacement task based on the computing core, and switch back to the current task through the top register when the replacement task is completed.

[0016] A RISC-V context switching optimization method, device, and medium provided in an embodiment of the present application include at least the following technical effects:

[0017] When a context switch operation is triggered, the value of the top register is used to accurately determine the remaining space in the register stack, so that the usage of the stack can be monitored in real time, providing accurate data support for subsequent task saving and switching.

[0018] According to the remaining space and the needs of the current task, it intelligently determines whether the register stack can save the current task. If the space is insufficient, it turns to the memory for storage, thus ensuring the complete preservation of the task status, making full use of the limited register stack resources, and ensuring the smooth progress of task switching.

[0019] By saving the state of the current task in the register stack or memory, the RISC-V context switch optimization system can quickly switch to the replacement task for execution. At the same time, after the replacement task is completed, the state of the current task is quickly restored through the top register of the stack, achieving seamless switching and continuous execution between tasks, reducing the performance overhead caused by task switching, and improving the overall operating efficiency of the RISC-V context switch optimization system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 A flow chart of a RISC-V context switching optimization method provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of the internal structure of a RISC-V context switching optimization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0024] The embodiments of the present application provide a RISC-V context switching optimization method, device and medium to solve the following technical problem: how to improve the context switching speed in RISC-V.

[0025] The technical solution proposed in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0026] Figure 1 A RISC-V context switch optimization flow chart provided in an embodiment of the present application. Figure 1 As shown, a RISC-V context switching optimization method provided in an embodiment of the present application specifically includes the following steps:

[0027] A flowchart corresponding to a RISC-V context switch optimization method is applied to a RISC-V context switch optimization system. The RISC-V context switch optimization system includes a computing core and a memory. The computing core includes a control unit, a register stack, a stack top register, a general register, and an arithmetic logic unit.

[0028] The computing core is the core part of the RISC-V context switching optimization system, responsible for executing instructions and processing data.

[0029] Control unit: The control unit is responsible for decoding instructions, controlling the execution order, and coordinating the work of other components. During the context switch process, the control unit is used to manage the task switching process to ensure that each task can be executed in a predetermined order and rules to a certain extent.

[0030] Register stack: The register stack is a component in the computing core used to store temporary data and intermediate results. When the context is switched, the register stack is used to save the state of the current task, including the value of the general register, the program counter and other key information.

[0031] Top of stack register: The top of stack register is used to record the top position of the register stack. During context switching, the value of the top of stack register is used to determine the position of the current task state in the stack. By reading the value of the top of stack register, the task state that needs to be saved or restored can be found.

[0032] General registers: General registers are temporary storage spaces in the computing core for storing operands and operation results. When the context is switched, the values ​​of the general registers need to be saved to the register stack so that these values ​​can be restored when the task is resumed.

[0033] Arithmetic Logic Unit (ALU): The Arithmetic Logic Unit is the component in the computing core that performs arithmetic and logic operations.

[0034] Memory: Memory is an integral part of the RISC-V context switch optimization system. Memory provides a large amount of storage space to save programs and data. During the context switch process, memory is used to store the tasks that are switched out.

[0035] Step 1: Execute the current task based on the computing core.

[0036] The RISC-V computing core is responsible for executing the current task. At the same time, the RISC-V context switch optimization system performs a series of monitoring and adjustment operations to ensure the efficiency of context switching and the smooth execution of tasks to a certain extent, which is specifically performed by the following steps.

[0037] A1. Based on the control unit monitoring interrupt signals, exception signals or task scheduling instructions to determine whether to trigger execution context switching. The control unit continuously monitors the RISC-V context switching optimization system interrupt signals, exception signals or task scheduling instructions. The above signals and instructions are potential trigger conditions for context switching. Once the above conditions are detected, the control unit will determine whether context switching needs to be executed.

[0038] A2. Monitor the current task based on the preset behavior prediction module to determine the future behavior characteristics. In order to optimize the context switching process, the RISC-V context switching optimization system uses a preset behavior prediction module to monitor the execution of the current task. This module predicts the future behavior characteristics of the task by collecting and analyzing the execution data of the task. This is specifically described in detail by steps A21 to A23.

[0039] A21. Collect the execution data of the current task, where the execution data includes instruction execution frequency, memory access mode, and I / O operation. The RISC-V context switch optimization system collects the execution data of the current task, where the execution data includes instruction execution frequency, memory access mode, and I / O operation. The above data provides detailed information on task behavior and is the basis for behavior prediction.

[0040] A22. Process the execution data based on the behavior prediction module to identify the behavior pattern of the current task. The behavior prediction module processes the collected execution data and identifies the behavior pattern of the task through the behavior prediction module. The behavior pattern reflects the regularity and characteristics of the task during execution.

[0041] A23. Determine the future behavior characteristics of the current task based on the behavior pattern; wherein the future behavior characteristics include execution time, replacement tasks, and occupied stack size. Based on the identified behavior pattern, the behavior prediction module determines the future behavior characteristics of the current task. The future behavior characteristics include the expected execution time, possible replacement tasks, and the expected occupied stack size.

[0042] B1 to B3 are used to illustrate the training process of the behavior prediction module.

[0043] B1. Obtain context switch data and preprocess the context switch data to construct training sets, test sets, and validation sets; wherein preprocessing includes: data cleaning, feature extraction, and standardization. The RISC-V context switch optimization system first obtains a large amount of context switch data and performs preprocessing operations, including data cleaning, feature extraction, and standardization. The above processing steps can help to build high-quality training sets, test sets, and validation sets to a certain extent.

[0044] B2. Train the preset deep neural network based on the training set. Using the constructed training set, the RISC-V context switch optimization system trains an existing deep neural network model. The deep neural network model gradually improves its ability to predict future behavior characteristics by learning the rules and patterns in the data.

[0045] B3. Verify the trained deep neural network based on the validation set and test set, and output it as a behavior prediction module when the accuracy is greater than the preset behavior threshold. After the training is completed, the RISC-V context switch optimization system verifies the model using the validation set and test set. When the accuracy of the model exceeds the preset behavior threshold, the RISC-V context switch optimization system outputs it as a usable behavior prediction module.

[0046] A3. Adjust the remaining space of the register stack based on future behavior characteristics and current tasks. Based on the future behavior characteristics provided by the behavior prediction module, the RISC-V context switch optimization system adjusts the remaining space of the register stack. The specific process is described by steps A31 to A35.

[0047] A31. Based on future behavior characteristics and the current task, evaluate the current task's need for the register stack during subsequent execution. The RISC-V context switch optimization system evaluates the task's need for the register stack during subsequent execution based on future behavior characteristics and the current task status.

[0048] A32. Compare the demand with the remaining space of the register stack to determine the register difference, and determine the adjustment method based on the register difference; wherein the adjustment method includes expansion adjustment and compression adjustment. By comparing the assessed demand with the remaining space of the current register stack, the RISC-V context switch optimization system determines a register value. Based on the register difference, the RISC-V context switch optimization system selects an appropriate adjustment method, including expansion adjustment and compression adjustment.

[0049] A33. When the adjustment mode is expansion adjustment, the remaining space of the register stack is expanded based on the registered difference.

[0050] A34. When the adjustment mode is compression adjustment, the remaining space of the register stack is compressed based on the stored difference.

[0051] A35. After the adjustment mode is executed, the value of the stack top register is updated. After the adjustment operation is completed, the RISC-V context switch optimization system updates the value of the stack top register to reflect the new stack top position.

[0052] Step 2: When a context switch operation is triggered, the remaining space of the register stack is determined based on the value of the top register of the stack.

[0053] First, read the current value of the top register to determine the top address of the register stack. The RISC-V context switch optimization system first reads the current value of the top register, which represents the current top address of the register stack, that is, the address of the last data item pushed into the stack.

[0054] Further, the base address of the register stack is obtained. Next, the RISC-V context switch optimization system obtains the base address of the register stack. The base address is the starting address of the stack, which identifies the location of the stack in memory.

[0055] Furthermore, the difference between the top address of the stack and the base address is calculated to determine the usage of the register stack. By calculating the difference between the top address of the stack and the base address, the RISC-V context switch optimization system can determine the current usage of the stack. This difference reflects the total number of data items from the bottom to the top of the stack, thereby indirectly indicating the usage of the stack.

[0056] Furthermore, the remaining space of the register stack is calculated based on the total capacity and usage of the register stack. After knowing the total capacity and usage of the stack, the RISC-V context switch optimization system can calculate the remaining space of the stack. The remaining space is the total capacity minus the usage, which indicates how many data items the stack can accommodate.

[0057] Step 3: Determine whether the register stack can save the current task based on the remaining space and the current task. After determining the remaining space of the register stack, the RISC-V context switch optimization system needs to determine whether this space is sufficient to save the state of the current task.

[0058] The RISC-V context switch optimization system estimates the stack space required to save the task state based on the complexity and state size of the current task, and compares the estimated required space with the remaining space calculated in step 2.

[0059] Step 4: If not, store the current task based on memory.

[0060] If the remaining space in the register stack is insufficient to save the state of the current task, the RISC-V context switch optimization system needs to take other measures to save the task state. The RISC-V context switch optimization system selects a memory area to save the state of the current task. The state information of the current task is saved in the selected memory area, and the RISC-V context switch optimization system records the location where the task state is saved in memory.

[0061] Step 5: If yes, store the current task based on the register stack. If the remaining space in the register stack is sufficient to save the state of the current task, the RISC-V context switch optimization system directly saves the task state to the stack.

[0062] Push the status information of the current task into the register stack. After the task status is pushed into the stack, the RISC-V context switch optimization system updates the value of the top stack register to reflect the new top stack position.

[0063] Step 6: Execute the replacement task based on the computing core, and switch back to the current task through the stack top register when the replacement task is completed. Once the state of the current task is saved, the RISC-V context switch optimization system can start executing the replacement task. When the replacement task is completed, the RISC-V context switch optimization system needs to restore and continue to execute the original current task through the stack top register.

[0064] First, the replacement task is executed based on the computing core, and the context operation is monitored to see if it is triggered. The RISC-V context switch optimization system starts executing the replacement task based on the computing core. During this process, the state of the current task is saved in the register stack or memory.

[0065] Further, when the replacement task is completed and it is necessary to switch back to the current task, the context information of the replacement task is saved.

[0066] Furthermore, the context information storage location of the current task is located based on the value of the top stack register to restore the context information of the current task to the technical core. When the replacement task is executed, the RISC-V context switch optimization system finds the status of the current task by reading the previously saved top stack register value or memory location information. Then, the RISC-V context switch optimization system restores this status information to the corresponding register and processor status.

[0067] Further, the current task is executed based on the technology core until the current task is completed or a context switch operation is triggered. Once the state of the current task is restored, the RISC-V context switch optimization system continues to execute the current task.

[0068] The above is an embodiment of the method proposed in this application. Based on the same inventive concept, the embodiment of this application also provides a RISC-V context switching optimization device, whose structure is as follows Figure 2 shown.

[0069] Figure 2 A schematic diagram of the internal structure of a RISC-V context switch optimization device provided in an embodiment of the present application. Figure 2 As shown, the device includes:

[0070] at least one processor 201;

[0071] and, a memory 202 communicatively connected to the at least one processor;

[0072] The memory 202 stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor 201 to enable at least one processor 201 to:

[0073] Execute the current task based on the computing core; when the context switch operation is triggered, determine the remaining space of the register stack based on the value of the top register; determine whether the register stack can save the current task based on the remaining space and the current task; if not, store the current task based on the memory; if so, store the current task based on the register stack; execute the replacement task based on the computing core, and switch back to the current task through the top register when the replacement task is completed.

[0074] Some embodiments of the present application provide corresponding Figure 1 A RISC-V context switch optimized non-volatile computer storage medium stores computer executable instructions, wherein the computer executable instructions are set to:

[0075] Execute the current task based on the computing core; when the context switch operation is triggered, determine the remaining space of the register stack based on the value of the top register; determine whether the register stack can save the current task based on the remaining space and the current task; if not, store the current task based on the memory; if so, store the current task based on the register stack; execute the replacement task based on the computing core, and switch back to the current task through the top register when the replacement task is completed.

[0076] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the IoT device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0077] The RISC-V context switch optimization system and medium provided in the embodiments of the present application correspond one-to-one to the method. Therefore, the RISC-V context switch optimization system and medium also have similar beneficial technical effects to the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the RISC-V context switch optimization system and medium will not be repeated here.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, RISC-V context switch optimization systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (RISC-V context switch optimization system) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0083] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0084] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0085] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0086] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A RISC-V context switching optimization method, characterized in that: Applied to a RISC-V context switch optimization system, the RISC-V context switch optimization system includes a computing core and a memory, the computing core includes a control unit, a register stack, a stack top register, a general register and an arithmetic logic unit, the method includes: Execute the current task based on the computing core; When a context switch operation is triggered, determining the remaining space of the register stack based on the value of the top register of the stack; Determining whether the register stack can save the current task based on the remaining space and the current task; If not, storing the current task based on the memory; If so, storing the current task based on the register stack; A replacement task is executed based on the computing core, and when the replacement task is completed, the current task is switched back through the stack top register.

2. A RISC-V context switching optimization method according to claim 1, characterized in that: When a context switch operation is triggered, before determining the remaining space of the register stack based on the value of the top register, the method further includes: Based on the control unit monitoring the interrupt signal, abnormal signal or task scheduling instruction to determine whether to trigger the execution context switch; Monitoring the current task based on a preset behavior prediction module to determine future behavior characteristics; The remaining space of the register stack is adjusted based on the future behavior characteristics and the current task.

3. A RISC-V context switching optimization method according to claim 2, characterized in that: The current task is monitored based on a preset behavior prediction module to determine future behavior characteristics, specifically including: Collecting execution data of the current task; wherein the execution data includes instruction execution frequency, memory access mode and I / O operation; Processing the execution data based on the behavior prediction module to identify a behavior pattern of the current task; Determine the future behavior characteristics of the current task based on the behavior pattern; wherein the future behavior characteristics include execution time, replacement tasks and occupied stack size.

4. A RISC-V context switching optimization method according to claim 3, characterized in that: Adjusting the remaining space of the register stack based on the future behavior characteristics and the current task specifically includes: Based on the future behavior characteristics and the current task, evaluating the need of the current task for a register stack during subsequent execution; Comparing the demand with the remaining space of the register stack to determine a register difference, and determining an adjustment method based on the register difference; wherein the adjustment method includes expansion adjustment and compression adjustment; When the adjustment mode is the expansion adjustment, expanding the remaining space of the register stack based on the register difference; When the adjustment mode is the compression adjustment, the remaining space of the register stack is compressed based on the register difference.

5. A RISC-V context switching optimization method according to claim 3, characterized in that: The method further comprises: After the adjustment mode is executed, the value of the stack top register is updated.

6. A RISC-V context switching optimization method according to claim 3, characterized in that: Before processing the execution data based on the behavior prediction module to identify the behavior pattern of the current task, the method further includes: Acquire context switching data, and preprocess the context switching data to construct a training set, a test set, and a validation set; wherein the preprocessing includes: data cleaning, feature extraction, and standardization processing; Training a preset deep neural network based on the training set; The trained deep neural network is verified based on the verification set and the test set, and is output as a behavior prediction module when the accuracy is greater than a preset behavior threshold.

7. A RISC-V context switching optimization method according to claim 1, characterized in that: When a context switch operation is triggered, determining the remaining space of the register stack based on the value of the top register of the stack specifically includes: Reading the current value of the top register to determine the top address of the register stack; Get the base address of the register stack; Calculating the difference between the stack top address and the base address to determine the usage of the register stack; The remaining space of the register stack is calculated according to the total capacity and usage of the register stack.

8. A RISC-V context switching optimization method according to claim 1, characterized in that: Executing a replacement task based on the computing core, and switching back to the current task through the stack top register when the replacement task is completed, specifically includes: executing the replacement task based on the computing core, and monitoring whether a context operation is triggered; When the replacement task is completed and it is necessary to switch back to the current task, save the context information of the replacement task; Locating a storage location of the context information of the current task based on the value of the stack top register to restore the context information of the current task to the technical core; The current task is executed based on the technology core until the current task is completed or a context switching operation is triggered.

9. A RISC-V context switch optimization device, characterized in that: The device comprises: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to: Execute the current task based on the computing core; When a context switch operation is triggered, determining the remaining space of the register stack based on the value of the top register of the stack; Determining whether the register stack can save the current task based on the remaining space and the current task; If not, storing the current task based on the memory; If so, storing the current task based on the register stack; A replacement task is executed based on the computing core, and when the replacement task is completed, the current task is switched back through the stack top register.

10. A RISC-V context switch optimized non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to: Execute the current task based on the computing core; When a context switch operation is triggered, determining the remaining space of the register stack based on the value of the top register of the stack; Determining whether the register stack can save the current task based on the remaining space and the current task; If not, storing the current task based on the memory; If so, storing the current task based on the register stack; A replacement task is executed based on the computing core, and when the replacement task is completed, the current task is switched back through the stack top register.

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