DPU power consumption control method and device, chip, electronic equipment and storage medium
Dynamic CPU core load rate adjustment in DPUs reallocates task queues and puts underutilized cores to sleep, addressing excessive power consumption in low traffic scenarios and optimizing DPU efficiency.
Patent Information
- Application Number
- CN202310713439.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2024-12-17
AI Technical Summary
Existing DPUs with multiple CPU cores consume excessive power when network traffic is low due to all cores being enabled, despite varying load rates, leading to inefficient power usage.
Dynamically adjust CPU core load rates by reallocating task queues from underutilized cores to more capable cores and putting underutilized cores into a dormant state when their load rate falls below a threshold, and waking up dormant cores when their load rate exceeds a threshold.
Optimizes DPU power consumption by reducing power usage during low network traffic while maintaining performance through dynamic load balancing.
Smart Images
Figure CN119149214A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a DPU power consumption control method, device, chip, electronic device and storage medium. Background Art
[0002] DPU (Data Processing Unit) is a data-centric dedicated processor that completes network, storage, and security acceleration processing tasks. At present, in order to achieve high-performance operation of DPU, the task queues in DPU are usually evenly distributed to different CPU cores, and will not be dynamically adjusted according to the load rate of the CPU core. For DPUs with more CPU cores, if the current actual network traffic is relatively low and the CPU core load rate is relatively low, all CPU cores are still enabled, which will result in higher DPU power consumption. Summary of the invention
[0003] The present application provides a DPU power consumption control method, device, chip, electronic device and storage medium to dynamically adjust the load rate of multiple CPU cores included in the DPU, thereby optimizing the DPU power consumption and achieving the technical effect of reducing the power consumption of the DPU.
[0004] According to one aspect of the present application, a DPU power consumption control method is provided, wherein the DPU includes multiple CPU cores, and the method includes:
[0005] Monitoring the load rates of the multiple CPU cores;
[0006] When the load rate of at least one CPU core to be controlled is less than a lower limit threshold, determining a corresponding first target CPU core among the multiple CPU cores except the CPU core to be controlled;
[0007] The task queue of the CPU core to be controlled is allocated to the first target CPU core, and the CPU core to be controlled is controlled to enter a dormant state.
[0008] According to another aspect of the present application, a DPU power consumption control device is provided. The DPU includes multiple CPU cores, and the device includes:
[0009] A load rate determination module, used to monitor the load rates of the multiple CPU cores;
[0010] A first CPU core determination module, configured to determine a corresponding first target CPU core among the plurality of CPU cores except the CPU core to be controlled when the load rate of at least one CPU core to be controlled is less than a lower limit threshold;
[0011] The first CPU core control module is used to allocate the task queue of the CPU core to be controlled to the first target CPU core, and control the CPU core to be controlled to enter a sleep state.
[0012] According to another aspect of the present application, a chip is provided, the chip comprising:
[0013] A processor, which is used to execute computer program instructions stored in a memory, wherein when the computer program instructions are executed by the processor, the chip is triggered to execute the DPU power consumption control method described in any embodiment of the present application.
[0014] According to another aspect of the present application, an electronic device is provided, and the electronic device includes the chip provided in another aspect of the present application.
[0015] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the DPU power consumption control method described in any embodiment of the present application when executed.
[0016] The technical solution of the embodiment of the present application dynamically adjusts the load rates of the multiple CPU cores of the DPU by assigning the task queue of the CPU core to be controlled whose load rate is less than the lower limit threshold to the first target CPU core determined among the multiple CPU cores other than the CPU core to be controlled, and then controlling the CPU core to be controlled to enter a sleep state, thereby optimizing the power consumption of the DPU and achieving the technical effect of reducing the power consumption of the DPU.
[0017] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 A flowchart of a DPU power consumption control method provided in one embodiment of the present application;
[0020] Figure 2 A schematic diagram of a flow chart of a DPU power consumption control method provided in another embodiment of the present application;
[0021] Figure 3 A schematic diagram of the structure of a DPU power consumption control device provided in another embodiment of the present application;
[0022] Figure 4 A schematic diagram of the structure of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION
[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0025] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.
[0026] The DPU power consumption control method described in the present application is applied to a scenario in which the power consumption of a DPU including multiple CPU cores is controlled. The method can be performed by a DPU power consumption control device. The DPU power consumption control device can be configured in a DPU, and the DPU can be configured in an electronic device such as a computer or a server.
[0027] Figure 1 A flow chart of a DPU power consumption control method provided in an embodiment of the present application. Figure 1 As shown, the method of this embodiment includes:
[0028] S110: Monitor the load rates of the multiple CPU cores.
[0029] In an embodiment of the present application, the load rate of the CPU core may be the load rate of the CPU core at a certain point in time; or, it may be the average load rate of the CPU core in a certain time period. The load rate of the CPU core may characterize the busyness of the CPU core at a certain point in time or in a certain time period. In this embodiment, the load rate of the CPU core may be the busyness of the CPU core at the current moment or in the current period. The current period may be a period of a preset time from the current moment. In actual applications, the greater the load rate of the CPU core, the busier the CPU core is; conversely, the smaller the load rate of the CPU core, the less busy the CPU core is.
[0030] In an embodiment of the present application, monitoring the load rates of the multiple CPU cores may include: upon receiving a power consumption control instruction for the DPU, monitoring the load rates of the multiple CPU cores in the DPU based on the power consumption control instruction. The power consumption control instruction may be understood as an instruction for monitoring the load rates of the CPU cores in the DPU.
[0031] Optionally, the monitoring of the load rates of the multiple CPU cores in the DPU based on the power consumption control instruction may include: based on the power consumption control instruction, calling a predefined CPU core load rate monitoring method to monitor the load rates of the multiple CPU cores in the DPU. The CPU core load rate monitoring method may be understood as a predefined method for monitoring the load rates of the multiple CPU cores in the DPU.
[0032] Among them, based on the power consumption control instruction, calling a predefined CPU core load rate monitoring method to monitor the load rate of multiple CPU cores in the DPU may include: parsing the power consumption control instruction to obtain the identification of each CPU core in the DPU. The identification of each CPU core is passed as an actual parameter to the formal parameter of the CPU core load rate monitoring method. After the parameter passing is completed, the CPU core load rate monitoring method can be executed to monitor the load rate of multiple CPU cores in the DPU.
[0033] Optionally, the monitoring of the load rates of the multiple CPU cores in the DPU based on the power consumption control instruction may include: monitoring the load rates of the multiple CPU cores in the DPU based on a preset load rate monitor. The load rate monitor may be set in the DPU. Optionally, the load rate monitor may be set in the main CPU core in the DPU. Accordingly, monitoring the load rates of the multiple CPU cores in the DPU may include: monitoring the load rates of the multiple slave CPU cores in the DPU.
[0034] In an embodiment of the present application, a specific method for obtaining the load rate of multiple CPU cores may include: for each CPU core, the task queue to which the CPU core is bound may be determined; and then the load rate of the task queue may be determined based on the task volume and queue capacity of the task queue, that is, the load rate of the CPU core is obtained. The task volume may be understood as the number of tasks that need to be executed in the task queue. The queue capacity may be understood as the maximum number of tasks that can be stored in the task queue.
[0035] S120. When the load rate of at least one CPU core to be controlled is less than a lower threshold, determine a corresponding first target CPU core among the multiple CPU cores except the CPU core to be controlled.
[0036] Among them, the CPU core to be controlled can be understood as a CPU core that needs to be controlled among multiple CPU cores. The number of CPU cores to be controlled can be one, two or more. It should be noted that the state of the CPU core to be controlled in the DPU is a working state. In other words, the load rate of the CPU core to be controlled is greater than zero. The lower limit threshold can be understood as the load rate at which the CPU core to be controlled enters sleep. The lower limit threshold can be a lower limit threshold pre-set for the load of the CPU core. There are many ways to obtain the lower limit threshold, which is not specifically limited here. For example, it can be obtained based on manual configuration by the user. The first target CPU core can be understood as a CPU core used to execute tasks in the task queue of the CPU core to be controlled. The correspondence between the CPU core to be controlled and the first target CPU core can be one-to-one or one-to-many.
[0037] Specifically, at least one CPU core to be controlled among the multiple CPU cores is determined. For each CPU core to be controlled, the load rate of the CPU core to be controlled can be compared with a lower threshold. If the load rate of the CPU core to be controlled is less than the lower threshold, a first target CPU core corresponding to the CPU core to be controlled can be determined among the multiple CPU cores except the CPU core to be controlled.
[0038] Optionally, there are multiple ways to determine the CPU core to be controlled among the multiple CPU cores, which are not specifically limited here. Exemplarily, at least one CPU core can be randomly selected from the multiple CPU cores, and the selected CPU core can be used as the CPU core to be controlled; or, the CPU core to be controlled can be selected from the multiple CPU cores based on the load rates of the multiple CPU cores. Optionally, based on the load rates of the multiple CPU cores, selecting the CPU core to be controlled from the multiple CPU cores can include: using a CPU core with a load rate greater than zero among the multiple CPU cores as the CPU core to be controlled; or, using a CPU core with the largest load rate among the multiple CPU cores as the CPU core to be controlled; or, using a CPU core with the smallest load rate and greater than zero among the multiple CPU cores as the CPU core to be controlled.
[0039] In one embodiment, determining the corresponding first target CPU core among the multiple CPU cores except the CPU core to be controlled may include: determining the remaining computing power of each CPU core among the multiple CPU cores except the CPU core to be controlled; if the remaining computing power matches the total amount of tasks of the CPU core to be controlled, the CPU core may be used as the first target CPU core corresponding to the CPU core to be controlled. The remaining computing power matches the total amount of tasks of the CPU core to be controlled, which can be understood as the CPU core with the remaining computing power being able to process the tasks of the total amount of tasks.
[0040] In another embodiment, determining the corresponding first target CPU core among the multiple CPU cores except the CPU core to be controlled may include: obtaining the remaining computing power of each CPU core among the multiple CPU cores except the CPU core to be controlled; and selecting the CPU core with the largest remaining computing power as the first target CPU core.
[0041] Among them, the remaining computing power can be used to evaluate the load of the CPU core. In an embodiment of the present application, the specific way to obtain the remaining computing power of each CPU core can be to determine the maximum computing power and occupied computing power of each CPU core; for each CPU core, the difference between the maximum computing power and the occupied computing power of the CPU core can be used as the remaining computing power of the CPU core. The occupied computing power can be understood as the computing power that the current CPU core already has. It can be understood that the greater the remaining computing power, the less the load on the CPU core; conversely, the smaller the remaining computing power, the greater the load on the CPU core. It should be noted that the purpose of selecting the CPU core with the largest remaining computing power as the first target CPU core is that all tasks of the CPU core to be controlled can be assigned to the first target CPU core.
[0042] Optionally, selecting the CPU core with the largest remaining computing power as the first target CPU core may include: when there are multiple CPU cores with the largest remaining computing power, randomly selecting a CPU core from the multiple CPU cores with the largest remaining computing power as the first target CPU core corresponding to the CPU core to be controlled.
[0043] Optionally, selecting the CPU core with the largest remaining computing power as the first target CPU core may include: when there are multiple CPU cores with the largest remaining computing power, selecting at least two CPU cores from the multiple CPU cores with the largest remaining computing power as the first target CPU cores corresponding to the CPU core to be controlled.
[0044] S130 , allocating the task queue of the CPU core to be controlled to the first target CPU core, and controlling the CPU core to be controlled to enter a sleep state.
[0045] The task queue of the CPU core to be controlled can be understood as a queue for storing tasks that need to be executed by the CPU core to be controlled. The number of the task queues of the CPU core to be controlled can be one, two, or more than two.
[0046] In an embodiment of the present application, the number of task queues corresponding to different CPU cores to be controlled may be the same or different. Exemplarily, the CPU cores to be controlled in the DPU may include a first CPU core, a second CPU core, and a third CPU core. Among them, the number of task queues of the first CPU core may be two, the number of task queues of the second CPU core may be two, and the number of task queues of the third CPU core may be three.
[0047] In the embodiment of the present application, the task queue of the CPU core to be controlled is assigned to the first target CPU core. It can be understood that the first target CPU core can access the task queue of the CPU core to be controlled and execute the tasks in the task queue.
[0048] Optionally, the allocating the task queue of the CPU core to be controlled to the first target CPU core may include: if there are multiple task queues of the CPU core to be controlled and multiple first target CPU cores, determining the total amount of tasks of the task queue for each task queue of the CPU core to be controlled; determining a first target CPU core whose remaining computing capacity matches the total amount of tasks from multiple first target CPU cores, and allocating the task queue of the CPU core to be controlled to the determined first target CPU core.
[0049] It should be noted that the advantage of controlling the CPU core to be controlled to enter a dormant state is that the CPU core to be controlled can be made to not generate power consumption, thereby achieving the technical effect of reducing the power consumption of the DPU.
[0050] In an embodiment of the present application, before allocating the task queue of the CPU core to be controlled to the first target CPU core, the method may further include: recording the task queue of the CPU core to be controlled using a hash table. That is, the task queue of the CPU core to be controlled is recorded in the form of a key-value pair. Using a hash table to record the task queue of the CPU core to be controlled can more clearly reflect the association between the CPU core to be controlled and the task queue. In addition, in the case where the CPU core to be controlled is bound to multiple task queues, the task queue bound to the CPU core to be controlled can also be determined more quickly to facilitate the management of the task queue bound to the CPU core to be controlled.
[0051] In the embodiment of the present application, there are many ways to record the task queue of the CPU core to be controlled in the form of key-value pairs, which are not specifically limited here.
[0052] As an optional implementation of the embodiment, the task queue of the CPU core to be controlled is recorded in the form of a key-value pair, which may include: in the case where the CPU core to be controlled includes a task queue, for the CPU core to be controlled, the identifier of the CPU core to be controlled and the identifier of a task queue of the CPU core to be controlled can be used as the key and value in the key-value pair respectively, that is, the identifier of the CPU core to be controlled is used as the key in the key-value pair, and the identifier of a task queue of the CPU core to be controlled is used as the value in the key-value pair. In other words, a key-value pair may include the identifier of a CPU core to be controlled and the identifier of a task queue of the CPU core to be controlled.
[0053] As another optional implementation of the embodiment, the task queue of the CPU core to be controlled is recorded in the form of a key-value pair, which may include: when the CPU core to be controlled includes multiple task queues, for each CPU core to be controlled, the identifier of the CPU core to be controlled and the identifiers of the multiple task queues of the CPU core to be controlled can be used as the key and value in the key-value pair respectively. In other words, a key-value pair can include the identifier of a CPU core to be controlled and the identifiers of all task queues of the CPU core to be controlled. It can be understood that, when the value in a key-value pair includes the identifiers of multiple task queues, the identifiers of each task queue can be spliced with a preset spacer to effectively identify the identifiers of each task queue. Among them, the preset spacer can be set according to actual needs, and is not specifically limited here. For example, the preset spacer can be "-", "+" or ".", etc.
[0054] The technical solution of the embodiment of the present application dynamically adjusts the load rates of the multiple CPU cores of the DPU by assigning the task queue of the CPU core to be controlled whose load rate is less than the lower limit threshold to the first target CPU core determined among the multiple CPU cores other than the CPU core to be controlled, and then controlling the CPU core to be controlled to enter a sleep state, thereby optimizing the power consumption of the DPU and achieving the technical effect of reducing the power consumption of the DPU.
[0055] Figure 2A flowchart of a DPU power consumption control method provided for another embodiment of the present application. Based on the aforementioned embodiment, optionally, the DPU power consumption control method provided in this embodiment also includes: when the load rate of at least one CPU core to be controlled is greater than an upper limit threshold, determining a corresponding second target CPU core in the dormant CPU core; waking up the second target CPU core, and allocating part of the task queues of the CPU core to be controlled to the second target CPU core, wherein the part of the task queues is a task queue whose load rate of the CPU core to be controlled is greater than the upper limit threshold. Wherein, Figure 2 The embodiment shown and Figure 1 For the same or similar technical features as shown in the embodiments, please refer to Figure 1 The detailed description of the illustrated embodiment will not be repeated here.
[0056] like Figure 2 As shown, the method of this embodiment specifically includes:
[0057] S210: Monitor the load rates of the multiple CPU cores.
[0058] S220: When the load rate of at least one CPU core to be controlled is less than a lower threshold, determine a corresponding first target CPU core among the multiple CPU cores except the CPU core to be controlled.
[0059] S230: Allocate the task queue of the CPU core to be controlled to the first target CPU core, and control the CPU core to be controlled to enter a sleep state.
[0060] S240: When the load rate of at least one CPU core to be controlled is greater than an upper threshold, determine a corresponding second target CPU core from the dormant CPU cores.
[0061] Among them, the upper threshold value can be understood as the load rate of the CPU core to be controlled that wakes up the dormant CPU core. It should be noted that the acquisition method of the upper threshold value and the acquisition method of the lower threshold value can be the same or different. The dormant CPU core can be understood as a CPU core that is in a state of not generating power consumption. The second target CPU core can be understood as a CPU core that needs to be awakened in the dormant CPU core. The number of the second target CPU cores can be one, two, or more than two.
[0062] In an embodiment of the present application, determining the corresponding second target CPU core in the dormant CPU core may include: searching a hash table for a dormant CPU core corresponding to a partial task queue of the CPU core to be controlled, so as to determine the corresponding second target CPU core in the dormant CPU core.
[0063] Among them, some task queues can be understood as task queues whose load rate of the CPU core to be controlled is greater than the upper limit threshold. In an embodiment of the present application, the CPU core and the task queue corresponding to the CPU core are recorded in the hash table. In other words, the CPU core and the task queue of the CPU core are stored in the form of key-value pairs.
[0064] Specifically, when the load rate of the CPU core to be controlled is greater than the upper threshold, the task queue that makes the load rate of the CPU core greater than the upper threshold can be searched in the task queues of the CPU cores recorded in the hash table, that is, the partial task queue of the CPU core to be controlled can be obtained. Then, according to the corresponding relationship between the CPU cores and the task queues in the hash table, the dormant CPU core corresponding to the partial task queue of the CPU core to be controlled can be determined. Thus, the second target CPU core corresponding to the CPU core to be controlled can be determined in the dormant CPU cores.
[0065] On the basis of the above embodiment, before searching the hash table for the dormant CPU core corresponding to the partial task queue of the CPU core to be controlled, the method further includes: determining whether there is a dormant CPU core in the idle CPU pool. If so, the operation of searching the hash table for the dormant CPU core corresponding to the partial task queue of the CPU core to be controlled can be performed; if not, the first abnormal prompt information can be generated to prompt that there is no dormant CPU core in the idle CPU pool. The idle CPU pool can be understood as a pool for storing CPU cores that are not generating power consumption.
[0066] On the basis of the above embodiment, after searching the hash table for the dormant CPU core corresponding to the partial task queue of the CPU core to be controlled, the method further includes: determining whether the dormant CPU core corresponding to the partial task queue of the CPU core to be controlled exists in the idle CPU pool; if not, a second abnormal information can be generated to prompt that the dormant CPU core corresponding to the partial task queue of the CPU core to be controlled does not exist in the idle CPU pool. The advantage of such processing is that the phenomenon of abnormal CPU core management can be avoided.
[0067] S250 , waking up the second target CPU core, and allocating part of the task queue of the CPU core to be controlled to the second target CPU core.
[0068] In the embodiment of the present application, waking up the second target CPU core can be understood as enabling or activating a CPU core that is in a state of not generating power consumption, so that the CPU core enters a working state.
[0069] Specifically, after determining the second target CPU core corresponding to the CPU core to be controlled, the second target CPU core may be awakened. After the second target CPU core is awakened, part of the task queue of the CPU core to be controlled may be allocated to the second target CPU core.
[0070] Optionally, allocating some task queues of the CPU core to be controlled to the second target CPU core can be, when the number of some task queues of the CPU core to be controlled is multiple and the number of second target CPU cores is multiple, for each task queue in the some task queues, the task queue can be allocated to the second target CPU core corresponding to the task queue according to the correspondence between the task queue and the second target CPU core.
[0071] In an embodiment of the present application, the second target CPU core is woken up, and part of the task queue of the CPU core to be controlled is allocated to the second target CPU core. The advantage of such processing is that by dynamically adjusting the power consumption of the CPU core in the DPU to schedule the tasks of the CPU core more reasonably, the power consumption of the CPU core to be controlled with a higher load rate can be effectively reduced, thereby optimizing the power consumption of the DPU.
[0072] In an embodiment of the present application, the method further includes: an upper threshold and a lower threshold of the load rate of the multiple CPU cores can be configured in at least one time period. Optionally, a single time period can be obtained based on a start time and an end time. It should be noted that when the number of configured time periods is multiple, the duration of each time period can be the same or different.
[0073] In the embodiment of the present application, there are multiple ways to configure the upper and lower thresholds of the load rates of the multiple CPU cores, which can be manually configured by the user, or can be obtained by using a machine learning model; illustratively, the method of obtaining the load rate using a machine learning model can be: using the historical load rates, historical upper and lower thresholds of the multiple CPU cores in a preset historical period as training samples, training the machine learning model to obtain a trained model, and obtaining the lower and upper thresholds based on the trained model. Among them, the preset historical period can be set according to actual needs and is not specifically limited here.
[0074] Exemplarily, at least one time period may include 8:00-9:00 and 9:00-12:00. In the 8:00-9:00 time period, the upper threshold of the load rate of the multiple CPU cores may be 90% and the lower threshold may be 5%; in the 9:00-12:00 time period, the upper threshold of the load rate of the multiple CPU cores may be 85% and the lower threshold may be 10%.
[0075] Based on the above embodiment, at least one time period and the upper and lower thresholds corresponding to the at least one time period can be stored in a linked list. The advantage of this process is that it is easy to modify the time period and modify the upper and lower thresholds configured for the time period, thereby improving the flexibility of the threshold configuration.
[0076] Furthermore, in order to uniformly manage the upper and lower thresholds configured for at least one time period, a global enable switch may be configured for the configured linked list. The global enable switch may be understood as a global variable used to control whether the configured linked list is enabled. Typically, the data type of the global enable switch is a Boolean type.
[0077] The technical solution of the embodiment of the present application can allocate part of the task queue of the CPU core with a higher load rate to the dormant CPU core when the load rate of the CPU core is high, thereby achieving the technical effect of load balancing.
[0078] Figure 3 This is a schematic diagram of the structure of a DPU power consumption control device provided by another embodiment of the present application. The DPU power consumption control device can be applied to a scenario where the power consumption of a DPU including multiple CPU cores is controlled. Figure 3 As shown, the DPU includes multiple CPU cores, and the device includes: a load rate determination module 310, a first CPU core determination module 320 and a first CPU core control module 330.
[0079] The load rate determination module 310 is used to monitor the load rates of the multiple CPU cores. The first CPU core determination module 320 is used to determine the corresponding first target CPU core among the multiple CPU cores except the CPU core to be controlled when the load rate of at least one CPU core to be controlled is less than the lower limit threshold. The first CPU core control module 330 is used to assign the task queue of the CPU core to be controlled to the first target CPU core and control the CPU core to be controlled to enter a sleep state.
[0080] The technical solution of the embodiment of the present application dynamically adjusts the load rates of the multiple CPU cores of the DPU by assigning the task queue of the CPU core to be controlled whose load rate is less than the lower limit threshold to the first target CPU core determined among the multiple CPU cores other than the CPU core to be controlled, and then controlling the CPU core to be controlled to enter a sleep state, thereby optimizing the power consumption of the DPU and achieving the technical effect of reducing the power consumption of the DPU.
[0081] Optionally, the first CPU core determination module 320 is further used to obtain the remaining computing capacity of each CPU core among the multiple CPU cores except the CPU core to be controlled, and select the CPU core with the largest remaining computing capacity as the first target CPU core.
[0082] Optionally, the device further comprises a task queue recording module. The task queue recording module is used to record the task queue of the CPU core to be controlled using a hash table before allocating the task queue of the CPU core to be controlled to the first target CPU core.
[0083] Optionally, the device further includes: a second CPU core determination module and a second CPU core control module.
[0084] The second CPU core determination module is used to determine the corresponding second target CPU core in the dormant CPU cores when the load rate of at least one CPU core to be controlled is greater than the upper threshold. The second CPU core control module is used to wake up the second target CPU core and allocate part of the task queues of the CPU core to be controlled to the second target CPU core, wherein the part of the task queues is the task queues whose load rate of the CPU core to be controlled is greater than the upper threshold.
[0085] Optionally, the device further includes a threshold configuration module, wherein the threshold configuration module is used to configure an upper threshold and a lower threshold of the load rate of the multiple CPU cores in at least one time period, wherein the upper threshold is the load rate of the CPU core to be controlled that wakes up the dormant CPU core, and the lower threshold is the load rate of the CPU core to be controlled that enters dormancy.
[0086] Optionally, the second CPU core determination module is specifically configured to search a hash table for a dormant CPU core corresponding to the part of the task queues of the CPU core to be controlled, so as to determine a corresponding second target CPU core among the dormant CPU cores.
[0087] The DPU power consumption control device provided in the embodiment of the present application can execute the DPU power consumption control method provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method.
[0088] It is worth noting that the various functional modules included in the above-mentioned DPU power consumption control device are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional modules are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the embodiments of the present application.
[0089] Accordingly, an embodiment of the present application also provides a chip. The chip includes a processor and a memory. The processor is used to execute computer program instructions stored in the memory, wherein, when the computer program instructions are executed by the processor, the chip is triggered to execute the DPU power consumption control method provided in the aforementioned embodiment. Specifically, the chip may be a DPU, and the DPU may include multiple CPU cores, capable of executing the DPU power consumption control method provided in the aforementioned embodiments. The method includes: monitoring the load rates of the multiple CPU cores; when the load rate of at least one CPU core to be controlled is less than a lower limit threshold, determining a corresponding first target CPU core among the multiple CPU cores other than the CPU core to be controlled; assigning the task queue of the CPU core to be controlled to the first target CPU core, and controlling the CPU core to be controlled to enter a sleep state.
[0090] Accordingly, the present application also provides an electronic device. The electronic device includes the chip provided in the above embodiment. Specifically, the electronic device may be a server. The chip may be a DPU, and the DPU is configured on the server through a PCIE interface.
[0091] See also Figure 4 , Figure 4 A schematic diagram of the structure of the electronic device 10 provided by the present application is shown. Specifically, the electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.
[0092] like Figure 4 As shown, the electronic device 10 includes at least one central processor 11, and a memory connected to the at least one central processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The central processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0093] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks. The communication unit 19 may include the chip provided by the aforementioned embodiment.
[0094] The central processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the central processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc.
[0095] In some embodiments, the DPU power consumption control method may be implemented as a computer program tangibly embodied in a computer-readable storage medium.
[0096] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0097] The computer programs for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer programs are executed by the processor, the functions / operations specified in the flow charts and / or block diagrams are implemented. The computer programs may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.
[0098] In the context of the present application, a computer readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device or equipment. A computer readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer readable storage medium may be a machine readable signal medium. A more specific example of a machine readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0099] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
[0100] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0101] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.
[0102] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution of this application can be achieved, and this document is not limited here.
[0103] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.
Claims
1. A DPU power consumption control method, characterized in that: The DPU includes multiple CPU cores, and the method includes: Monitoring the load rates of the multiple CPU cores; When the load rate of at least one CPU core to be controlled is less than a lower limit threshold, determining a corresponding first target CPU core among the multiple CPU cores except the CPU core to be controlled; The task queue of the CPU core to be controlled is allocated to the first target CPU core, and the CPU core to be controlled is controlled to enter a dormant state.
2. The method according to claim 1, characterized in that Determining a corresponding first target CPU core among the plurality of CPU cores except the CPU core to be controlled includes: Acquire the remaining computing capacity of each CPU core among the multiple CPU cores except the CPU core to be controlled; The CPU core with the largest remaining computing power is selected as the first target CPU core.
3. The method according to claim 1, characterized in that Before allocating the task queue of the CPU core to be controlled to the first target CPU core, the method includes: A hash table is used to record the task queue of the CPU core to be controlled.
4. The method according to claim 1, characterized in that: The method comprises: When the load rate of at least one CPU core to be controlled is greater than an upper threshold, determining a corresponding second target CPU core from the dormant CPU cores; Waking up the second target CPU core and allocating part of the task queue of the CPU core to be controlled to the second target CPU core, The partial task queues are task queues whose load rates of the CPU cores to be controlled are greater than the upper limit threshold.
5. The method according to claim 4, characterized in that The method includes: configuring an upper threshold and a lower threshold of the load rate of the multiple CPU cores in at least one time period, wherein the upper threshold is the load rate of the CPU core to be controlled that wakes up the dormant CPU core, and the lower threshold is the load rate of the CPU core to be controlled that goes into dormancy.
6. The method according to claim 4, characterized in that Determining a corresponding second target CPU core in the dormant CPU core includes: The dormant CPU cores corresponding to the part of the task queues of the CPU core to be controlled are searched in the hash table to determine the corresponding second target CPU cores among the dormant CPU cores.
7. A DPU power consumption control device, characterized in that: The DPU includes multiple CPU cores, and the device includes: A load rate determination module, used to monitor the load rates of the multiple CPU cores; A first CPU core determination module, configured to determine a corresponding first target CPU core among the plurality of CPU cores except the CPU core to be controlled when the load rate of at least one CPU core to be controlled is less than a lower limit threshold; The first CPU core control module is used to allocate the task queue of the CPU core to be controlled to the first target CPU core, and control the CPU core to be controlled to enter a sleep state.
8. A chip, characterized in that: The chip comprises: A processor, which is used to execute computer program instructions stored in a memory, wherein when the computer program instructions are executed by the processor, the chip is triggered to execute the DPU power consumption control method described in any one of claims 1 to 6.
9. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 8.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the DPU power consumption control method according to any one of claims 1 to 6 when executed.