Method, system and equipment for resetting multi-core heterogeneous system

Abstract

The invention provides a resetting method, system and equipment for a multi-core heterogeneous system. The reset method comprises the following steps: a processor core in a first hardware domain generates a reset flag bit in response to a reset request operation of a user or based on a reset monitoring result of an operating system running on the processor core, and writes the reset flag bit into a shared memory; the processor core in the first hardware domain sends a reset signal to the second hardware domain after writing the reset flag bit into the shared memory; and the second hardware domain reads the reset flag bit in the shared memory based on the reset signal, and performs reset restarting on the single first hardware domain or all the first hardware domains based on the reset flag bit. Therefore, single-domain reset and global reset can be realized, and the problem that the integrity of the system cannot be solved by single-domain reset is solved.

Description

Technical Field

[0001] The present application relates to the technical field of multi-core heterogeneous systems, and in particular to a reset method, system and device for a multi-core heterogeneous system. Background Art

[0002] In a multi-core heterogeneous chip, multiple operating systems (such as RTOS, Android, Linux, QNX, etc.) are integrated, and each operating system runs in an independent domain. For a single-domain system, the reset operation can be implemented through the Android reset mechanism, such as restarting the system through recovery mode, restoring factory settings, etc. However, for multi-core heterogeneous chips, the existing technology cannot meet the reset requirements of all domains.

[0003] Single-domain reset can only reset specific systems or devices, and cannot handle global faults of the entire chip or system. In some cases, if there is mutual dependence or influence between multiple systems, single-domain reset may not be able to solve the problem of system integrity. In a complex multi-core heterogeneous chip system, the failure of a system may spread to other systems, causing a chain reaction. Single-domain reset cannot effectively deal with the spread of faults, which may affect the instability and reliability of the entire system. In addition, frequent single-domain reset operations may reduce the operating efficiency of the system because the system needs to be reinitialized and restored during the reset process, resulting in a slower system response speed and affecting the user experience. Summary of the invention

[0004] The present application is proposed to solve the above technical problems existing in the prior art. The present application provides a reset method, system and device for a multi-core heterogeneous system, which can solve the system integrity problem when multiple operating systems are mutually dependent or influenced, and can improve the stability and reliability of the multi-core heterogeneous system.

[0005] According to a first scheme of the present application, a reset method for a multi-core heterogeneous system is provided, wherein the multi-core heterogeneous system comprises a plurality of processor cores with different architectures, wherein the processor cores and their corresponding hardware resources respectively constitute a first hardware domain and a second hardware domain, wherein the first hardware domain and the second hardware domain are hard-isolated from each other, and there is inter-core communication between the first hardware domain and the second hardware domain, and the data processing security of the second hardware domain is higher than that of the first hardware domain, and the reset method comprises: the processor core in the first hardware domain generates a reset flag in response to a reset request operation of a user or based on a reset monitoring result of an operating system running on the processor core, and writes the reset flag into a shared memory, wherein the reset flag is used to indicate that a single first hardware domain or all first hardware domains' operating systems are to be reset and restarted; after the processor core in the first hardware domain writes the reset flag into the shared memory, the processor core sends a reset signal to the second hardware domain; the second hardware domain reads the reset flag in the shared memory based on the reset signal, and resets and restarts a single first hardware domain or all first hardware domains based on the reset flag.

[0006] According to a second scheme of the present application, a multi-core heterogeneous reset system is provided, comprising: a reset monitoring module and a reset module, wherein the reset monitoring module is configured to generate a reset flag in response to a user's reset request operation, or based on a reset monitoring result of a reset monitoring of the working status of the processor core of each first hardware domain, and write the reset flag into a shared memory, wherein the reset flag is used to indicate that the operating system of a single first hardware domain or all first hardware domains is to be reset and restarted; after the reset flag is written into the shared memory, a reset signal is sent to the reset module; the reset module is configured to: based on the reset signal, read the reset flag in the shared memory, and reset and restart the single first hardware domain or all first hardware domains based on the reset flag.

[0007] According to a third scheme of the present application, a computer device is provided, comprising a processor, a memory, and a computer program stored in the memory and running on the processor, wherein the processor is used to execute the computer program stored in the memory to implement the reset method of the multi-core heterogeneous system described in each embodiment of the present application.

[0008] According to a fourth embodiment of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor executes the reset method of the multi-core heterogeneous system described in each embodiment of the present application.

[0009] Compared with the prior art, the beneficial effects of the embodiments of the present application are:

[0010] The processor core in the first hardware domain provided by the embodiment of the present application responds to the user's reset request operation or generates a reset flag based on the reset monitoring result, writes the reset flag into the shared memory, and sends a reset signal to the second hardware domain. The second hardware domain responds to the reset signal and reads the reset flag from the shared memory to perform a single domain reset or a global reset based on the reset flag. In this way, a global reset can be achieved, and the global failure of the entire chip or multi-core heterogeneous system can be handled by the global reset to solve the problem of overall instability of the multi-core heterogeneous system. Secondly, the difficulty of maintaining and debugging the multi-core heterogeneous system can be reduced, and the repair of the problems of the entire multi-core heterogeneous system can be achieved by global reset. In addition, through the global reset method, the operating efficiency of the multi-core heterogeneous system can also be improved, avoiding the problem of slow system response speed and poor user experience caused by initializing the multi-core heterogeneous system.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above description and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar parts in different views. Similar reference numerals with letter suffixes or different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments by way of example and not by way of limitation, and together with the description and claims, are used to illustrate the disclosed embodiments. Such embodiments are illustrative and exemplary and are not intended to be exhaustive or exclusive embodiments of the present method, apparatus, system, or non-transitory computer-readable medium having instructions for implementing the method.

[0013] Figure 1 A flowchart of a method for resetting a multi-core heterogeneous system according to an embodiment of the present application is shown.

[0014] Figure 2 A structural schematic diagram of a SOC system according to an embodiment of the present application is shown.

[0015] Figure 3 Another flowchart of the reset method of the multi-core heterogeneous system according to the embodiment of the present application is shown. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solution of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific implementation examples. The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation examples, but are not intended to limit the present application.

[0017] The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish. The words "include" or "comprises" and similar words used in this application mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of covering other elements. In this application, the arrows shown in the figures of each step are only examples of the execution order, not limitations. The technical solution of this application is not limited to the execution order described in the embodiments. The various steps in the execution order can be combined, decomposed, or the order can be changed, as long as the logical relationship of the execution content is not affected.

[0018] All terms (including technical terms or scientific terms) used in this application have the same meaning as those understood by ordinary technicians in the field to which this application belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined here. Techniques and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques and equipment should be considered as part of the specification.

[0019] Figure 1 A flow chart of a reset method for a multi-core heterogeneous system according to an embodiment of the present application is shown. The multi-core heterogeneous system includes multiple processor cores with different architectures, and the processor cores and their corresponding hardware resources respectively form a first hardware domain and a second hardware domain, and the first hardware domain and the second hardware domain are hard-isolated, and there is inter-core communication between the first hardware domain and the second hardware domain, and the data processing security of the second hardware domain is higher than that of the first hardware domain. In addition, in the case where there are multiple first hardware domains or multiple second hardware domains, inter-core communication can also be performed between each first hardware domain and between each second hardware domain. Specifically, as Figure 2 The multi-core heterogeneous system may be, for example, a SOC (system on chip) 200, which includes a plurality of first hardware domains (first hardware domain-1 2011 and first hardware domain-2 2012) and a second hardware domain 202, wherein only this case is shown, and the number and structure of the first hardware domains and the second hardware domains 202 are not specifically limited.

[0020] The processor cores with different architectures respectively form a plurality of first hardware domains and a second hardware domain 202 with their corresponding hardware resources, which enables the SOC 200 to have a multi-core heterogeneous characteristic. The first hardware domain and the second hardware domain 202 are independent of each other and can communicate between cores to exchange data. In some other embodiments, the second hardware domain 202 is associated with a plurality of first hardware domains, specifically, the second hardware domain 202 can have inter-core communication with a plurality of first hardware domains, so that each first hardware domain can interact with the second hardware domain 202 through inter-core communication.

[0021] The data processing security of the second hardware domain 202 is higher than that of the first hardware domain. For example, the first hardware domain may be an application domain, and the second hardware domain 202 may be a security domain. The application domain has a corresponding operating system, and the security domain also has a corresponding operating system. The inter-core communication between the application domain and the security domain can be realized based on the interaction between the two operating systems.

[0022] The SOC 200 can be applied to the smart cockpit of the automotive electronic system, which integrates a variety of intelligent devices, including instrument panels, central control screens, car audio, navigation systems, car entertainment systems, etc. There are associations and dependencies between multiple systems in the smart cockpit. This complex intelligent system cannot ensure the stability and reliability of multiple systems in the entire smart cockpit based on the traditional single-domain reset method. In addition, for smart cockpits with higher complexity, frequent single-domain reset operations will reduce the operating efficiency of the entire smart cockpit system and affect the user experience.

[0023] To this end, an embodiment of the present application provides a multi-core heterogeneous reset method, specifically steps S101 to S103. The arrows shown in the figures of each step are merely examples of the execution order, not limitations. The technical solution of the present application is not limited to the execution order described in the embodiment. The steps in the execution order can be combined, decomposed, or the order can be changed, as long as the logical relationship of the execution content is not affected.

[0024] Combination Figure 2 , the reset method provided in the embodiment of the present application is described in detail.

[0025] In step S101, the processor core in the first hardware domain generates a reset flag in response to a reset request operation by a user or based on a reset monitoring result of the operating system running on the processor core, and writes the reset flag into the shared memory 203, wherein the reset flag is used to indicate that the operating system of a single first hardware domain or all first hardware domains will be reset and restarted. Specifically, Figure 2For example, the first hardware domain includes the first hardware domain-1 2011 and the second hardware domain-2 2012. The first hardware domain-1 2011 and the second hardware domain-2 2012 respectively run different operating systems. For example, the first hardware domain-1 2011 is used to control the in-vehicle entertainment of the smart cockpit, and the second hardware domain-2 2012 is used to control the navigation of the smart cockpit.

[0026] In the specific implementation process, assuming that the vehicle driver is driving the vehicle, and during the driving process, the in-vehicle entertainment system is found to be stuck or confused, the driver can trigger a reset request operation by controlling the function buttons on the in-vehicle screen or voice and other methods. Among them, the reset request operation includes a single-domain reset request operation and a global reset request operation. For example, the driver triggers the single-domain reset request operation of the first hardware domain-1 2011, and the processor core of the first hardware domain-1 2011 responds to the user's single-domain reset request operation, generates a corresponding single-domain reset flag, and writes the single-domain reset flag into the shared memory 203.

[0027] Alternatively, assuming that the driver triggers the global reset request operation of the first hardware domain-1 2011 and the first hardware domain-2 2012, the processor cores of the first hardware domain-1 2011 and the first hardware domain-2 2012 generate corresponding global reset flags in response to the global reset request operation of the user, and write the global reset flags into the shared memory 203. That is, the reset flags include single-domain reset flags and global reset flags. In some other embodiments, when the processor core of the first hardware domain responds to the single-domain reset request operation of the user, a single-domain reset flag is generated to reset and restart the operating system of a single first hardware domain; when the processor core of the first hardware domain responds to the global reset request operation of the user, a global reset flag is generated to reset and restart the operating systems of all first hardware domains.

[0028] In addition, the main processor core or other hardware domains of SOC 200 can also perform reset monitoring on the operating systems running in the processor cores in the first hardware domain-1 2011 and the second hardware domain-2 2012, and generate reset monitoring results. For example, during the reset monitoring process, if it is found that the in-vehicle entertainment system has data loss, data error and other related problems, a reset monitoring result for characterizing the system error of the first hardware domain-1 2011 is generated. Similarly, if it is found that the navigation system has data loss, connection error and other related problems, a reset monitoring result for characterizing the system error of the second hardware domain-2 2012 is also generated. The reset monitoring results can be stored in the memory of each hardware domain so that they can be read by the processor core of each hardware domain.

[0029] Specifically, the first hardware domain-1 2011 and the second hardware domain-2 2012 can respectively read the reset monitoring result, generate a reset flag according to the reset monitoring result, and then write the reset flag bit generated by each into the shared memory 203 .

[0030] Among them, the reset flag bit can be 0 (for example, used to indicate a single domain reset) or 1 (for example, used to indicate a global domain reset), or it can be other marking symbols, and there is no limitation on this, as long as it can be determined based on the reset flag bit whether a single domain reset or a global domain reset is performed.

[0031] In step S102, after the processor core in the first hardware domain writes the reset flag into the shared memory 203, it sends a reset signal to the second hardware domain 202. Each of the first hardware domains performs inter-core communication with the second hardware domain 202, and after determining the reset mode, the first hardware domain-1 2011 and the second hardware domain-2 2012 send a reset signal to the second hardware domain 202. The reset signal may be, for example, a watchdog or other symbol with an identification, to notify the second hardware domain 202 to perform a reset and restart process.

[0032] In step S103, the second hardware domain 202 reads the reset flag in the shared memory 203 based on the reset signal, and resets and restarts a single first hardware domain or all first hardware domains based on the reset flag. That is, the second hardware domain 202 responsible for resetting can be responsive to the received reset signal, checks the reset flag in the shared memory 203, and determines whether to perform a single domain reset or a global domain reset according to the reset flag. If it is a single domain reset, the second hardware domain 202 controls the first hardware domain-1 2011 or the second hardware domain-2 2012 to reset and restart, and if it is a global domain reset, controls the first hardware domain-1 2011 and the second hardware domain-2 2012 to reset and restart.

[0033] The reset method provided in the embodiment of the present application is used in application scenarios of automotive electronic systems such as smart cockpits. In the smart cockpit, for example, when an abnormality occurs in the entertainment system and needs to be restarted, recovery is achieved by default through a single-domain reset. For situations where recovery cannot be achieved through a single-domain reset, global reset and restart operations can be performed on multiple systems on the entire SOC 200 chip, thereby quickly restoring the normal operating state of the entire smart cockpit.

[0034] In some embodiments of the present application, when it is determined based on the reset flag that a single first hardware domain needs to be reset and restarted, the second hardware domain 202 writes a single domain reset instruction in the processor core of the first hardware domain to be reset that needs to be reset and restarted, so that the first hardware domain to be reset restarts the operating system of the first hardware domain to be reset based on the single domain reset instruction. Specifically, if the first hardware domain-1 2011 needs to be reset, the first hardware domain-1 2011 will generate a reset flag that marks that the first hardware domain-1 2011 needs to be reset, and store it in the shared memory 203. Similarly, if the first hardware domain-2 2012 needs to be reset, the first hardware domain-2 2012 will generate a reset flag that marks that the first hardware domain-2 2012 needs to be reset. In other words, each first hardware domain is marked in the reset flag generated by each, so that the second hardware domain 202 can identify each first hardware domain. This is only used as an exemplary description and does not constitute a limitation on the specific solution.

[0035] When the second hardware domain 202 reads the reset flag in the shared memory 203, it can identify the first hardware domain that needs to be reset according to the identity tag in the reset flag. If there is only the reset flag from the first hardware domain -1 2011 in the shared memory 203, the second hardware domain 202 can determine that the reset mode is a single domain reset. If there are reset flags from all the first hardware domains in the shared memory 203, the second hardware domain 202 can determine that the reset mode is a global domain reset. In other words, the second hardware domain 202 can determine the reset mode based on the source of the reset flag stored in the shared memory 203.

[0036] Alternatively, in the case where there is a mutual connection between the first hardware domain-1 2011 and the first hardware domain-2 2012, a running error in the first hardware domain-1 2011 will also affect the running status of the first hardware domain-2 2012. At this time, if only the first hardware domain-1 2011 is reset, the system of the entire SOC 200 cannot be restored to stability. In this case, the first hardware domain-1 2011 can determine that a global reset is required by performing reset monitoring on the system when the reset monitoring result shows that the system is abnormal and cannot be restored, and a global reset (i.e., a global reset flag) will be marked in the generated reset flag. That is to say, in some other embodiments, the processor cores in each first hardware domain perform reset monitoring on the working status of each first hardware domain, and when the reset monitoring result shows that the system is abnormal and cannot be restored, a global reset flag is generated to reset and restart the operating systems of all first hardware domains.

[0037] At this time, even if the second hardware domain 202 reads the reset flag from the first hardware domain-1 2011 in the shared memory 203, since the reset flag indicates a global reset, the second hardware domain 202 can identify that the reset and restart is performed in a global reset manner.

[0038] For example, the second hardware domain 202 reads the reset flag based on the shared memory 203, and when it is identified that the first hardware domain-1 2011 is to be reset as a single domain, the second hardware domain 202 writes a single domain reset instruction into the processor core of the first hardware domain-1 200. In response to the single domain reset instruction, the first hardware domain-1 2011 resets and restarts the operating system of the first hardware domain-1 2011.

[0039] Alternatively, the second hardware domain 202 reads the reset flag bit and identifies that all first hardware domains need to be reset, that is, when a global reset is performed, a global reset instruction can be directly written into the main processor core of the SOC 200 to control the first hardware domain-1 2011 and the first hardware domain-2 2012 of the SOC 200 to reset and restart through the main processor core. Of course, when the second hardware domain 202 identifies that the reset mode is a global reset, the global reset instruction can also be written into the processor core of each first hardware domain. The global reset instruction can include relevant information such as the time stamp for performing the global reset, so that each first hardware domain is reset and restarted at the same time based on the global reset instruction. This is only used as an exemplary description and does not constitute a limitation on the specific solution.

[0040] That is to say, in some other embodiments of the present application, when it is determined based on the reset flag that all first hardware domains need to be reset and restarted, the second hardware domain directly writes a global reset instruction into the main processor core of the multi-core heterogeneous system, so that the main processor core restarts the operating systems of all first hardware domains based on the global reset instruction.

[0041] Figure 3Another exemplary flowchart of the reset method of a multi-core heterogeneous system is shown. In step S301, the first hardware domain triggers a reset according to the reset monitoring result or in response to a reset request operation, and determines the reset mode based on the reset monitoring result or the reset request (such as step S302). The reset mode includes a single-domain reset mode and a global reset mode. Step S303 is further executed to determine whether it is a global reset. If the judgment result is no, step S309 is executed. The first hardware domain generates a single-domain reset flag and writes the single-domain reset flag to the shared memory, and then step S310 is executed. The first hardware domain sends a reset signal, and the second hardware domain responds to the reset signal and detects the single-domain reset flag (such as step S311). Then step S312 is executed. The second hardware domain writes a single-domain reset instruction in the first hardware domain that needs to be reset, and the first hardware domain performs a single-domain reset and restart based on the single-domain reset instruction (step S313). In this way, the local system errors and freezes in the smart cockpit can be solved by resetting and restarting a single first hardware domain.

[0042] If the judgment result of step S303 is yes, then step S304 is executed, the first hardware domain generates a global reset flag, and writes the global reset flag into the shared memory, and step S305 is executed, the first hardware domain sends a reset signal, the second hardware domain responds to the reset signal, detects the global reset flag (such as step S306), and then step S307 is executed, the second hardware domain writes a global reset instruction in the main processor core, and the main processor core performs a global reset and restart based on the global reset instruction (step S308). In this way, the problem that cannot be solved by a single domain reset can be solved by a global reset, ensuring the stability and reliability of the entire system of the smart cockpit.

[0043] In some embodiments of the present application, a multi-core heterogeneous reset system is provided, including: a reset monitoring module and a reset module, wherein the reset monitoring module is configured to: generate a reset flag in response to a user's reset request operation, or based on a reset monitoring result of a reset monitoring of the working conditions of the processor cores of each first hardware domain, and write the reset flag into a shared memory, wherein the reset flag is used to indicate that a single first hardware domain or all first hardware domains' operating systems are to be reset and restarted; after the reset flag is written into the shared memory, a reset signal is sent to the reset module; the reset module is configured to: read the reset flag in the shared memory based on the reset signal, and reset and restart a single first hardware domain or all first hardware domains based on the reset flag. In this way, the system integrity problem can be solved in the case where multiple operating systems are mutually dependent or influenced, and the stability and reliability of the multi-core heterogeneous system can be improved.

[0044] The reset module is further configured to, when it is determined based on the reset flag that a single first hardware domain needs to be reset and restarted, write a single-domain reset instruction into a processor core of the first hardware domain to be reset that needs to be reset and restarted, so that the first hardware domain to be reset restarts the operating system of the first hardware domain to be reset based on the single-domain reset instruction.

[0045] The reset module is further configured to: when it is determined based on the reset flag that all first hardware domains need to be reset and restarted, write a global reset instruction in the main processor core of the multi-core heterogeneous system, so that the main processor core restarts the operating systems of all first hardware domains based on the global reset instruction.

[0046] In some embodiments of the present application, a computer device is provided, including a processor, a memory, and a computer program stored in the memory and running on the processor, wherein the processor is used to execute the computer program stored in the memory to implement the reset method of the multi-core heterogeneous system described in each embodiment of the present application.

[0047] In some embodiments of the present application, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor executes the reset method of the multi-core heterogeneous system described in each embodiment of the present application.

[0048] The steps of the reset method of the multi-core heterogeneous system described in the above embodiments can all be combined here and will not be described in detail.

[0049] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0050] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0051] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0052] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0053] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.

[0054] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0055] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0056] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0057] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0058] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices, chips, electronic devices and storage media can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0059] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0061] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0062] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A reset method for a multi-core heterogeneous system, characterized in that: The multi-core heterogeneous system includes a plurality of processor cores with different architectures, the processor cores and their corresponding hardware resources respectively form a first hardware domain and a second hardware domain, the first hardware domain and the second hardware domain are hard-isolated, and there is inter-core communication between the first hardware domain and the second hardware domain, the data processing security of the second hardware domain is higher than that of the first hardware domain, and the reset method includes: The processor core in the first hardware domain generates a reset flag in response to a reset request operation of a user or based on a reset monitoring result of an operating system running on the processor core, and writes the reset flag into a shared memory, wherein the reset flag is used to indicate that the operating system of a single first hardware domain or all first hardware domains will be reset and restarted; After writing the reset flag into the shared memory, the processor core in the first hardware domain sends a reset signal to the second hardware domain; The second hardware domain reads the reset flag in the shared memory based on the reset signal, and resets and restarts a single first hardware domain or all first hardware domains based on the reset flag.

2. The reset method according to claim 1, characterized in that: The resetting method further comprises: When it is determined based on the reset flag that a single first hardware domain needs to be reset and restarted, the second hardware domain writes a single-domain reset instruction into a processor core of the first hardware domain to be reset that needs to be reset and restarted, so that the first hardware domain to be reset restarts the operating system of the first hardware domain to be reset based on the single-domain reset instruction.

3. The resetting method according to claim 2, characterized in that: The resetting method further comprises: When it is determined based on the reset flag that all first hardware domains need to be reset and restarted, the second hardware domain directly writes a global reset instruction into the main processor core of the multi-core heterogeneous system, so that the main processor core restarts the operating systems of all first hardware domains based on the global reset instruction.

4. The resetting method according to claim 1, characterized in that: The reset flag includes a single domain reset flag and a global domain reset flag. The resetting method further comprises: The processor cores in each first hardware domain perform reset monitoring on the working status of each first hardware domain, and when the reset monitoring result shows that the system is abnormal and cannot be recovered, a global reset flag is generated to reset and restart the operating systems of all first hardware domains.

5. The resetting method according to claim 1, characterized in that: The reset request operation includes a single-domain reset request operation and a global-domain reset request operation. When the processor core of the first hardware domain responds to the single-domain reset request operation of the user, a single-domain reset flag is generated to reset and restart the operating system of the single first hardware domain. When the processor core of the first hardware domain responds to the global reset request operation of the user, a global reset flag is generated to reset and restart the operating systems of all the first hardware domains.

6. A multi-core heterogeneous reset system, characterized in that: include: A reset monitoring module and a reset module, wherein the reset monitoring module is configured as: In response to a reset request operation by a user, or based on a reset monitoring result of performing reset monitoring on the working conditions of the processor cores of each first hardware domain, a reset flag is generated, and the reset flag is written into a shared memory, wherein the reset flag is used to indicate that the operating system of a single first hardware domain or all first hardware domains is to be reset and restarted; After writing the reset flag into the shared memory, sending a reset signal to the reset module; The reset module is configured to: read the reset flag in the shared memory based on the reset signal, and reset and restart a single first hardware domain or all first hardware domains based on the reset flag.

7. The multi-core heterogeneous reset system according to claim 6, characterized in that: The reset module is further configured as follows: When it is determined based on the reset flag that a single first hardware domain needs to be reset and restarted, a single-domain reset instruction is written into a processor core of the first hardware domain to be reset that needs to be reset and restarted, so that the first hardware domain to be reset restarts the operating system of the first hardware domain to be reset based on the single-domain reset instruction.

8. The multi-core heterogeneous reset system according to claim 6, characterized in that: The reset module is further configured as follows: When it is determined based on the reset flag that all first hardware domains need to be reset and restarted, a global reset instruction is written into the main processor core of the multi-core heterogeneous system so that the main processor core restarts the operating systems of all first hardware domains based on the global reset instruction.

9. A computer device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and running on the processor, wherein the processor is used to execute the computer program stored in the memory to implement the reset method of the multi-core heterogeneous system according to any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor executes the reset method of a multi-core heterogeneous system according to any one of claims 1 to 5.

Images