Chip and circuit structure for I2C address device information configuration

Abstract

The invention discloses a chip and a circuit structure for I2C address device information configuration. The chip is connected to an I2C bus; the chip is provided with a detection pin, the detection pin of the chip is connected with the detection resistor, and when the resistance value of the detection resistor changes, the voltage value of the voltage signal at the detection pin changes; the chip stores the mapping relation between the voltage value of the voltage signal at the detection pin and the I2C address equipment information; and the chip is used for configuring I2C address equipment information by using the voltage signal at the detection pin based on the mapping relation. The invention further discloses a circuit structure, the circuit structure comprises a detection resistor and the chip, the first end of the detection resistor is connected with the detection pin of the chip, the second end of the detection resistor is grounded, and the chip is connected to the I2C bus so that the circuit structure can be connected to the I2C bus.

Description

Technical Field

[0001] The present application relates to the electronic technical field of I2C bus, and in particular to a chip and circuit structure for configuring I2C address device information. Background Art

[0002] In the prior art, I2C communication is a relatively common communication control protocol, and the hardware support structure built into the integrated circuit is a multi-machine single-ended two-wire communication interface, which is configured to use a bus including a serial data line (SDA) and a serial clock line (SCL) to serially send or receive information from an I2C master device to an I2C slave device. The I2C master device may include a microcontroller or other electronic device configured to issue a clock and address a slave device, and the I2C slave device may include a peripheral device such as an analog digital controller (ADC), a digital analog controller (DAC), or one or more other peripheral devices configured to receive a clock and an address.

[0003] The device connected to the I2C bus has an independent device address, and the I2C system with an independent device address needs to be configured with a programmable ID. The existing I2C circuit needs to use more than two independent device addresses. For example, the chip that needs to burn firmware for a period of time is the chip that plays the role of the host, and the chip that needs to burn firmware for another period of time is the chip that plays the role of the slave. The firmware burned into the chip that plays the role of the host is different from the firmware burned into the chip that plays the role of the slave. When configuring the logical function of the same chip, after the configuration of the chip that plays the role of the host is completed by burning, the firmware needs to be modified before it can be configured as a chip that plays the role of the slave, which increases the complexity of external configuration and application of the I2C bus. Summary of the invention

[0004] This application discloses a chip and circuit structure for configuring I2C address device information. The specific technical solution is as follows:

[0005] A chip for configuring I2C address device information, the chip is connected to an I2C bus; the chip is provided with a detection pin, the detection pin of the chip is connected to a detection resistor, when the resistance value of the detection resistor changes, the voltage value of the voltage signal at the detection pin changes; the chip stores a mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information; the chip is used to configure the I2C address device information using the voltage signal at the detection pin based on the aforementioned mapping relationship. In summary, the technical solution provides a detection pin in the chip connected to the I2C bus, and detects the voltage signal at the detection pin in real time by detecting the amount of electricity fed back by the detection resistor, and automatically configures the I2C master-slave role and device address of the chip based on the corresponding mapping relationship. There is no need for relevant technical personnel to burn matching firmware to the chip connected to the I2C bus according to the established welding position when leaving the factory. Even if the welding position is uncertain, the chip will not be affected from configuring the correct master and slave and their device addresses in the I2C bus without modifying the firmware. In this way, when configuring the logical function of one of the chips connected to the I2C bus, after completing the configuration of the chip that plays the role of the host by burning, it is not necessary to modify the firmware before configuring it as a chip that plays the role of the slave. Instead, the same firmware is used to automatically configure the I2C master-slave role and device address of the chip, thereby simplifying the process of producing chips that support I2C communication.

[0006] Furthermore, the chip includes a control unit, an I2C address device configuration module and a current source; the current source is connected to the first end of the detection resistor, and the second end of the detection resistor is grounded; the detection resistor is used to receive the current output by the current source and generate a voltage signal at its first end; the detection pin is connected to the first end of the detection resistor, and the detection pin is used to collect the voltage signal generated by the first end of the detection resistor, wherein the voltage signal generated by the first end of the detection resistor is the voltage signal at the detection pin; the I2C address device configuration module is connected to the control unit; the control unit is used to detect the voltage value of the voltage signal at the detection pin, and based on the determined mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, call the I2C address device information from the I2C address device configuration module according to the voltage value of the voltage signal at the detection pin to configure the I2C address device information. Therefore, based on a chip disclosed in the present technical solution, usually only one detection pin needs to be retained, and there is no need to provide multiple pins for users to set. The setting of I2C address device information (including I2C address or device address) and the control of master and slave roles can be achieved through a completely software-based operation method, thereby speeding up the process of producing chips that support I2C communication.

[0007] Further, the I2C address device configuration module is used to store the mapping relationship between the resistance value of the detection resistor and the I2C address device information, and the mapping relationship between the resistance value of the detection resistor and the I2C address device information includes the mapping relationship between the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, so that the control unit configures the I2C address device information according to the detection resistor; wherein the current source is used to generate a constant current, so that the voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor, forming a mapping relationship between the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin. In summary, the mapping relationship between the I2C address device information and the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin is constructed in the chip connected to the I2C bus, which can be compatible with the mapping relationship of the chip connected to the I2C bus, and improve the functional logic of the control unit to map the corresponding I2C address device information by controlling the detection resistor and the voltage signal at the detection pin. When the device address of the chip in the I2C bus needs to be modified, there is no need to burn different firmware according to different device addresses. Instead, the I2C master-slave role and device address of the chip are automatically configured based on the corresponding mapping relationship, which simplifies the tediousness of burning different firmware due to the need to modify the master-slave role and device address.

[0008] Furthermore, the chip also includes an analog-to-digital converter; the detection pin is connected to the collection end of the analog-to-digital converter; the analog-to-digital converter is used to collect the voltage signal generated by the first end of the detection resistor and convert the collected voltage signal into a voltage identification value; the control unit is connected to the conversion output end of the analog-to-digital converter; the control unit is used to receive the voltage identification value and transmit it to the I2C address device configuration module to detect the voltage signal generated by the first end of the detection resistor through the analog-to-digital converter; the control unit is used to call the I2C address device information corresponding to the voltage identification value from the I2C address device configuration module according to the voltage identification value; wherein the mapping relationship between the voltage identification value and the I2C address device information is the mapping relationship between the voltage value of the converted voltage signal and the I2C address device information. This technical solution converts the voltage value of the voltage signal at the detection pin into a digital signal that is easy for the control unit to identify and encode and process in real time through the analog-to-digital converter, thereby improving the efficiency of voltage value comparison and mapping.

[0009] Further, the control unit calls the I2C address device information from the I2C address device configuration module according to the voltage value of the voltage signal at the detection pin, and configures the called I2C address device information as the method of the I2C address device information, including: when the control unit detects that the voltage value of the voltage signal at the detection pin is less than the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and then the chip is configured as a host device or an I2C host chip according to the called role configuration information; and the control unit is used to call the device address from the I2C address device configuration module according to the host address recognition voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configure the called device address as the I2C host address, forming the device address of the host device or the device address of the I2C host chip. In this technical solution, the control unit configures the I2C address device information using the resistance value of the detection resistor based on the mapping relationship between the resistance value of the detection resistor connected to the detection pin and the voltage value of the voltage signal at the detection pin, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information and the device address.

[0010] Further, a host identification voltage range corresponds to the role configuration information of a host device, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the host device; wherein the preset target voltage value is the upper limit value of the host identification voltage range; a host identification voltage range is divided into multiple host address identification voltage ranges, wherein a host address identification voltage range corresponds to an I2C host address, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the host device; wherein the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information includes the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the host device, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the host device; wherein the I2C address device information includes the role configuration information of the host device and its corresponding device address; the device address of the host device is the device address of the I2C host chip.

[0011] Therefore, within the voltage range for identifying the host device, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board and whether it is identified as a host in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls within a host address recognition voltage range, the role configuration information and the device address can be determined by the sensing voltage at its detection pin (specifically the voltage signal generated by the external detection resistor).

[0012] Furthermore, the number of host address identification voltage ranges divided by a host identification voltage range is equal to the number of I2C host addresses stored in the I2C address device configuration module or the number of I2C host addresses required to be configured by the control unit; the voltage change value covered by each host address identification voltage range is equal; when the detection resistor is an adjustable resistor, the detection resistor is configured to have multiple host detection resistor adjustment ranges, the number of host detection resistor adjustment ranges is equal to the number of host address identification voltage ranges, and the resistance change value covered by each host detection resistor adjustment range is equal; when the resistance value of the detection resistor is adjusted to a host detection resistor adjustment range, the voltage value of the voltage signal at the detection pin is within a corresponding host address identification voltage range. It is only necessary to judge the slave role configuration information and the device address by the resistance value of the detection resistor according to the set mapping relationship after the chip is powered on, thereby improving the production efficiency of chips supporting I2C communication.

[0013] Furthermore, the control unit calls I2C address device information from the I2C address device configuration module according to the voltage value of the voltage signal at the detection pin, and configures the called I2C address device information as the method of the I2C address device information, including: when the control unit detects that the voltage value of the voltage signal at the detection pin is greater than or equal to the preset target voltage value, calls the corresponding role configuration information from the I2C address device configuration module, and then configures the chip as a slave device or an I2C slave chip according to the called role configuration information; and the control unit is used to call the device address from the I2C address device configuration module according to the slave address identification voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C slave address to form the device address of the slave device or the device address of the I2C slave chip. In summary, the control unit is based on the mapping relationship between the voltage value of the voltage signal at the detection pin and the resistance value of the detection resistor connected to the detection pin, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device. The control unit can configure the I2C address device information according to the detection resistor. When the chip is configured as a slave device, it also configures the device address of the slave device or the device address of the I2C slave chip, so that other chips connected to the I2C bus can access the currently configured I2C slave chip.

[0014] Furthermore, a slave identification voltage range corresponds to the role configuration information of a slave device, forming a mapping relationship between the voltage signal and the role configuration information of the slave device; wherein the preset target voltage value is the lower limit value of the slave identification voltage range; a slave identification voltage range is divided into multiple slave address identification voltage ranges, and a slave address identification voltage range corresponds to an I2C slave address, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device; wherein the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information includes the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the slave device, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device; wherein the I2C address device information includes the role configuration information of the slave device and its corresponding device address; the device address of the slave device is the device address of the I2C slave chip. Therefore, within the voltage range for identifying slave devices, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board, whether it is identified as a master slave in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls within a slave address identification voltage range, the device address of the I2C slave chip can be determined by the sensed voltage at its detection pin (specifically the voltage signal generated by the external detection resistor), that is, the I2C slave address is configured.

[0015] Further, the number of slave address identification voltage ranges divided by a slave identification voltage range is equal to the number of I2C slave addresses stored in the I2C address device configuration module or the number of I2C slave addresses required to be configured by the control unit, and the voltage change value covered by each slave address identification voltage range is equal; when the detection resistor is an adjustable resistor, the detection resistor is configured to have multiple slave detection resistor adjustment ranges, the number of slave detection resistor adjustment ranges is equal to the number of slave address identification voltage ranges, and the resistance change value covered by each slave detection resistor adjustment range is equal; when the resistance value of the detection resistor is adjusted to a slave detection resistor adjustment range, the voltage value of the voltage signal generated by the first end of the detection resistor is within the corresponding slave address identification voltage range. In this technical solution, it is only necessary to judge the slave role configuration information and the device address by the resistance value of the detection resistor according to the set mapping relationship after the chip is powered on, and improve the production efficiency of the chip supporting I2C communication.

[0016] Furthermore, the I2C address device configuration module includes a memory, in which the mapping relationship stores the voltage value of the voltage signal at the detection pin and the corresponding I2C address device information in the form of a mapping table, so that the storage address of the voltage value of a voltage signal at the detection pin is mapped to the storage address of the corresponding I2C address device information; the mapping relationship also stores the resistance value of the detection resistor and the voltage value of the voltage signal at its first end in the form of a mapping table, so that the storage address of the resistance value of a detection resistor is mapped to the storage address of the voltage value of the voltage signal at the first end of a detection resistor. Thus, the mapping relationship enumerates the resistance values ​​of multiple detection resistors, the voltage value of the voltage signal at the first end of a detection resistor, the slave address identification voltage range, and the I2C address device information in the form of a mapping table, so as to use the memory to configure the mapping relationship for the chip in advance, so that when the control unit detects the voltage value of the corresponding voltage signal, the role configuration information and the device address are automatically mapped.

[0017] A circuit structure includes a detection resistor and a chip, wherein a first end of the detection resistor is connected to a detection pin of the chip, a second end of the detection resistor is grounded, and the chip is connected to an I2C bus so that the circuit structure is connected to the I2C bus. Based on the circuit structure disclosed in the technical solution, usually only one detection pin needs to be reserved, and multiple pins do not need to be provided for user setting. The setting of I2C address device information (including I2C address or device address) and the control of master and slave roles can be realized through a completely software operation mode, thereby improving the production efficiency of chips supporting I2C communication in the circuit structure, or the installation efficiency and adaptability of chips supporting I2C communication in the circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a circuit schematic block diagram of a chip used for I2C address device information configuration and its circuit structure in one embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0020] As an embodiment, a chip for configuring I2C address device information is disclosed, such as Figure 1As shown, the chip is connected to the I2C bus, and the chip is provided with a serial data line pin and a serial clock line pin. The serial data line pin is connected to the serial data line SDA of the I2C bus, and the serial data line pin is used to receive a data signal from the serial data line SDA; the serial clock line pin is connected to the serial clock line SCL of the I2C bus, and the serial clock line pin is used to receive a clock signal from the serial clock line SCL. The chip is also provided with a detection pin, and the detection pin of the chip is connected to a detection resistor, and the detection resistor is arranged at the periphery of the chip. In this embodiment, when the resistance value of the detection resistor changes, the voltage value of the voltage signal at the detection pin changes. For example, when the resistance value of the detection resistor increases, the voltage value of the voltage signal at the detection pin increases, which can be quantified as the voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor.

[0021] In this embodiment, the chip pre-sets the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, and the mapping relationship between the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin. These mapping relationships and the parameters required for use, the mapped results and the mapped variables are all pre-stored in the storage unit provided in the chip, and can be stored in the form of firmware and remain unchanged. The firmware can be a library that encapsulates the fast charging protocol or other communication protocols. The I2C address device information includes role configuration information (host or slave) and device address. The device address configured by the chip can be unique in the I2C bus, forming the ID of the I2C slave chip or slave device.

[0022] The chip is used to configure the I2C address device information using the voltage signal at the detection pin based on the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information; the configuration function performed by the chip includes configuring the corresponding I2C address device information according to the voltage change at the detection pin or the change in the resistance value of the connected resistor, and automatically configuring the role configuration information and the device address based on the real-time detection result. During this configuration process, the configuration is automatically performed based on the voltage value of the voltage signal at the detection pin. The manufacturer does not need to distinguish the welding position of the chip in the circuit board, nor does it need to increase or decrease the number of pins for the same chip, nor does it need to repeatedly modify the firmware program stored in the same chip based on the change of the voltage signal at the detection pin.

[0023] In summary, this embodiment provides a detection pin in the chip connected to the I2C bus, and detects the voltage signal at the detection pin in real time by detecting the amount of electricity fed back by the detection resistor, and automatically configures the I2C master-slave role and device address of the chip based on the corresponding mapping relationship. It is not necessary for relevant technical personnel to burn matching firmware to the chip connected to the I2C bus according to the established welding position when leaving the factory. Even if the welding position is uncertain, it does not affect the correct configuration of the master and slave and their device addresses in the I2C bus without modifying the firmware. In this way, when the logic function of one of the chips connected to the I2C bus is configured, after the configuration of the chip that plays the role of the host is completed by burning, it is not necessary to modify the firmware before configuring it as a chip that plays the role of the slave. Instead, the I2C master-slave role and device address of the chip are automatically configured by the same firmware, thereby simplifying the process of producing chips that support I2C communication.

[0024] It should be noted that after a firmware is burned on the chip, the chip is used to configure the corresponding I2C address device information according to the voltage signal at the detection pin set by the chip, so that the chip can be recognized by the I2C bus after the I2C address device information is configured. When the voltage signal at the detection pin set by the chip changes, the voltage value (voltage amplitude value) of the voltage signal at the detection pin changes, and the I2C address device information corresponding to the chip will change, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, and it is solidified into the chip in the form of firmware. Therefore, configuring the corresponding I2C address device information according to the voltage signal at the detection pin set by the chip, or using the voltage signal at the detection pin to configure the I2C address device information based on the aforementioned mapping relationship is a logical function configured by the firmware to the chip.

[0025] As an example, combining Figure 1It can be seen that the chip includes a control unit, an I2C address device configuration module and a current source, wherein the detection resistor is equivalent to an external resistor of the chip and is connected to a detection pin set by the chip; the control unit can be a microcontroller (abbreviated as MCU), as a control core embedded in the chip. The current source is connected to the first end of the detection resistor, and the second end of the detection resistor is grounded; the detection resistor is used to receive the current output by the current source and generate a voltage signal at its first end; the detection pin is connected to the first end of the detection resistor, and the detection pin is used to collect the voltage signal generated by the first end of the detection resistor and configure the collected voltage signal as the voltage signal at the detection pin. The I2C address device configuration module is connected to the control unit; the control unit is used to detect the voltage value of the voltage signal at the detection pin, that is, to collect the voltage signal at the detection pin generated by the first end of the detection resistor, and based on the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, the I2C address device information is called from the I2C address device configuration module according to the voltage signal at the detection pin to configure the I2C address device information, and the called I2C address device information can be configured as the I2C address device information of the chip. This supports other devices connected to the I2C bus to identify the device address of the chip and access it through the I2C bus. Therefore, based on a chip disclosed in this embodiment, usually only one detection pin needs to be reserved, and there is no need to provide multiple pins for users to set. The setting of I2C address device information (including I2C address or device address) and the control of master and slave roles can be achieved through a completely software-based operation mode, which speeds up the process of producing chips that support I2C communication.

[0026] In some embodiments, the I2C address device configuration module is used to store the mapping relationship between the resistance value of the detection resistor and the I2C address device information, and the mapping relationship between the resistance value of the detection resistor and the I2C address device information includes the mapping relationship between the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, so that the control unit configures the I2C address device information according to the detection resistor, or the control unit uses the voltage signal at the detection pin to configure the corresponding I2C address device information based on the corresponding mapping relationship. The current source is used to generate a constant current, so that the voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor. Due to the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, a mapping relationship is formed between the I2C address device information and the detection resistor, and it is applicable to all chips of the same type connected to the I2C bus.

[0027] In some embodiments, a current source of 100uA flowing through the detection resistor will generate a voltage value U on the detection pin, that is, U=100uA×R0, where U is the voltage value of the voltage signal at the detection pin, and R0 is the resistance value of the detection resistor. The control unit will collect the voltage value U generated on the detection pin through an analog-to-digital converter. In actual application, the chip can distinguish the master-slave role and the device address according to the resistance value of the detection resistor connected to its detection pin or the voltage value of the voltage signal at the detection pin, where the I2C address device information includes the master-slave role configuration information and the device address. Preferably, when the current value flowing through the detection resistor remains unchanged, the voltage value of the voltage signal at the detection pin is directly proportional to the resistance value of the detection resistor connected to the detection pin, so that the voltage value of the voltage signal at the detection pin can provide real-time feedback on the resistance value of the detection resistor. As long as the chip is mounted on the circuit board (the specific position is not limited, and it does not need to be distinguished from other chips) and powered on, since there is a mapping relationship between the I2C address device information and the detection resistor, the chip can directly configure the corresponding I2C address device information according to the external resistance value of the detection pin.

[0028] In summary, a mapping relationship between the I2C address device information and the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin is constructed in the chip connected to the I2C bus, which can be compatible with the mapping relationship of the chip connected to the I2C bus, and improve the functional logic of the control unit to map the corresponding I2C address device information by controlling the detection resistor and the voltage signal at the detection pin. When the device address of the chip in the I2C bus needs to be modified, there is no need to burn different firmware according to different device addresses, but the I2C master-slave role and device address of the chip are automatically configured based on the corresponding mapping relationship, which simplifies the tediousness of burning different firmware due to the need to modify the master-slave role and device address.

[0029] Preferably, the chip further includes an analog-to-digital converter; the detection pin is connected to the collection end of the analog-to-digital converter; the analog-to-digital converter is used to collect the voltage signal at the detection pin generated by the first end of the detection resistor, and convert the collected voltage signal into a voltage identification value, which is equivalent to converting the analog voltage at the first end of the detection resistor into a digital voltage encoding value as the voltage sampling information of the chip at the detection pin. Figure 1It can be seen that the control unit is connected to the conversion output end of the analog-to-digital converter; the control unit is used to receive the voltage identification value and transmit it to the I2C address device configuration module, so as to detect the voltage signal generated by the first end of the detection resistor through the analog-to-digital converter. The control unit is used to call the I2C address device information corresponding to the voltage identification value from the I2C address device configuration module according to the voltage identification value; wherein the mapping relationship between the voltage identification value and the I2C address device information is the mapping relationship between the voltage value of the converted voltage signal and the I2C address device information, and the current source is used to generate a constant current so that the voltage identification value is proportional to the resistance value of the detection resistor. This embodiment converts the voltage value of the voltage signal at the detection pin into a digital signal that is easy for the control unit to identify and encode and process in real time through the analog-to-digital converter, thereby improving the efficiency of voltage value comparison and mapping.

[0030] As an embodiment of configuring a host device, the control unit calls the I2C address device information from the I2C address device configuration module according to the voltage value of the voltage signal at the detection pin, and configures the called I2C address device information as the I2C address device information. The method includes: when the control unit detects that the voltage value of the voltage signal at the detection pin is less than the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and the basis for the call at this time is the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information; and then the chip is configured as a host device or an I2C host chip according to the called role configuration information; and, the control unit detects the voltage value of the voltage signal at the detection pin and determines which host address identification voltage range it falls into; the control unit calls the corresponding device address from the I2C address device configuration module according to the host address identification voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C host address to form the device address of the host device or the device address of the I2C host chip, and the basis for the call at this time is the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the host device. In summary, the control unit configures the I2C address device information using the resistance value of the detection resistor based on the mapping relationship between the resistance value of the detection resistor connected to the detection pin and the voltage value of the voltage signal at the detection pin, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information and the device address.

[0031] In some embodiments, the mapping relationship between the resistance value of the detection resistor, the voltage value of the voltage signal at the detection pin, the role configuration information of the host device and the device address is as described in Table 1 below:

[0032]

[0033] A host identification voltage range corresponds to the role configuration information of a host device, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the host device, wherein the preset target voltage value is the upper limit value of the host identification voltage range, preferably 1.35V. A host identification voltage range is divided into multiple host address identification voltage ranges, wherein the host identification voltage range is preferably 0 to 1.35V, as described in Table 1, when the voltage signal at the detection pin falls within the host identification voltage range of 0 to 1.35V, the chip is configured as a host device or an I2C host chip, corresponding to Table 1 above, the role configuration information of the chip is the host, that is, the role configuration information of the host device.

[0034] Combined with Table 1, it can be seen that the host recognition voltage range of 0 to 1.35V is divided into 0.0000 to 0.3375V, 0.3375 to 0.6750V, 0.6750 to 1.0125V and 1.0125 to 1.3500V respectively. A host address identification voltage range corresponds to an I2C host address, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the host device, where the I2C host address is the device address of the host device; as described in Table 1, the host address identification voltage range of 0.0000 to 0.3375V corresponds to an address value 0 of an I2C host address, the host address identification voltage range of 0.3375 to 0.6750V corresponds to an address value 1 of an I2C host address, the host address identification voltage range of 0.6750 to 1.0125V corresponds to an address value 2 of an I2C host address, and the host address identification voltage range of 1.0125 to 1.3500V corresponds to an address value 3 of an I2C host address. Among them, the I2C address device information includes the role configuration information of the host device and its corresponding device address. In summary, whenever the boundary value (upper limit or lower limit) of the host address recognition voltage range increases by 0.3375V, the address value of the corresponding mapped I2C host address increases by 1, and starts from address value 0 until it increases to address value 4.

[0035] In Table 1, the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information includes the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the host device, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the host device. When the host address identification voltage range into which the voltage value of the voltage signal at the detection pin of the same chip falls changes, the address value of the device address assigned to the chip changes. For example, if the host address identification voltage range into which the voltage value generated by the detection resistor collected by the chip falls is 0.0000 to 0.3375V, it is mapped to the address value 0 of the I2C host address, and the chip is configured as an I2C host chip, and its device address is assigned to the address value 0; similarly, if the host address identification voltage range into which the voltage value generated by the detection resistor collected by the same chip falls is 0.3375 to 0.6750V, it is mapped to the address value 1 of the I2C host address, and the same chip is configured as an I2C host chip, and its device address is assigned to the address value 1.

[0036] Therefore, within the voltage range for identifying the host device, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board and whether it is identified as a host in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls within a host address recognition voltage range, the role configuration information and the device address can be determined by the sensing voltage at its detection pin (specifically the voltage signal generated by the external detection resistor).

[0037] Based on the above embodiments, combined with Table 1, it can be seen that the number of host address identification voltage ranges divided by a host identification voltage range is equal to the number of I2C host addresses stored in the I2C address device configuration module or the number of I2C host addresses required to be configured by the control unit, and the voltage change value covered by each host address identification voltage range is equal, and the specific value is equal to 0.3375V; corresponding to Table 1, the number of I2C host chips supported by the chip is 4.

[0038] In a chip configured as a host device or an I2C host chip, when the detection resistor is an adjustable resistor, the detection resistor is configured to have multiple host detection resistor adjustment ranges, wherein the resistance value of a detection resistor is configured to correspond to a host detection resistor adjustment range, corresponding to Table 1, and the host detection resistor adjustment ranges listed in Table 1 are 0.000 to 3.375 kΩ, 3.375 to 6.750 kΩ, 6.750 to 10.125 kΩ, and 10.125 to 13.500 kΩ, respectively. The host address identification voltage range of 0.0000 to 0.3375V corresponds to a host detection resistance adjustment range of 0.000 to 3.375kΩ. The ratio between the two values ​​can be regarded as the current value of 100uA output by the current source, and the voltage value of the voltage signal at the detection pin is directly proportional to the resistance value of the detection resistor; similarly, the host address identification voltage range of 0.3375 to 0.6750V corresponds to a host detection resistance adjustment range of 3.375 to 6.750kΩ, the host address identification voltage range of 0.6750 to 1.0125V corresponds to a host detection resistance adjustment range of 6.750 to 10.125kΩ, and the host address identification voltage range of 1.0125 to 1.3500V corresponds to a host detection resistance adjustment range of 10.125 to 13.500kΩ. Among them, the resistance change value covered by each host detection resistance adjustment range is equal, and the specific value is equal to 3.375kΩ.

[0039] The number of host detection resistance adjustment ranges corresponding to the resistance value of the detection resistor is equal to the number of divided host address identification voltage ranges, and the resistance change value covered by each host detection resistance adjustment range is equal. Corresponding to Table 1, the number of host detection resistance adjustment ranges corresponding to the detection resistor is 4, and the number of detection resistor resistance values ​​is 4; in the chip, when the resistance value of the detection resistor is adjusted to a host detection resistance adjustment range, the voltage value of the voltage signal at the detection pin is within a corresponding host address identification voltage range. It is only necessary to judge the host role configuration information and device address according to the set mapping relationship by the resistance value of the detection resistor after the chip is powered on, whenever the chip detects that the voltage value of the voltage signal at the detection pin can fall into a host address identification voltage range, thereby improving the production efficiency of chips supporting I2C communication.

[0040] Preferably, the I2C address device configuration module includes a memory, and the I2C address device configuration module can be a memory connected by multiple registers; the mapping relationship mentioned in the above embodiment stores the voltage value of the voltage signal at the detection pin and its corresponding I2C address device information in the form of a mapping table, that is, a mapping table in the register is formed, so that the storage address of the voltage value of a voltage signal at the detection pin is mapped to the storage address of the corresponding I2C address device information, wherein a host address identification voltage range in the memory is mapped to its corresponding role configuration information The storage address range of the storage address range in the memory, and a host address identification voltage range in the memory is mapped to the storage address range of the device address in the memory.

[0041] The mapping relationship also stores the resistance value of the detection resistor and the voltage value of the voltage signal at its first end in the form of a mapping table, the storage address range of the resistance value of a detection resistor in the memory is mapped to the voltage value of the voltage signal at the first end of a detection resistor (i.e., the voltage value of the voltage signal at the detection pin to which the detection resistor is connected) in the storage address range in the memory, and the storage address range of the voltage value of the voltage signal at the first end of a detection resistor in the memory falls within the storage address range of a host address recognition voltage range in the memory. Thus, the mapping relationship is implemented in the form of a mapping table to enumerate the resistance values ​​of multiple detection resistors, the voltage value of the voltage signal at the first end of a detection resistor, the host address recognition voltage range, and the I2C address device information, so as to use the memory to configure the mapping relationship for the chip in advance, so that when the control unit detects the voltage value of the corresponding voltage signal, the role configuration information and the device address are automatically mapped.

[0042] In some embodiments, the control unit includes an address selector, which is used to identify the voltage range of the host address according to the voltage value of the voltage signal at the detection pin falling into, and select the corresponding I2C host address for the chip based on the mapping relationship between the voltage value of the voltage signal at the aforementioned detection pin and the device address of the host device. The corresponding device address can be selected for the chip in the mapping table set in the I2C address device configuration module.

[0043] As an embodiment of configuring a slave device, the control unit calls the I2C address device information from the I2C address device configuration module according to the voltage signal at the detection pin, and configures the called I2C address device information as the method of the I2C address device information, including: when the control unit detects that the voltage value of the voltage signal at the detection pin is greater than or equal to the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and the basis for the call at this time is the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information; then, according to the called role configuration information, the chip where the control unit is located is configured as an I2C slave chip or slave device; and, the control unit detects the voltage value of the voltage signal at the detection pin and determines which slave address identification voltage range it falls into; the control unit determines the role configuration information according to the voltage value of the voltage signal at the detection pin The slave address falls into the slave address identification voltage range, calls the corresponding device address from the I2C address device configuration module, and then configures the called device address as the I2C slave address to form the device address of the slave device or the device address of the I2C slave chip. The basis for the call at this time is the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device; in summary, the control unit configures the I2C address device information according to the detection resistor based on the mapping relationship between the resistance value of the detection resistor connected to the detection pin and the voltage value of the voltage signal at the detection pin, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device. When the chip is configured as a slave device, it also configures the device address of the slave device or the device address of the I2C slave chip, so that other chips connected to the I2C bus can access the currently configured I2C slave chip.

[0044] In some embodiments, the mapping relationship between the resistance value of the detection resistor, the voltage value of the voltage signal at the detection pin, the role configuration information of the slave device and the device address is as described in Table 2 below:

[0045]

[0046] A slave identification voltage range corresponds to the role configuration information of a slave device, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the slave device, wherein the preset target voltage value is the lower limit of the slave identification voltage range, preferably 1.35V. A slave identification voltage range is divided into multiple slave address identification voltage ranges, wherein the slave identification voltage range is preferably 1.35 to 2.7V. As described in Table 2, when the voltage value of the voltage signal at the detection pin falls within a slave identification voltage range of 1.35 to 2.7V, the chip is configured as a slave device or an I2C slave chip, corresponding to Table 2 above, the role configuration information of the chip is a slave, that is, the role configuration information of the slave device.

[0047] Combined with Table 2, it can be seen that the slave identification voltage range of 1.35 to 2.7V is divided into 1.3500 to 1.6875V, 1.6875 to 2.0250V, 2.0250 to 2.3625V and 2.3625 to 2.7000V. A slave address identification voltage range corresponds to an I2C slave address, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device, where the I2C slave address is the device address of the slave device; as described in Table 2, the slave address identification voltage range of 1.3500 to 1.6875V corresponds to an address value of 4 of an I2C slave address, the slave address identification voltage range of 1.6875 to 2.0250V corresponds to an address value of 5 of an I2C slave address, the slave address identification voltage range of 2.0250 to 2.3625V corresponds to an address value of 6 of an I2C slave address, and the slave address identification voltage range of 2.3625 to 2.7000V corresponds to an address value of 6 of an I2C slave address. Among them, the I2C address device information includes the role configuration information of the slave device and its corresponding device address, the device address of the host device is the device address of the I2C host chip, and the device address of the slave device is the device address of the I2C slave chip. In summary, whenever the boundary value (upper limit or lower limit) of the slave address recognition voltage range increases by 0.3375V, the address value of the corresponding mapped I2C slave address increases by 1, and starts from address value 4 until it increases to address value 8.

[0048] In Table 2, the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information includes the mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the slave device, and the mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device. When the slave address identification voltage range into which the voltage value of the voltage signal at the detection pin of the same chip falls changes, the address value of the I2C slave address assigned to the chip changes. For example, if the voltage value generated by the detection resistor collected by the chip falls within the slave address identification voltage range of 1.6875 to 2.0250V, it is mapped to the address value 5 of the I2C slave address. The chip is configured as an I2C slave chip, and its device address is assigned to the address value 5; similarly, if the voltage value generated by the detection resistor collected by the chip falls within the slave address identification voltage range of 2.0250 to 2.3625V, it is mapped to the address value 6 of the I2C slave address. The chip is configured as an I2C slave chip, and its device address is assigned to the address value 6. Therefore, within the voltage range for identifying slave devices, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board, whether it is identified as a master slave in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls within a slave address identification voltage range, the device address of the I2C slave chip can be determined by the sensed voltage at its detection pin (specifically the voltage signal generated by the external detection resistor), that is, the I2C slave address is configured.

[0049] Based on the above embodiments, combined with Table 2, it can be seen that the number of slave address identification voltage ranges divided by a slave identification voltage range is equal to the number of I2C slave addresses stored in the I2C address device configuration module or the number of I2C slave addresses required to be configured by the control unit, and is also equal to the number of I2C slave chips, and the voltage change value covered by each slave address identification voltage range is equal, and the specific value is equal to 0.3375V; corresponding to Table 2, the adjustment ranges of the slave detection resistances listed in Table 2 are 13.500 to 16.875kΩ, 16.875 to 20.250kΩ, 20.250 to 23.625kΩ and 23.625 to 27.000kΩ respectively. Corresponding to the mapping relationship, the slave address identification voltage range of 1.3500 to 1.6875V corresponds to a slave detection resistance adjustment range of 13.500 to 16.875kΩ, and the ratio between the two values ​​can be regarded as the current value of 100uA output by the current source, and the voltage value of the voltage signal at the detection pin is directly proportional to the resistance value of the detection resistor; similarly, the slave address identification voltage range of 1.6875 to 2.0250V corresponds to a slave detection resistance adjustment range of 16.875 to 20.250kΩ, the host address identification voltage range of 2.0250 to 2.3625V corresponds to a slave detection resistance adjustment range of 20.250 to 23.625kΩ, and the host address identification voltage range of 2.3625 to 2.7000V corresponds to a slave detection resistance adjustment range of 23.625 to 27.000kΩ. Among them, the resistance change value covered by each slave detection resistor adjustment range is equal, and the specific value is equal to 3.375kΩ. The number of slave detection resistor adjustment ranges corresponding to the detection resistor is equal to the number of slave address identification voltage ranges divided, and the resistance change value covered by each slave detection resistor adjustment range is equal. Corresponding to Table 2, for a chip, the number of slave detection resistor adjustment ranges corresponding to the detection resistor is 4; in the chip, when the resistance value of the detection resistor is in a slave detection resistor adjustment range, the voltage value of the voltage signal generated by the first end of the detection resistor is in a corresponding slave address identification voltage range. It is only necessary to judge the slave role configuration information and the device address by the resistance value of the detection resistor according to the set mapping relationship after the chip is powered on, and improve the production efficiency of chips supporting I2C communication.

[0050] Preferably, the I2C address device configuration module includes a memory, and the I2C address device configuration module can be a memory connected by multiple registers; the mapping relationship mentioned in the above embodiment stores the voltage value of the voltage signal at the detection pin and its corresponding I2C address device information in the form of a mapping table, that is, a mapping table in the register is formed, so that the storage address of the voltage value of a voltage signal at the detection pin is mapped to the storage address of the corresponding I2C address device information, wherein a storage address range of a slave address identification voltage range in the memory is mapped to the storage address range of its corresponding role configuration information in the memory, and a storage address range of a slave address identification voltage range in the memory is mapped to the storage address range of the device address in the memory. The mapping relationship also stores the resistance value of the detection resistor and the voltage value of the voltage signal at its first end in the form of a mapping table, and the storage address range of the resistance value of a detection resistor in the memory is mapped to the voltage value of the voltage signal at the first end of a detection resistor (that is, the voltage value of the voltage signal at the detection pin connected to the detection resistor) in the storage address range in the memory, and the storage address range of the voltage value of the voltage signal at the first end of a detection resistor in the memory falls within the storage address range of a slave address identification voltage range in the memory. The mapping relationship is thereby implemented by enumerating the resistance values ​​of multiple detection resistors, the voltage value of the voltage signal at the first end of a detection resistor, the slave address identification voltage range, and the I2C address device information in the form of a mapping table, so as to use the memory to configure the mapping relationship for the chip in advance, so that when the control unit detects the voltage value of the corresponding voltage signal, the role configuration information and the device address are automatically mapped.

[0051] In some embodiments, the control unit includes an address selector, which is used to identify the voltage range of the slave address according to the voltage value of the voltage signal at the detection pin falling into, and select the corresponding I2C slave address for the chip based on the mapping relationship between the voltage value of the voltage signal at the aforementioned detection pin and the device address of the slave device. The corresponding device address may be selected for the chip in a mapping table set in the I2C address device configuration module.

[0052] Based on the aforementioned embodiment, a circuit structure is also disclosed, which includes a detection resistor and the chip disclosed in the aforementioned embodiment, wherein the first end of the detection resistor is connected to the detection pin of the chip, the second end of the detection resistor is grounded, and the chip is connected to the I2C bus so that the circuit structure is connected to the I2C bus. Based on the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, the chip uses the voltage signal at the detection pin to configure the I2C address device information, including role configuration information and device address. When the chip is configured as an I2C slave chip, the circuit structure is configured as a slave device; when the chip is configured as an I2C host chip, the circuit structure is configured as a host device. It should be supplemented that, Figure 1 As shown, the serial data line SDA of the I2C bus is pulled up to the power supply voltage 3.3V through the pull-up resistor 1, and the serial clock line SCL of the I2C bus is pulled up to the power supply voltage 3.3V through the pull-up resistor 2; thus, in the process of configuring the I2C address device information for the circuit structure, the normal I2C communication is not affected.

[0053] In the circuit structure, the chip is used to configure the I2C address device information using the voltage signal at the detection pin based on the mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information; the configuration function performed by the chip includes configuring the corresponding I2C address device information according to the voltage change at the detection pin or the change in the resistance value of the connected resistor, and automatically configuring the role configuration information and the device address according to the real-time detection result. In this configuration process, the voltage value of the voltage signal at the detection pin (the first end of the detection resistor) is automatically configured, and the manufacturer does not need to distinguish the welding position of the chip in the circuit board, and there is no need to repeatedly modify the firmware program stored in the same chip according to the change of the voltage signal at the detection pin. Therefore, based on the circuit structure disclosed in this embodiment, usually only one detection pin needs to be retained, and there is no need to provide multiple pins for users to set. The setting of the I2C address device information (including the I2C address or the device address) and the control of the master and slave roles can be realized through a completely software operation mode, thereby improving the production efficiency of the chip supporting I2C communication in the circuit structure, or the installation efficiency and adaptability of the chip supporting I2C communication in the circuit structure.

[0054] Preferably, for the voltage signal at the detection pin, within the voltage range where the voltage value is less than the preset target voltage value, there are multiple different host address identification voltage ranges, and each host address identification voltage range and each slave address identification voltage range support being identified by the same pre-burned firmware and configuring the I2C address device information of the circuit structure based on the corresponding mapping relationship, that is, accepting the mapping relationship disclosed in Table 1 and Table 2, so as to trigger the circuit structure to identify in real time and configure the corresponding role configuration information and the corresponding device address in the I2C bus for the chip that needs to play the same role or different roles by connecting the detection resistor with the corresponding resistance value, and the circuit structure is also configured with the corresponding role configuration information and assigned to the corresponding device address. Therefore, it is only necessary that after the circuit structure is powered on, whenever the firmware in the chip detects that the voltage value of the voltage signal at the detection pin falls into a host address identification voltage range or a slave address identification voltage range, the firmware in the chip can determine the master-slave role configuration information and the device address according to the set mapping relationship by the resistance value of the detection resistor.

[0055] The above embodiments are only for full disclosure rather than limitation of the present invention. Any replacement of equivalent technical features based on the creative purpose of the present invention without creative work should be regarded as the scope disclosed by this application.

Claims

1. A chip for configuring I2C address device information, characterized in that: The chip is connected to the I2C bus; the chip is provided with a detection pin, the detection pin of the chip is connected to the detection resistor, and when the resistance value of the detection resistor changes, the voltage value of the voltage signal at the detection pin changes; The chip stores a mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information; The chip is used to configure the I2C address device information based on the aforementioned mapping relationship using the voltage signal at the detection pin.

2. The chip according to claim 1, characterized in that: The chip includes a control unit, an I2C address device configuration module and a current source; The current source is connected to the first end of the detection resistor, and the second end of the detection resistor is grounded; the detection resistor is used to receive the current output by the current source and generate a voltage signal at its first end; The detection pin is connected to the first end of the detection resistor, and the detection pin is used to collect the voltage signal generated by the first end of the detection resistor, wherein the voltage signal generated by the first end of the detection resistor is the voltage signal at the detection pin; The I2C address device configuration module is connected to the control unit; the control unit is used to detect the voltage value of the voltage signal at the detection pin, and based on the determined mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, call the I2C address device information from the I2C address device configuration module according to the voltage value of the voltage signal at the detection pin to configure the I2C address device information.

3. The chip according to claim 2, characterized in that: The I2C address device configuration module is used to store the mapping relationship between the resistance value of the detection resistor and the I2C address device information, wherein the mapping relationship between the resistance value of the detection resistor and the I2C address device information includes a mapping relationship between the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin, and a mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information, so that the control unit configures the I2C address device information according to the detection resistor; The current source is used to generate a constant current, so that the voltage value of the voltage signal at the detection pin is proportional to the resistance value of the detection resistor, forming a mapping relationship between the resistance value of the detection resistor and the voltage value of the voltage signal at the detection pin.

4. The chip according to claim 3, characterized in that: The chip also includes an analog-to-digital converter; The detection pin is connected to the collection end of the analog-to-digital converter; the analog-to-digital converter is used to collect the voltage signal generated by the first end of the detection resistor and convert the collected voltage signal into a voltage identification value; The control unit is connected to the conversion output end of the analog-to-digital converter; the control unit is used to receive the voltage identification value and transmit it to the I2C address device configuration module, so as to detect the voltage signal generated by the first end of the detection resistor through the analog-to-digital converter; The control unit is used to call the I2C address device information corresponding to the voltage identification value from the I2C address device configuration module according to the voltage identification value; wherein the mapping relationship between the voltage identification value and the I2C address device information is the mapping relationship between the voltage value of the converted voltage signal and the I2C address device information.

5. The chip according to claim 3, characterized in that: The control unit calls the I2C address device information from the I2C address device configuration module according to the voltage value of the voltage signal at the detection pin, and configures the called I2C address device information as the I2C address device information, including: When the control unit detects that the voltage value of the voltage signal at the detection pin is less than the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and the chip is configured as a host device or an I2C host chip according to the called role configuration information; and the control unit is used to call the device address from the I2C address device configuration module according to the host address recognition voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configure the called device address as the I2C host address, thereby forming the device address of the host device or the device address of the I2C host chip.

6. The chip according to claim 5, characterized in that: One host identification voltage range corresponds to one host device role configuration information, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the host device; wherein the preset target voltage value is the upper limit value of the host identification voltage range; A host identification voltage range is divided into a plurality of host address identification voltage ranges, wherein one host address identification voltage range corresponds to one I2C host address, forming a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the host device; The mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information includes a mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the host device, and a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the host device; The I2C address device information includes the role configuration information of the host device and its corresponding device address; the device address of the host device is the device address of the I2C host chip.

7. The chip according to claim 6, characterized in that: The number of host address identification voltage ranges divided by a host identification voltage range is equal to the number of I2C host addresses stored in the I2C address device configuration module or the number of I2C host addresses required to be configured by the control unit; the voltage change value covered by each host address identification voltage range is equal; When the detection resistor is an adjustable resistor, the detection resistor is configured to have a plurality of host detection resistor adjustment ranges, the number of host detection resistor adjustment ranges is equal to the number of host address identification voltage ranges, and the resistance change value covered by each host detection resistor adjustment range is equal; When the resistance value of the detection resistor is adjusted to a host detection resistor adjustment range, the voltage value of the voltage signal at the detection pin is within a corresponding host address identification voltage range.

8. The chip according to claim 3, characterized in that: The control unit calls the I2C address device information from the I2C address device configuration module according to the voltage value of the voltage signal at the detection pin, and configures the called I2C address device information as the I2C address device information, including: When the control unit detects that the voltage value of the voltage signal at the detection pin is greater than or equal to the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and the chip is configured as a slave device or an I2C slave chip according to the called role configuration information; and the control unit is used to call the device address from the I2C address device configuration module according to the slave address recognition voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configure the called device address as the I2C slave address, thereby forming the device address of the slave device or the device address of the I2C slave chip.

9. The chip according to claim 8, characterized in that: One slave identification voltage range corresponds to one slave device role configuration information, forming a mapping relationship between the voltage signal and the slave device role configuration information; wherein the preset target voltage value is the lower limit value of the slave identification voltage range; A slave identification voltage range is divided into a plurality of slave address identification voltage ranges, and a slave address identification voltage range corresponds to an I2C slave address, so as to form a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device; The mapping relationship between the voltage value of the voltage signal at the detection pin and the I2C address device information includes a mapping relationship between the voltage value of the voltage signal at the detection pin and the role configuration information of the slave device, and a mapping relationship between the voltage value of the voltage signal at the detection pin and the device address of the slave device; The I2C address device information includes the role configuration information of the slave device and its corresponding device address; the device address of the slave device is the device address of the I2C slave chip.

10. The chip according to claim 9, characterized in that: The number of slave address identification voltage ranges divided by a slave identification voltage range is equal to the number of I2C slave addresses stored in the I2C address device configuration module or the number of I2C slave addresses required to be configured by the control unit, and the voltage change value covered by each slave address identification voltage range is equal; When the detection resistor is an adjustable resistor, the detection resistor is configured to have a plurality of slave detection resistor adjustment ranges, the number of slave detection resistor adjustment ranges is equal to the number of slave address identification voltage ranges, and the resistance variation value covered by each slave detection resistor adjustment range is equal; When the resistance value of the detection resistor is adjusted to a slave detection resistor adjustment range, the voltage value of the voltage signal generated by the first end of the detection resistor is within a corresponding slave address recognition voltage range.

11. The chip according to claim 7 or 10, characterized in that: The I2C address device configuration module includes a memory, in which the mapping relationship stores the voltage value of the voltage signal at the detection pin and the corresponding I2C address device information in the form of a mapping table, so that the storage address of the voltage value of a voltage signal at the detection pin is mapped to the storage address of the corresponding I2C address device information; The mapping relationship also stores the resistance value of the detection resistor and the voltage value of the voltage signal at its first end in the form of a mapping table, so that the storage address of the resistance value of a detection resistor is mapped to the storage address of the voltage value of the voltage signal at the first end of a detection resistor.

12. A circuit structure, characterized in that: The circuit structure includes a detection resistor and a chip as described in any one of claims 1 to 11, wherein the first end of the detection resistor is connected to the detection pin of the chip, the second end of the detection resistor is grounded, and the chip is connected to an I2C bus so that the circuit structure is connected to the I2C bus.

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