Collaborative simulation communication system based on shared memory
By using shared memory to form a ring buffer message queue in the collaborative simulation scenario of FPGA chip, data is directly transmitted in memory, which solves the delay problem caused by network communication and achieves efficient communication efficiency improvement.
Patent Information
- Application Number
- CN202411160805.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2024-12-17
AI Technical Summary
In the collaborative simulation scenario of FPGA chips, the network communication-based API causes the message processing delay between the test platform and the FPGA chip to be too high, making it difficult to meet performance requirements, and communication efficiency needs to be improved.
Using a collaborative simulation communication system based on shared memory, create memory space through preset memory mapping functions to form a ring buffer message queue. The test platform and the running platform directly write and read data in memory to avoid system calls and process contexts Switch.
The communication efficiency between the test platform and the FPGA chip is significantly improved, with a performance improvement of about 40 times, meeting the high performance needs of collaborative simulation.
Smart Images
Figure CN119150770A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip simulation, and in particular to a collaborative simulation communication system based on shared memory. Background Art
[0002] Typically, FPGA chip clusters are managed through a runtime platform (Runtime), which provides a unified application programming interface (API) based on network communication to support client access. The interface encapsulation of FPGA chips implemented through the runtime platform can better reuse the resources of FPGA chips. However, providing services through an API based on network communication can also bring more serious performance issues.
[0003] In the scenario of chip simulation verification, collaborative simulation can use hardware accelerators to collaborate with software to accelerate simulation. In the scenario of using hardware accelerators based on FPGA chips, collaborative simulation needs to be achieved through mutual function calls between the test platform and the FPGA chip. The calling frequency between the test platform and the FPGA chip is very high, and the performance requirements are as high as possible. If the above-mentioned API based on network communication is used to provide calling services between the test platform and the FPGA chip, the message processing delay is too high, and it is difficult to meet the performance requirements of collaborative simulation.
[0004] Therefore, how to improve the communication efficiency between the test platform and the FPGA chip has become an urgent problem to be solved. Summary of the invention
[0005] In view of the above technical problems, the technical solution adopted by the present invention is:
[0006] A collaborative simulation communication system based on shared memory comprises: a test platform, a running platform and an FPGA chip.
[0007] The operating platform is used to create a first memory and a second memory through a preset memory mapping function, the first memory includes a first subspace and a second subspace, the second memory includes a third subspace and a fourth subspace, the first subspace is used to store first metadata, and the third subspace is used to store second metadata.
[0008] The second subspace is defined as a first ring buffer, the fourth subspace is defined as a second ring buffer, the first ring buffer and the second ring buffer form a message queue, the first metadata is used to maintain the data structure of the first ring buffer, and the second metadata is used to maintain the data structure of the second ring buffer.
[0009] The test platform is used to write first data into the message queue, and to read second data from the message queue. The second data is pushed to the running platform by the FPGA chip and written into the message queue by the running platform.
[0010] The operating platform is also used to read the first data from the message queue and send the first data to the FPGA chip.
[0011] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, the collaborative simulation communication system based on shared memory provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:
[0012] The present invention provides a collaborative simulation communication system based on shared memory. The system includes: a test platform, an operation platform and an FPGA chip. The operation platform is used to create a first memory and a second memory through a preset memory mapping function. The first memory includes a first subspace and a second subspace. The second memory includes a third subspace and a fourth subspace. The first subspace is used to store first metadata, and the third subspace is used to store second metadata. The second subspace is defined as a first ring buffer, and the fourth subspace is defined as a second ring buffer. The first ring buffer and the second ring buffer form a message queue. The first metadata is used to maintain the data structure of the first ring buffer, and the second metadata is used to maintain the data structure of the second ring buffer. The test platform is used to write first data into the message queue and to read second data from the message queue. The second data is pushed to the operation platform by the FPGA chip and written into the message queue by the operation platform. The operation platform is also used to read the first data from the message queue and send the first data to the FPGA chip.
[0013] It can be seen that compared with transmitting data through the network, using the first memory and the second memory for data transmission can avoid system calls and thus avoid process context switching, thereby improving the efficiency of data transmission and improving the communication efficiency between the test platform and the FPGA chip in the collaborative simulation scenario. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0015] Figure 1 A schematic diagram of the system architecture of a shared memory-based collaborative simulation communication system provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0017] This embodiment provides a shared memory-based collaborative simulation communication system, characterized in that the system includes: a test platform, a running platform and an FPGA chip;
[0018] The operating platform is used to create a first memory and a second memory through a preset memory mapping function, the first memory includes a first subspace and a second subspace, the second memory includes a third subspace and a fourth subspace, the first subspace is used to store first metadata, and the third subspace is used to store second metadata;
[0019] The second subspace is defined as a first ring buffer, the fourth subspace is defined as a second ring buffer, the first ring buffer and the second ring buffer form a message queue, the first metadata is used to maintain a data structure of the first ring buffer, and the second metadata is used to maintain a data structure of the second ring buffer;
[0020] The test platform is used to write first data into the message queue, and to read second data from the message queue, the second data is pushed by the FPGA chip to the operation platform, and is written into the message queue by the operation platform;
[0021] The operating platform is also used to read the first data from the message queue and send the first data to the FPGA chip.
[0022] Among them, the test platform (TestBench) can be used to describe the changes in test signals and the test process, so as to execute and verify the functional correctness of the hardware model during the simulation process. In the collaborative simulation scenario, the FPGA chip can be used as a hardware accelerator, and the hardware accelerator can be used to verify the timing part and the design part to be tested in the test platform to maximize the performance of the hardware accelerator. The runtime is a system process that can be used to manage FPGA chips.
[0023] See also Figure 1, is a schematic diagram of a system architecture of a collaborative simulation communication system based on shared memory provided by an embodiment of the present invention, such as Figure 1 As shown, the data flow from the test platform to the FPGA chip is from the test platform to the running platform and then to the FPGA chip, and the data flow from the FPGA chip to the test platform is from the FPGA chip to the running platform and then to the test platform. That is, the test platform transmits messages to the running platform by writing to the shared memory. The running platform pushes the messages to the corresponding FPGA chip after receiving them. The FPGA chip pushes the messages to the running platform. The running platform writes the messages to the shared memory. The test platform obtains the messages from the FPGA chip by reading the shared memory.
[0024] The preset memory mapping function may refer to an MMAP function. The first memory and the second memory are both shared memories. Both the test platform and the running platform can access the shared memories at will. The second subspace and the fourth subspace are both ring buffer data structures (ring buffer) to support bidirectional data transmission between the test platform and the FPGA chip.
[0025] Specifically, the prior condition of this embodiment is that the test platform and the running platform are located in the same host and belong to different processes of the same host.
[0026] In the locked communication mode, the performance of the test platform is about 8us / call. In the unlocked communication mode provided in this embodiment, the performance of the test platform is about 0.2us / call. It can be seen that in the collaborative simulation scenario, this embodiment can improve the communication efficiency between the test platform and the FPGA chip.
[0027] It should be noted that, in this embodiment, the system processes information in a polling manner, so that the system does not fall into a sleep state, further improving the transmission efficiency.
[0028] In a specific implementation, both the first metadata and the second metadata are defined by atomic variables.
[0029] Among them, an atomic variable may refer to a special data type used to perform atomic operations, and an atomic operation may refer to an indivisible operation. The atomic operation performed on the atomic variable can ensure thread-safe execution in a multi-threaded environment.
[0030] In a specific implementation, there is padding data between the first metadata and the second metadata;
[0031] The filling data is used to make the cache line corresponding to the first metadata different from the cache line corresponding to the second metadata.
[0032] The size corresponding to the padding data may be the cache line size minus one. By adding the padding data, false sharing can be avoided, thereby achieving higher performance.
[0033] In a specific implementation, the message queue is a single-read single-write queue.
[0034] The first metadata is equivalent to the tail pointer of the message queue, and the second metadata is equivalent to the head pointer of the message queue.
[0035] In a specific implementation, when a first processing operation is performed on the first metadata, the first processing operation corresponds to a first memory order, and when a processing operation is performed on the second metadata, the second processing operation corresponds to a second memory order;
[0036] When writing the first target data into the message queue, the first metadata is loaded, the first memory order corresponding to the first processing operation of loading the first metadata is the first preset order, and the first target data is the first data or the second data;
[0037] Increment the first metadata by 1 to obtain first updated data;
[0038] If the first update data is consistent with the length corresponding to the message queue, the first update data is set to zero;
[0039] Loading the second metadata, if the first update data is the same as the second metadata, returning a write failure, and the second memory order corresponding to the second processing operation of loading the second metadata is a second preset order;
[0040] Otherwise, the first target data is written into the position corresponding to the first metadata in the message queue, and the first update data is used to update the first metadata, and the first memory order corresponding to the first processing operation of updating the first metadata using the first update data is the third preset order.
[0041] Among them, since the first metadata and the second metadata are both atomic variables, the first processing operation may refer to an atomic operation performed on the first metadata, and the memory order corresponding to the atomic operation is the first memory order. The second processing operation may refer to an atomic operation performed on the second metadata, and the memory order corresponding to the atomic operation is the second memory order.
[0042] Specifically, increasing the first metadata by 1 may mean increasing the queue tail pointer by 1. If the first update data is consistent with the length corresponding to the message queue, it means that it is necessary to return to the starting position of the message queue, so the first update data is set to zero.
[0043] In this embodiment, the consistency of the message is ensured by using the memory model of the CPU, that is, the memory model corresponding to the memory order.
[0044] In a specific implementation, when the first target data is read from the message queue, the second metadata is loaded, and the second memory order corresponding to the second processing operation of loading the second metadata is the first preset order;
[0045] The first metadata is loaded, and if the second metadata is the same as the first metadata, a read failure is returned, and the first memory order corresponding to the first processing operation of loading the first metadata is the second preset order;
[0046] otherwise, reading the first target data from the position corresponding to the second metadata in the message queue;
[0047] Increment the second metadata by 1 to obtain second updated data;
[0048] If the second update data is consistent with the length corresponding to the message queue, the second update data is set to zero;
[0049] The second updated data is used to update the second metadata, and a second memory order corresponding to the second processing operation of using the second updated data to update the second metadata is a third preset order.
[0050] Increasing the second metadata by 1 may refer to increasing the queue head pointer by 1. If the second update data is consistent with the length corresponding to the message queue, it means that it is necessary to return to the starting position of the message queue, so the second update data is set to zero.
[0051] In a specific implementation, the first preset order is a relaxed memory order.
[0052] Among them, the relaxed memory order means that the corresponding atomic operations can be reordered, and there is no need to ensure that other threads see the modified values immediately.
[0053] In a specific implementation, the second preset order is the acquire memory order, and the third preset order is the release memory order.
[0054] Among them, the acquire memory order can be used to ensure that the read operation before the corresponding atomic operation can be completed in the memory, and the subsequent read and write operations cannot be reordered before the atomic operation, thereby ensuring that the thread can safely read the data written by other threads and ensure that the read data is the latest updated.
[0055] The release memory order can be used to ensure that the write operation after the corresponding atomic operation cannot be reordered before the atomic operation, and the read and write operations before the atomic operation cannot be reordered after the atomic operation, thereby ensuring that the thread can safely write data to be released to other threads and ensuring that the data seen by other threads is the latest update.
[0056] Compared with transmitting data through the network, this embodiment uses the first memory and the second memory for data transmission, which can avoid system calls and further avoid process context switching, thereby improving the efficiency of data transmission and improving the communication efficiency between the test platform and the FPGA chip in the collaborative simulation scenario.
[0057] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.
Claims
1. A collaborative simulation communication system based on shared memory, characterized in that: The system includes: a test platform, an operation platform and an FPGA chip; The operating platform is used to create a first memory and a second memory through a preset memory mapping function, the first memory includes a first subspace and a second subspace, the second memory includes a third subspace and a fourth subspace, the first subspace is used to store first metadata, and the third subspace is used to store second metadata; The second subspace is defined as a first ring buffer, the fourth subspace is defined as a second ring buffer, the first ring buffer and the second ring buffer form a message queue, the first metadata is used to maintain a data structure of the first ring buffer, and the second metadata is used to maintain a data structure of the second ring buffer; The test platform is used to write first data into the message queue, and to read second data from the message queue, the second data is pushed by the FPGA chip to the operation platform, and is written into the message queue by the operation platform; The operating platform is also used to read the first data from the message queue and send the first data to the FPGA chip.
2. The shared memory-based collaborative simulation communication system according to claim 1, characterized in that: The first metadata and the second metadata are both defined by atomic variables.
3. The shared memory-based collaborative simulation communication system according to claim 2, characterized in that: There is padding data between the first metadata and the second metadata; The filling data is used to make the cache line corresponding to the first metadata different from the cache line corresponding to the second metadata.
4. The shared memory-based collaborative simulation communication system according to claim 1, characterized in that: The message queue is a single-read and single-write queue.
5. The shared memory-based collaborative simulation communication system according to claim 1, characterized in that: When a first processing operation is performed on the first metadata, the first processing operation corresponds to a first memory order, and when a processing operation is performed on the second metadata, the second processing operation corresponds to a second memory order; When writing the first target data into the message queue, the first metadata is loaded, the first memory order corresponding to the first processing operation of loading the first metadata is the first preset order, and the first target data is the first data or the second data; Increment the first metadata by 1 to obtain first updated data; If the first update data is consistent with the length corresponding to the message queue, the first update data is set to zero; Loading the second metadata, if the first update data is the same as the second metadata, returning a write failure, and the second memory order corresponding to the second processing operation of loading the second metadata is a second preset order; Otherwise, the first target data is written into the position corresponding to the first metadata in the message queue, and the first update data is used to update the first metadata, and the first memory order corresponding to the first processing operation of updating the first metadata using the first update data is the third preset order.
6. The shared memory-based collaborative simulation communication system according to claim 5, characterized in that: When the first target data is read out from the message queue, the second metadata is loaded, and the second memory order corresponding to the second processing operation of loading the second metadata is the first preset order; The first metadata is loaded, and if the second metadata is the same as the first metadata, a read failure is returned, and the first memory order corresponding to the first processing operation of loading the first metadata is the second preset order; otherwise, reading the first target data from the position corresponding to the second metadata in the message queue; Increment the second metadata by 1 to obtain second updated data; If the second update data is consistent with the length corresponding to the message queue, the second update data is set to zero; The second updated data is used to update the second metadata, and a second memory order corresponding to the second processing operation of using the second updated data to update the second metadata is a third preset order.
7. The shared memory-based collaborative simulation communication system according to claim 6, characterized in that: The first preset order is a relaxed memory order.
8. The shared memory-based collaborative simulation communication system according to claim 7, characterized in that: The second preset order is the acquire memory order, and the third preset order is the release memory order.