Scanning driving circuit, display device and scanning driving circuit control method

Abstract

The invention relates to a scanning driving circuit, a display device and a scanning driving circuit control method, the scanning driving circuit comprises a plurality of cascaded grid scanning driving circuits, and each grid scanning driving circuit comprises a control unit, an independent driving unit, a first output unit, a second output unit and a pull-down unit; the control unit is connected with the first output unit, the independent driving unit and the pull-down unit; the independent driving unit is connected with the first output unit and the second output unit; the pull-down unit is connected with the first output unit and the second output unit. The independent driving unit of the scanning driving circuit can control the first output unit and the second output unit to output two overlapped scanning signals under the action of the control unit, so that the output scanning signals can independently work in the output period, the operation stability of the scanning driving circuit is improved, and the scanning driving circuit is simple in structure and convenient to operate. The first output unit and the second output unit share one control unit, so that the circuit area can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a scan drive circuit, a display device, and a scan drive circuit control method. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) compensation technology is a series of technical innovation strategies designed to solve the defects of uneven brightness and afterimage in the manufacturing and use of AMOLED displays. These technologies use a combination of software and hardware methods to optimize the luminous efficiency of each pixel, thereby significantly improving the overall image quality of the display.

[0003] Compensation strategies are divided into two categories: internal and external. External compensation strategies are common in commercial organic light-emitting semiconductor OLED TVs, and are specifically used to correct the threshold voltage (VTH) of IGZO TFT (indium gallium zinc oxide thin film transistor). Although this solution simplifies the pixel circuit design, it requires additional drive system support, so the production cost has increased. On the other hand, the internal compensation circuit technology based on IGZO TFT requires a special structure built into the scanning drive circuit to avoid potential problems. This requirement will inevitably increase the overall area of ​​the circuit, which is contrary to the current pursuit of high resolution to reduce the available circuit area to create narrow-border display products. Therefore, how to ensure the stable operation of the system without increasing the circuit area has become an urgent problem to be solved. Summary of the invention

[0004] The present application provides a scan drive circuit, a display device and a scan drive circuit control method to solve the technical problem of how to ensure stable operation of the system while not increasing the circuit area.

[0005] In a first aspect, the present application provides a scan driving circuit, the scan driving circuit comprising a plurality of cascaded gate scanning driving circuits, the gate scanning driving circuit comprising: a control unit, an independent driving unit, a first output unit, a second output unit and a pull-down unit; The control unit is connected to the first output unit, the independent driving unit and the pull-down unit; the independent driving unit is connected to the first output unit and the second output unit; the pull-down unit is connected to the first output unit and the second output unit; Under the action of the control unit, the independent driving unit controls the first output unit and the second output unit to output two overlapping scanning signals.

[0006] Optionally, the independent driving unit includes a clock signal unit and a driving switch; The first output unit outputs a first scanning signal based on the first clock signal of the clock signal unit under the action of the driving switch; The second output unit outputs a second scanning signal based on the second clock signal of the clock signal unit under the action of the driving switch; The first scanning signal and the second scanning signal at least partially overlap.

[0007] Optionally, the control unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a tenth thin film transistor; A first end of the first thin film transistor is connected to a previous stage gate scanning signal, a second end of the first thin film transistor is connected to a first end of the second thin film transistor, a first end of the fourth thin film transistor, a gate of the sixth thin film transistor, a gate of the seventh thin film transistor, a gate of the eighth thin film transistor and a first sampling node of the first output unit; a second end of the second thin film transistor is connected to a first end of the third thin film transistor, a second end of the fourth thin film transistor, a first end of the fifth thin film transistor and a second end of the sixth thin film transistor; The gate of the fourth thin film transistor is connected to the gate of the fifth thin film transistor, the first end of the seventh thin film transistor, the second end of the tenth thin film transistor and the second sampling node, and the second sampling node is connected to the gate of the ninth thin film transistor and the pull-down unit; The second end of the seventh thin film transistor is connected to the first end of the eighth thin film transistor and the first end of the ninth thin film transistor; The first end of the sixth thin film transistor, the first end of the tenth thin film transistor and the second end of the ninth thin film transistor are connected to a high level; the second end of the third thin film transistor, the second end of the fifth thin film transistor and the second end of the eighth thin film transistor are connected to a low level; The gate of the first thin film transistor is connected to the level transmission signal of the previous stage; the gate of the second thin film transistor is connected to the gate of the third thin film transistor and the level transmission signal of the next stage; The gate of the tenth thin film transistor is connected to the control terminal of the driving switch and a fourth clock signal.

[0008] Optionally, the first output unit includes an eleventh thin film transistor and a first capacitor; The first end of the eleventh thin film transistor is connected to the first clock signal, the gate of the eleventh thin film transistor, the first end of the first capacitor and the first end of the driving switch are commonly connected to the first sampling node, and the second end of the eleventh thin film transistor is connected to the second end of the first capacitor; the second end of the eleventh thin film transistor is used to output a first scanning signal.

[0009] Optionally, the second output unit includes a thirteenth thin film transistor and a second capacitor; The first end of the thirteenth thin film transistor is connected to the second clock signal, the gate of the thirteenth thin film transistor, the first end of the second capacitor and the second end of the driving switch are commonly connected to the third sampling node of the second output unit, and the second end of the thirteenth thin film transistor is connected to the second end of the second capacitor; the second end of the thirteenth thin film transistor is used to output the second scanning signal.

[0010] Optionally, the pull-down unit includes a twelfth thin film transistor and a fourteenth thin film transistor; The first end of the twelfth thin film transistor is connected to the second end of the eleventh thin film transistor, the gate of the twelfth thin film transistor and the gate of the fourteenth thin film transistor are commonly connected to the second sampling node, and the second end of the twelfth thin film transistor and the second end of the fourteenth thin film transistor are commonly connected to a low level; The first end of the fourteenth thin film transistor is connected to the second end of the thirteenth thin film transistor.

[0011] Optionally, the gate scanning driving circuit further includes a level transmission output unit, and the level transmission output unit includes a fifteenth thin film transistor and a sixteenth thin film transistor; A first end of the fifteenth thin film transistor is connected to a first end of the thirteenth thin film transistor, a gate of the fifteenth thin film transistor is connected to a gate of the thirteenth thin film transistor, a second end of the fifteenth thin film transistor is connected to a first end of the sixteenth thin film transistor, a gate of the sixteenth thin film transistor is connected to a gate of the fourteenth thin film transistor, and a second end of the sixteenth thin film transistor is connected to a low level; The second end of the fifteenth thin film transistor and the first end of the sixteenth thin film transistor jointly output the stage transmission signal of the current stage.

[0012] Optionally, the driving switch includes a seventeenth thin film transistor; A first end of the seventeenth thin film transistor is connected to the gate of the eleventh thin film transistor, a second end of the seventeenth thin film transistor is connected to the third sampling node, and a gate of the seventeenth thin film transistor is connected to the gate of the tenth thin film transistor.

[0013] In a second aspect, the present application provides a display device, including: a display panel and a driving circuit; The display panel comprises a pixel unit array; the driving circuit is used to drive the pixel units and comprises the scanning driving circuit described in any one of the first aspects.

[0014] In a third aspect, the present application provides a scan drive circuit control method, the scan drive circuit control method is applied to the scan drive circuit as described in any one of the first aspects, the scan drive circuit control method comprising: The first output unit and the second output unit are controlled by an independent driving unit to output two overlapping scanning signals.

[0015] The above technical solution provided by the embodiment of the present application has the following advantages over the prior art: the scan drive circuit provided by the embodiment of the present application includes a plurality of cascaded gate scan drive circuits, and the gate scan drive circuit includes: a control unit, an independent drive unit, a first output unit, a second output unit and a pull-down unit; the control unit is connected to the first output unit, the independent drive unit and the pull-down unit; the independent drive unit is connected to the first output unit and the second output unit; the pull-down unit is connected to the first output unit and the second output unit. The independent drive unit of the scan drive circuit can control the first output unit and the second output unit to output two overlapping scan signals under the control of the control unit, so that the output scan signals can work independently during the output period, thereby improving the operation stability of the scan drive circuit, and since the first output unit and the second output unit share a control unit, the circuit area can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0019] Figure 1A schematic diagram of a scan driving circuit provided by an embodiment of the present application; Figure 2 A schematic diagram of the structure of a scan drive circuit provided by one embodiment of the present application; Figure 3 A timing diagram of a signal provided for one embodiment of the present application; Figure 4 A schematic diagram of a reset phase provided by an embodiment of the present application; Figure 5 A schematic diagram of a pre-charging stage provided for one embodiment of the present application; Figure 6 A schematic diagram of a pre-charge voltage holding stage provided for an embodiment of the present application.

[0020] The figures are as follows: 101-control unit; 102-independent driving unit; 103-first output unit; 104-second output unit; 105-pull-down unit; 106-level transmission output unit; T1-first thin film transistor; T2-second thin film transistor; T3-third thin film transistor; T4-fourth thin film transistor; T5-fifth thin film transistor; T6-sixth thin film transistor; T7-seventh thin film transistor; T8-eighth thin film transistor; T9-ninth thin film transistor; T10-tenth thin film transistor; T11-eleventh thin film transistor; T12-twelfth thin film transistor; T13-thirteenth thin film transistor; T14-fourteenth thin film transistor; T15-fifteenth thin film transistor; T16-sixteenth thin film transistor; T17-seventeenth thin film transistor; C1-first capacitor; C2-second capacitor; VGH-high level; VGL-low level; Gout (2n-3) - the gate scanning signal of the previous level; Cout (2n-4) - the level transmission signal of the previous level; Cout (2n+2) - the level transmission signal of the next level; Cout (2n) - the level transmission signal of this level; Gout (2n-1) - the first scanning signal; Gout (2n) - the second scanning signal; CLK1 - the first clock signal; CLK2 - the second clock signal; CLK4 - the fourth clock signal; Q[n] - first sampling node; QB[n] - second sampling node; QA[n] - third sampling node. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0023] In order to solve the technical problem in the prior art of how to ensure the stable operation of the system without increasing the circuit area, the present application provides a scan drive circuit, a display device and a scan drive circuit control method, which can enable the output scan signal to work independently during the output period, improve the operating stability of the scan drive circuit, and reduce the circuit area.

[0024] Example 1 The first embodiment of the present application provides a scan driving circuit, the scan driving circuit includes a plurality of cascaded gate scan driving circuits, such as Figure 1 The gate scanning driving circuit includes: a control unit 101, an independent driving unit 102, a first output unit 103, a second output unit 104 and a pull-down unit 105.

[0025] The connection relationship is as follows: the control unit 101 is connected to the first output unit 103, the independent driving unit 102 and the pull-down unit 105; the independent driving unit 102 is connected to the first output unit 103 and the second output unit 104; the pull-down unit 105 is connected to the first output unit 103 and the second output unit 104.

[0026] Under the control of the control unit 101 , the independent driving unit 102 controls the first output unit 103 and the second output unit 104 to output two overlapping scanning signals.

[0027] The independent driving unit of the scan driving circuit can control the first output unit and the second output unit to output two overlapping scan signals under the action of the control unit, so that the output scan signals can work independently during the output period, thereby improving the operating stability of the scan driving circuit. In addition, since the first output unit and the second output unit share a control unit, the circuit area can be reduced.

[0028] In one embodiment, the independent driving unit 102 includes a clock signal unit and a driving switch. Figure 2 The driving switch may be the seventeenth thin film transistor T17, and the clock signal unit may output a clock signal.

[0029] Under the action of the driving switch, the first output unit outputs a first scanning signal based on the first clock signal of the clock signal unit; under the action of the driving switch, the second output unit outputs a second scanning signal based on the second clock signal of the clock signal unit; wherein the first scanning signal and the second scanning signal at least partially overlap, for example, can overlap by 50%, to ensure the stability of system operation during the overlapping output period.

[0030] In a specific embodiment, the structural diagram of the scan driving circuit is as follows: Figure 2 The control unit includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, and a tenth thin film transistor T10.

[0031] The connection relationship is as follows: A first end of the first thin film transistor T1 is connected to the previous stage gate scanning signal Gout (2n-3), a second end of the first thin film transistor T1 is connected to a first end of the second thin film transistor T2, a first end of the fourth thin film transistor T4, a gate of the sixth thin film transistor T6, a gate of the seventh thin film transistor T7, a gate of the eighth thin film transistor T8 and a first sampling node Q[n] of the first output unit; a second end of the second thin film transistor T2 is connected to a first end of the third thin film transistor T3, a second end of the fourth thin film transistor T4, a first end of the fifth thin film transistor T5 and a second end of the sixth thin film transistor T6; The gate of the fourth thin film transistor T4 is connected to the gate of the fifth thin film transistor T5, the first end of the seventh thin film transistor T7, the second end of the tenth thin film transistor T10 and the second sampling node QB[n], and the second sampling node QB[n] is connected to the gate of the ninth thin film transistor T9 and the pull-down unit 105; The second end of the seventh thin film transistor T7 is connected to the first end of the eighth thin film transistor T8 and the first end of the ninth thin film transistor T9; The first end of the sixth thin film transistor T6, the first end of the tenth thin film transistor T10 and the second end of the ninth thin film transistor T9 are connected to the high level VGH; the second end of the third thin film transistor T3, the second end of the fifth thin film transistor T5 and the second end of the eighth thin film transistor T8 are connected to the low level VGL; The gate of the first thin film transistor T1 is connected to the level transmission signal Cout (2n-4) of the previous stage; the gate of the second thin film transistor T2 is connected to the gate of the third thin film transistor T3 and the level transmission signal Cout (2n+2) of the next stage; A gate of the tenth thin film transistor T10 is connected to the control terminal of the driving switch and the fourth clock signal CLK4 .

[0032] The first output unit includes an eleventh thin film transistor T11 and a first capacitor C1.

[0033] The connection relationship is as follows: A first end of the eleventh thin film transistor T11 is connected to the first clock signal CLK1, a gate of the eleventh thin film transistor T11, a first end of the first capacitor C1 and a first end of the driving switch are commonly connected to the first sampling node Q[n], and a second end of the eleventh thin film transistor T11 is connected to the second end of the first capacitor C1; the second end of the eleventh thin film transistor T11 is used to output a first scanning signal Gout(2n-1).

[0034] The second output unit includes a thirteenth thin film transistor T13 and a second capacitor C2.

[0035] The connection relationship is as follows: A first end of the thirteenth thin film transistor T13 is connected to the second clock signal CLK2, a gate of the thirteenth thin film transistor T13, a first end of the second capacitor C2 and a second end of the driving switch are commonly connected to the third sampling node QA[n] of the second output unit, and a second end of the thirteenth thin film transistor T13 is connected to the second end of the second capacitor C2; the second end of the thirteenth thin film transistor T13 is used to output the second scanning signal Gout(2n).

[0036] The pull-down unit includes a twelfth thin film transistor T12 and a fourteenth thin film transistor T14.

[0037] The connection relationship is as follows: A first end of the twelfth thin film transistor T12 is connected to the second end of the eleventh thin film transistor T11, a gate of the twelfth thin film transistor T12 and a gate of the fourteenth thin film transistor T14 are commonly connected to the second sampling node QB[n], and a second end of the twelfth thin film transistor T12 and a second end of the fourteenth thin film transistor T14 are commonly connected to the low level VGL; A first end of the fourteenth thin film transistor T14 is connected to a second end of the thirteenth thin film transistor T13 .

[0038] The gate scanning driving circuit further includes a level transmission output unit 106 , and the level transmission output unit 106 includes a fifteenth thin film transistor T15 and a sixteenth thin film transistor T16 .

[0039] The connection relationship is as follows: A first end of the fifteenth thin film transistor T15 is connected to the first end of the thirteenth thin film transistor T13, a gate of the fifteenth thin film transistor T15 is connected to the gate of the thirteenth thin film transistor T13, a second end of the fifteenth thin film transistor T15 is connected to the first end of the sixteenth thin film transistor T16, a gate of the sixteenth thin film transistor T16 is connected to the gate of the fourteenth thin film transistor T14, and a second end of the sixteenth thin film transistor T16 is connected to the low level VGL; the second end of the fifteenth thin film transistor T15 and the first end of the sixteenth thin film transistor T16 jointly output the stage transfer signal Cout (2n) of this stage.

[0040] Specifically, the driving switch includes a seventeenth thin film transistor T17. A first end of the seventeenth thin film transistor T17 is connected to the gate of the eleventh thin film transistor T11, a second end of the seventeenth thin film transistor T17 is connected to the third sampling node QA[n], and a gate of the seventeenth thin film transistor T17 is connected to the gate of the tenth thin film transistor T10.

[0041] In this embodiment, the scanning drive circuit is composed of 17 thin film transistors TFT (T1-T17) and two capacitors (C1, C2). It works in eight cycles from t1 to t8. The timing diagram of the signal is as follows: Figure 3 The circuit uses six (three in a single phase) clock signals and two DC signals VGL and VGH. Next, the operation of the eight-cycle scan drive circuit is described in detail.

[0042] t1: Reset phase The schematic diagram of the reset phase is as follows Figure 4 As shown, when Cout(2n-4) and CLKL4 signals become high level voltages, the low level voltage of Gout(2n-3) is applied to Q(n) and QA(n) through T1 and T17. Therefore, nodes Q(n) and QA(n) are reset to VGL. At the same time, as CLK4 turns on T10, the voltage of QB(n) is reset to VGH.

[0043] t2: Pre-charge phase The schematic diagram of the pre-charge stage is as follows Figure 5As shown, during the pre-charge period, T1 is turned on by the Cout(2n-4) signal, and when the Gout(2n-3) signal becomes the high level voltage of VGH, the voltage of Q(n) is charged to the high level voltage. CLK4 turns on T17, so the node QA(n) is also charged to the high level voltage of Q(n). Since T7, T8 and T10 are turned on at the same time, QB(n) is connected to VGL, and the voltage of QB(n) will be discharged to VGL. VGH applies a high level voltage to the source node of T4 through T6, and the gate-source voltage (VGS) of T4 is lower than VTH, and T4 is turned off. Therefore, the nodes Q(n) and QA(n) can maintain a high level voltage. The voltages of Gout(2n-1), Gout(2n) and Cout(2n) are determined by the CLK signal and are all VGL.

[0044] t3: Pre-charge voltage holding stage The schematic diagram of the pre-charge voltage holding stage is as follows Figure 6 As shown, when the Cout(2n-4) signal becomes a low-level voltage, T1 is turned off and nodes Q(n) and QA(n) are in a floating state. Since T2 and T4 are completely turned off by applying VGH to the source node through T6, the voltage drop of Q(n) due to leakage current is prevented. Therefore, Q(n) and QA(n) maintain the voltage level during precharging through C1 and C2. When CLK4 becomes a low-level voltage, T10 is turned off and QB(n) is discharged to VGL through T7 and T8.

[0045] t4: Q(n) bootstrap phase During this period, because T1, T2, T4 and T17 are all turned off, node Q(n) is in a floating state. When the CLK1 signal becomes a high-level voltage, Q(n) is bootstrapped through capacitor C1. Subsequently, the low-level voltage of QB(n) turns off T12, and T11 outputs the Gout(2n-1) signal. Due to the use of a closed T17 independent drive structure, the voltage of QA(n) is maintained at the bootstrap voltage at this stage.

[0046] t5: QA(n) bootstrap phase When the CLK2 signal becomes a high level voltage, QA(n) is bootstrapped through capacitor C2, which is similar to the situation of Q(n) in the previous cycle. T13 and T15 output Gout(2n) and Cout(2n) respectively. At this time, the voltage of Q(n) is not affected by the bootstrap of QA(n) because T17 is still closed and the independent drive structure disconnects nodes Q(n) and QA(n). At this stage, Gout(2n) and Gout(2n-1) output independent scan signals respectively.

[0047] t6: Gout(2n-1) discharge stage When the CLK1 signal becomes a low voltage, the voltage of Q(n) drops to close to VGH due to the coupling effect of C1. Since the voltage of CLK4 is still VGL, T17 is turned off, so nodes Q(n) and QA(n) are controlled separately. Therefore, QA(n) and Gout(2n) are not affected by the voltage change of Q(n), and maintain the bootstrap voltage and VGH respectively.

[0048] t7: Gout(2n) discharge holding stage When Cout (2n+2) and CLK4 signal become high level voltage of VGH, T2, T3, T10 and T17 are turned on. Nodes Q(n) and QA(n) are discharged to VGL through T2 and T3. T2, T3 and Cout (2n+2) work together to significantly reduce the gate-source voltage (VGS) of T7 and T8, so that QB(n) is charged to VGH through T10. Therefore, T4 and T5 are also turned on and discharge Q(n) and QA(n) at the same time. At the same time, the high voltage of QB(n) turns on T12, T14 and T16, discharging the output signal node to the low level voltage VGL.

[0049] t8: Holding phase During this period, node QB(n) is in a floating state because CLK4 is a low-level voltage, turning off T10. The leakage path T7 of QB(n) is completely turned off by applying VGH to the source node of T7, and QB(n) can maintain VGH. Therefore, the voltages of Q(n) and QA(n) are maintained at VGL through the discharge of T4 and T5. At the same time, since the high voltage of QB(n) turns on T12, T14, and T16, the output signal can also be maintained at a low voltage.

[0050] In the above 8 stages, if T17 is not used, during the bootstrap period, nodes Q(n) and QA(n) are connected to and affected by CLK1 and CLK2 respectively through the capacitive coupling of C1 and C2. As CLK1 becomes a high-level voltage, the voltage of Q(n) increases. Subsequently, when CLK2 becomes VGH, the voltage of Q(n) increases again. Therefore, the voltage of Q(n) does not directly reach the bootstrap voltage level. In addition, when T17 is not used, the degree of charging of node Q(n) through CLK1 or CLK2 is low because these signals charge C1 and C2 at the same time. After Gout(2n) is output, when CLK1 becomes a low-level voltage, due to the capacitive coupling of C1, node Q(n) cannot be maintained at the bootstrap voltage level, and it is also impossible to stably output two stable scan signals with an overlap rate of 50% in the t5 stage.

[0051] In this embodiment, due to the use of the T17 independent driving structure, the nodes Q(n) and QA(n) can maintain the bootstrap voltage during the output of Gout(2n-1) and Gout(2n). When the bootstrap voltage level of Q(n) or QA(n) is higher than VGH, T17 is turned off, so that the nodes Q(n) and QA(n) can have a sufficiently high voltage during the bootstrap period of each output signal. During the capacitor pre-charging and bootstrap period, the voltage of QB(n) is VGL, so that the pull-down TFT (T12, T14 and T16) is in a closed state. Therefore, by using an independent driving structure, the proposed scan drive circuit generates two output signals with an overlap rate of 50% and stability. In addition, the scan drive circuit can also reduce the circuit area because the two output signals Gout(2n-1) and Gout(2n) of adjacent gate lines share a control unit, and the shift register operation can be successfully demonstrated through the above 8 stages. Therefore, using the independent driving structure, the scan drive circuit can show stable operation under multiple overlapping output signals.

[0052] It should be understood that the scan driving circuit proposed in the embodiment of the present application can also appropriately adjust the signal timing and circuit scheme according to the output signal to generate multiple output signals with different timings, without limitation.

[0053] Example 2 Based on the same technical concept, the second embodiment of the present application provides a display device, including: a display panel and a driving circuit; The display panel includes a pixel unit array; a driving circuit, used for driving the pixel units, including any one of the scanning driving circuits in the first embodiment.

[0054] The driving circuit of the display device can output two independent and overlapping scanning signals, so that the output scanning signals can work independently during the output period, thereby improving the operating stability of the system. In addition, since the first output unit and the second output unit share a control unit, the circuit area of ​​the display device can be reduced.

[0055] Example 3 A scanning drive circuit control method is applied to the scanning drive circuit of any one of the first embodiments, and the scanning drive circuit control method includes: The first output unit and the second output unit are controlled by an independent driving unit to output two overlapping scanning signals.

[0056] The method can control the first output unit and the second output unit to output two overlapping scanning signals through an independent driving unit, thereby improving the operating stability of the system.

[0057] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0058] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0059] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0060] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. In the description, the suffixes such as "module", "component" or "unit" used to represent the elements are only used to facilitate the description of the present application and have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0061] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A scanning driving circuit, comprising a plurality of cascaded gate scanning driving circuits, characterized in that: The gate scanning driving circuit comprises: a control unit, an independent driving unit, a first output unit, a second output unit and a pull-down unit; The control unit is connected to the first output unit, the independent driving unit and the pull-down unit; the independent driving unit is connected to the first output unit and the second output unit; the pull-down unit is connected to the first output unit and the second output unit; Under the action of the control unit, the independent driving unit controls the first output unit and the second output unit to output two overlapping scanning signals.

2. The scanning driving circuit according to claim 1, characterized in that: The independent driving unit includes a clock signal unit and a driving switch; The first output unit outputs a first scanning signal based on the first clock signal of the clock signal unit under the action of the driving switch; The second output unit outputs a second scanning signal based on the second clock signal of the clock signal unit under the action of the driving switch; The first scanning signal and the second scanning signal at least partially overlap.

3. The scanning driving circuit according to claim 2, characterized in that: The control unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a tenth thin film transistor; A first end of the first thin film transistor is connected to a previous stage gate scanning signal, a second end of the first thin film transistor is connected to a first end of the second thin film transistor, a first end of the fourth thin film transistor, a gate of the sixth thin film transistor, a gate of the seventh thin film transistor, a gate of the eighth thin film transistor and a first sampling node of the first output unit; a second end of the second thin film transistor is connected to a first end of the third thin film transistor, a second end of the fourth thin film transistor, a first end of the fifth thin film transistor and a second end of the sixth thin film transistor; The gate of the fourth thin film transistor is connected to the gate of the fifth thin film transistor, the first end of the seventh thin film transistor, the second end of the tenth thin film transistor and the second sampling node, and the second sampling node is connected to the gate of the ninth thin film transistor and the pull-down unit; The second end of the seventh thin film transistor is connected to the first end of the eighth thin film transistor and the first end of the ninth thin film transistor; The first end of the sixth thin film transistor, the first end of the tenth thin film transistor and the second end of the ninth thin film transistor are connected to a high level; the second end of the third thin film transistor, the second end of the fifth thin film transistor and the second end of the eighth thin film transistor are connected to a low level; The gate of the first thin film transistor is connected to the stage transmission signal of the previous stage; The gate of the second thin film transistor is connected to the gate of the third thin film transistor and a stage transmission signal of the next stage; The gate of the tenth thin film transistor is connected to the control terminal of the driving switch and a fourth clock signal.

4. The scanning driving circuit according to claim 3, characterized in that: The first output unit includes an eleventh thin film transistor and a first capacitor; The first end of the eleventh thin film transistor is connected to the first clock signal, the gate of the eleventh thin film transistor, the first end of the first capacitor and the first end of the driving switch are commonly connected to the first sampling node, and the second end of the eleventh thin film transistor is connected to the second end of the first capacitor; the second end of the eleventh thin film transistor is used to output a first scanning signal.

5. The scanning driving circuit according to claim 4, characterized in that: The second output unit includes a thirteenth thin film transistor and a second capacitor; The first end of the thirteenth thin film transistor is connected to the second clock signal, the gate of the thirteenth thin film transistor, the first end of the second capacitor and the second end of the driving switch are commonly connected to the third sampling node of the second output unit, and the second end of the thirteenth thin film transistor is connected to the second end of the second capacitor; the second end of the thirteenth thin film transistor is used to output the second scanning signal.

6. The scanning driving circuit according to claim 5, characterized in that: The pull-down unit includes a twelfth thin film transistor and a fourteenth thin film transistor; The first end of the twelfth thin film transistor is connected to the second end of the eleventh thin film transistor, the gate of the twelfth thin film transistor and the gate of the fourteenth thin film transistor are commonly connected to the second sampling node, and the second end of the twelfth thin film transistor and the second end of the fourteenth thin film transistor are commonly connected to a low level; The first end of the fourteenth thin film transistor is connected to the second end of the thirteenth thin film transistor.

7. The scanning driving circuit according to claim 6, characterized in that: The gate scanning driving circuit further includes a level transmission output unit, and the level transmission output unit includes a fifteenth thin film transistor and a sixteenth thin film transistor; A first end of the fifteenth thin film transistor is connected to a first end of the thirteenth thin film transistor, a gate of the fifteenth thin film transistor is connected to a gate of the thirteenth thin film transistor, a second end of the fifteenth thin film transistor is connected to a first end of the sixteenth thin film transistor, a gate of the sixteenth thin film transistor is connected to a gate of the fourteenth thin film transistor, and a second end of the sixteenth thin film transistor is connected to a low level; The second end of the fifteenth thin film transistor and the first end of the sixteenth thin film transistor jointly output the stage transmission signal of the current stage.

8. The scanning driving circuit according to claim 7, characterized in that: The driving switch includes a seventeenth thin film transistor; A first end of the seventeenth thin film transistor is connected to the gate of the eleventh thin film transistor, a second end of the seventeenth thin film transistor is connected to the third sampling node, and a gate of the seventeenth thin film transistor is connected to the gate of the tenth thin film transistor.

9. A display device, characterized in that: include: Display panel and driving circuit; The display panel includes a pixel unit array; The driving circuit is used to drive a pixel unit, and comprises the scanning driving circuit according to any one of claims 1 to 8.

10. A scanning drive circuit control method, characterized in that: The scanning driving circuit control method is applied to the scanning driving circuit according to any one of claims 1 to 8, and the scanning driving circuit control method comprises: The first output unit and the second output unit are controlled by an independent driving unit to output two overlapping scanning signals.

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