Flash memory testing method, device, storage medium and computer equipment

Abstract

This application discloses a flash memory testing method, apparatus, storage medium, and computer device. The method includes: acquiring error bit count and read voltage offset data corresponding to each of multiple flash memory chips through a storage controller; acquiring normalized values ​​of the error bit count and offset data for each flash memory chip through a processor; acquiring weight values ​​for the error bit count and offset data; obtaining an evaluation value for each flash memory chip based on the normalized values ​​of the error bit count, offset data, and weight values; and obtaining test results for multiple flash memory chips based on the evaluation values ​​of each flash memory chip. The solution provided by this application can perform normalized weighted averaging of the error bit count and read voltage offset data of flash memory chips to calculate the corresponding evaluation value, and classify them based on the score, thus improving the accuracy of flash memory chip classification.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a flash memory testing method, device, storage medium and computer equipment. Background Art

[0002] In the manufacturing process of storage technology, a wafer can produce multiple flash memory particles (storage chips). Due to the limitations of the manufacturing process and technology, the quality of these flash memory particles will vary from die to die, and there may be large differences in storage performance.

[0003] At present, there are different levels of storage requirements, including enterprise-level, industrial-level, automotive-level and consumer-level storage. Different levels have different requirements for the quality of flash memory particles. If flash memory particles with poor particle quality are selected at the enterprise-level storage level, it will cause serious safety hazards. If flash memory particles with very good particle quality are selected at the consumer-level storage level, it will cause a certain waste of storage performance. Therefore, the current classification of flash memory particles is relatively rough and inaccurate, and the accuracy of particle level classification is low. Summary of the invention

[0004] The embodiments of the present application provide a flash memory testing method, apparatus, storage medium and computer equipment, which can perform normalized weighted averaging on the error bit number of flash memory particles and the offset data of the read voltage, thereby calculating the corresponding score, and classifying based on the score, thereby improving the accuracy of flash memory particle classification.

[0005] The embodiment of the present application provides a flash memory testing method, which is applied to a flash memory testing device, wherein the flash memory testing device includes a processor and a storage controller, including:

[0006] Acquiring the error bit number and read voltage offset data corresponding to each of the plurality of flash memory particles through the storage controller;

[0007] Acquiring, by the processor, a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles;

[0008] Obtaining weight values ​​of the number of error bits and the offset data, and obtaining an evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data, and the weight value;

[0009] The test results of the plurality of flash memory particles are obtained according to the evaluation value of each of the flash memory particles.

[0010] In one embodiment, obtaining a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles includes:

[0011] Obtaining a maximum value of the number of error bits, a minimum value of the number of error bits, and a maximum value and a minimum value of the offset data in a plurality of flash memory particles;

[0012] Calculate the normalized value of the number of error bits according to the number of error bits, the maximum number of error bits and the minimum number of error bits of each flash memory particle;

[0013] The normalized value of the offset data is calculated according to the offset data of each flash memory particle, the maximum value of the offset data and the minimum value of the offset data.

[0014] In one embodiment, obtaining the weight values ​​of the number of error bits and the offset data, and obtaining the evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data, and the weight value, includes:

[0015] According to the application type of the flash memory particles, weight values ​​are respectively assigned to the number of error bits and the offset data;

[0016] Calculating a first product of a normalized value of the number of error bits in each of the flash memory particles and a corresponding weight value;

[0017] Calculating a second product of a normalized value of the offset data in each of the flash memory particles and a corresponding weight value;

[0018] The sum of the first product and the second product is used as an evaluation value of the flash memory particle.

[0019] In one embodiment, obtaining the test results of the plurality of flash memory particles according to the evaluation value of each of the flash memory particles includes:

[0020] Randomly select a preset number of evaluation values ​​from the evaluation values ​​of all flash memory particles as the initial centroid;

[0021] Calculate the distance from each evaluation value to all initial centroids, and assign all evaluation values ​​to the initial centroids with the closest distance to obtain a preset number of clusters;

[0022] Calculate the mean of all evaluation values ​​in each cluster, and use the mean as the second centroid to iterate the centroid;

[0023] When the iteration is completed, the final cluster is used as the preset number of classifications.

[0024] In one embodiment, the iterative process includes:

[0025] Calculate the distance from each evaluation value to all second centroids, and assign all evaluation values ​​to the second centroids with the closest distances to obtain a preset number of clusters;

[0026] Calculate the mean of all evaluation values ​​in each cluster and use the mean as the third centroid;

[0027] The center of mass is calculated repeatedly until the center of mass no longer changes, and the iteration is confirmed to be completed.

[0028] In one embodiment, the final cluster is used as the preset number of categories, including:

[0029] The flash memory particles in the cluster corresponding to the centroid with the smallest value are determined as first-class particles;

[0030] The flash memory particles in the cluster corresponding to the centroid with the second smallest value are determined as second-class particles;

[0031] The flash memory particles in the cluster corresponding to the centroid with the largest value are determined as third-class particles.

[0032] In one embodiment, the method further comprises:

[0033] Calculate the variance of the flash memory particle evaluation value in each category, and the mean difference of the flash memory particle scores between different categories;

[0034] The number of the categories is adjusted according to the variance and mean difference.

[0035] The embodiment of the present application further provides a flash memory testing device, the flash memory testing device comprising a processor and a storage controller, including:

[0036] An acquisition unit, used for acquiring the error bit number and read voltage offset data corresponding to each of a plurality of flash memory particles through the storage controller;

[0037] A first calculation unit, configured to obtain, through the processor, a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles;

[0038] A second calculation unit, used to obtain the weight value of the number of error bits and the offset data, and obtain the evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data and the weight value;

[0039] The dividing unit is used to obtain the test results of the plurality of flash memory particles according to the evaluation value of each of the flash memory particles.

[0040] The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed on a computer, the computer executes the flash memory testing method as described above.

[0041] An embodiment of the present application further provides a computer device, including a memory and a processor, wherein the processor executes the flash memory testing method as described above by calling a computer program stored in the memory.

[0042] The flash memory testing method, device, storage medium and computer equipment provided in the embodiment of the present application can obtain the error bit number and the offset data of the read voltage corresponding to each of the multiple flash memory particles through the storage controller, and then the processor obtains the normalized value of the error bit number and the normalized value of the offset data of each flash memory particle, obtains the weight value of the error bit number and the offset data, obtains the evaluation value of each flash memory particle according to the normalized value of the error bit number, the normalized value of the offset data and the weight value, and obtains the test results of multiple flash memory particles according to the evaluation value of each flash memory particle. The scheme provided in the embodiment of the present application can perform normalized weighted average on the error bit number and the offset data of the read voltage of the flash memory particles, thereby calculating the corresponding evaluation value, and classifying based on the score, thereby improving the accuracy of flash memory particle classification. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A flowchart of a flash memory testing method provided in an embodiment of the present application.

[0045] Figure 2 Another flowchart of the flash memory testing method provided in an embodiment of the present application.

[0046] Figure 3 A schematic diagram of the structure of a flash memory testing device provided in an embodiment of the present application.

[0047] Figure 4 Another structural schematic diagram of the flash memory testing device provided in an embodiment of the present application.

[0048] Figure 5 A schematic diagram of the computer device structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0050] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0051] The embodiments of the present application provide a flash memory testing method, device, storage medium and computer equipment. Specifically, the flash memory testing method of the embodiments of the present application can be executed by a computer device or a server, wherein the computer device can be a terminal. The terminal can be a smart phone, a tablet computer, a laptop computer, a touch screen, a game console, a personal computer (PC, Personal Computer), a personal digital assistant (Personal Digital Assistant, PDA), a smart home and other devices, and the terminal can also include a client, which can be a media playback client or an instant messaging client, etc.

[0052] See also Figure 1 , the specific process of the flash memory testing method can be as follows:

[0053] Step 101: obtaining error bit numbers and read voltage offset data corresponding to a plurality of flash memory particles respectively through a storage controller.

[0054] In one embodiment, flash memory is a non-volatile storage technology that can retain data when power is off. The flash memory particles (or flash memory chips, flash memory units) in this application are the most basic components of flash memory devices, including but not limited to NAND flash memory and NOR flash memory.

[0055] Specifically, when collecting the number of error bits of flash memory particles, you can first write a specific test program or use existing test tools to read and write flash memory particles, and record the error correction code (ECC) type and its related parameters used in the data transmission process, where these parameters may include the number of bits of the error correction code, coding efficiency, etc., and then use a log file or database to record the number of error bits for each flash memory particle. For example, if ECC detects that there are 10 error bits in 1KB of data, then the ECC value (number of error bits) is 10. This value can be used to evaluate the data integrity and reliability of the storage medium. A lower number of error bits indicates that the quality of the storage medium is good or the storage environment is relatively stable.

[0056] Furthermore, since the electrical characteristics of the flash memory particles will change with the increase of the usage time, it is necessary to regularly measure the offset data of the read voltage. In one embodiment, the voltage value of the storage unit in different states can be read and compared with the preset reference voltage to obtain the offset data. For example, all storage blocks in the NAND flash memory can be traversed to obtain the usage of each storage block. For the storage block in use, the word line (Word Line) information currently in use can be further obtained. Then, based on the pre-created correspondence between the storage page and the region, the target storage page is matched for the currently used word line, and then the reference voltage candidate table (including multiple candidate reference voltages) in the test equipment is used to perform a read operation on the target storage page. Each read operation uses a different reference voltage and records the corresponding error bit rate. Finally, the error bit rates corresponding to all read operations are counted, and the reference voltage corresponding to the minimum error bit rate is found, and the reference voltage corresponding to the minimum error bit rate is determined as the offset voltage amount in the current use stage.

[0057] In one embodiment, the above-mentioned multiple flash memory particles can also be preliminarily screened, such as only selecting memory particles whose ECC is in the range of 0-80bit, and only selecting memory particles whose offset data is in the range of 0-0.2V. This is because the Page quality classification standard in the flash memory particles is that 20bit or less is the best, which is suitable for PCIE terminal storage products, 21-60bit is suitable for SATA terminal storage products, and 61-80bit is suitable for USB terminal storage products. Correspondingly, the offset data ΔV is between 0-0.06V for the best, 0.06-0.12 is the second best, and 0.12-0.2 is the worst, so it can be used as PCIE terminal storage products, SATA terminal storage products, and USB terminal storage products in turn. In the prior art, the quality of flash memory particles can often only be evaluated by one indicator, while the present application can further combine the above two indicators to calculate a comprehensive score, so as to perform subsequent quality classification of flash memory particles.

[0058] Step 102: Obtain, by a processor, a normalized value of the number of error bits and a normalized value of offset data of each flash memory particle.

[0059] In one embodiment, the processor may normalize the number of error bits and offset data of each flash memory particle respectively, specifically through linear normalization, such as calculating the normalized value of the number of error bits and the normalized value of the offset data of each flash memory particle based on the maximum and minimum values ​​of all the number of error bits and offset data, and converting these values ​​to a common interval, usually [0, 1].

[0060] In other embodiments, it can also be normalized by standard deviation, which is achieved by subtracting the mean from the original data and dividing it by its standard deviation. This method converts the data into a form with 0 as the mean and 1 as the standard deviation, which is suitable for situations where the data distribution is close to a normal distribution. It can also be normalized by decimal calibration. First, find the maximum value in the data, and then determine how many decimal places need to be moved to make the value become 1 (or a number close to but less than 1). Then, apply the same decimal point movement to all data to complete the normalization, which is not further limited in this embodiment.

[0061] Step 103: Obtain the weight values ​​of the number of error bits and the offset data, and obtain the evaluation value of each flash memory particle according to the normalized value of the number of error bits, the normalized value of the offset data, and the weight value.

[0062] In one embodiment, the weight values ​​of the number of error bits and offset data can be assigned according to the application of the flash memory particle, wherein the number of error bits is crucial to ensuring data integrity and reliability, while the offset data may directly affect the read and write stability and life of the flash memory particle. Therefore, for long-term data storage applications, data integrity and persistence are more important, so the weight of the number of error bits will be higher, and in applications that require fast read and write operations (such as the cache layer of SSD), the offset data is not the primary consideration, and the weight of the number of error bits can be set higher to balance performance and reliability. In resource-constrained embedded systems, the offset data will directly affect power consumption and stability, so its weight can be set higher. For example, if data reliability is the primary consideration, the weight of the number of error bits can be set to 0.7, and the weight of the offset data can be set to 0.3.

[0063] In practical applications, the weight value can be assigned in one of the following ways: 1. Analytic Hierarchy Process (AHP), which uses the analytic hierarchy process to decompose complex decision factors into different components, and determines the relative importance of each factor by comparing them two by two, thereby calculating the weight value. 2. Data-driven method, based on a large amount of test data and statistical analysis results, the weight value of the number of error bits and offset data is automatically calculated through machine learning or statistical methods.

[0064] After allocating weight values ​​for the number of error bits and the offset data, the comprehensive evaluation value of each flash memory particle can be further calculated according to the normalized value of the number of error bits, the normalized value of the offset data, and the corresponding weight values.

[0065] Step 104 , obtaining test results of multiple flash memory particles according to the evaluation value of each flash memory particle.

[0066] In one embodiment, after obtaining the score of each flash memory particle, a clustering algorithm can be used to divide the multiple flash memory particles into a preset number of categories, wherein the clustering algorithm includes K-means clustering, hierarchical clustering (such as AGNES or DIANA), DBSCAN, etc. Taking the K-means clustering algorithm as an example for explanation, it is first necessary to determine how many categories the flash memory particles are to be divided into according to the application scenario or business requirements, such as K categories, and then randomly select the scores of K flash memory particles as initial cluster centers, assign each flash memory particle to the nearest cluster center to form K clusters, and then recalculate the center of each cluster, that is, the mean of the scores of all flash memory particles in the cluster, and repeat the above calculation of cluster centers and iteration steps until the cluster centers no longer change significantly or the preset number of iterations is reached. At this time, the quality of the clustering results can be evaluated. Specifically, indicators such as the silhouette coefficient can be used to measure the compactness and separation of the clusters to check whether any clusters appear abnormal. If there is no abnormality, the flash memory particles can be divided into K groups according to the final clustering results.

[0067] In one embodiment, after obtaining the evaluation value of each flash memory particle, in order to further analyze and optimize the classification of flash memory particles, the variance of the evaluation value of the flash memory particles within each classification and the mean difference of the evaluation values ​​of the flash memory particles between different classifications can also be calculated. These statistics are used to evaluate the rationality of the classification, and the number of classifications is adjusted according to the above variance and mean difference. Specifically, for each classification, the evaluation values ​​of all flash memory particles within it can be collected, the average value of these evaluation values, that is, the mean of the classification, is calculated, the square of the difference between each evaluation value and the mean is calculated, and then the average value of these square differences is calculated to obtain the variance. Among them, if the variance of a certain classification is very large, it means that the performance of the flash memory particles within the classification is very different. If the variance of all classifications is relatively small, it means that the classification is relatively reasonable. Further, when calculating the mean difference of the flash memory particle scores between different classifications, the average value of the flash memory particle evaluation value within each classification can be calculated, and then the absolute value of the difference between the means of any two classifications can be calculated to obtain the mean difference. Among them, if the mean difference between different categories is small, it means that there is no obvious difference in performance between these categories. If the mean difference is large, it means that there is an obvious performance difference between the categories and the classification is more reasonable.

[0068] Based on the above variance and mean difference, when adjusting the number of categories, if the mean difference between some categories is small and the variance within these categories is also small, these categories can be merged into a larger category. If the variance within a category is very large, it means that the performance of flash memory particles within the category varies greatly. In this case, the category can be further subdivided according to other standards (such as performance parameters, application scenarios, etc.).

[0069] As can be seen from the above, the flash memory test method provided in the embodiment of the present application can obtain the error bit number and the offset data of the read voltage corresponding to each of the multiple flash memory particles through the storage controller, and then the processor obtains the normalized value of the error bit number and the normalized value of the offset data of each flash memory particle, obtains the weight value of the error bit number and the offset data, obtains the evaluation value of each flash memory particle according to the normalized value of the error bit number, the normalized value of the offset data and the weight value, and obtains the test results of multiple flash memory particles according to the evaluation value of each flash memory particle. The scheme provided in the embodiment of the present application can perform normalized weighted average on the error bit number and the offset data of the read voltage of the flash memory particles, thereby calculating the corresponding evaluation value, and classifying based on the score, thereby improving the accuracy of flash memory particle classification.

[0070] See also Figure 2 , is another flow chart of the flash memory testing method provided by the embodiment of the present application. The specific flow of the method can be as follows:

[0071] Step 201: Obtain the error bit number and read voltage offset data corresponding to each of a plurality of flash memory particles.

[0072] In one embodiment, the plurality of flash memory particles may be preliminarily screened, such as selecting only memory particles whose ECC is in the range of 0-80 bits, and selecting only memory particles whose read voltage offset data is in the range of 0-0.2V. For example, if the plurality of flash memory particles is 9 in number, the corresponding error bit number (ECC) and offset data (ΔV) are as follows:

[0073]

[0074] For the dies with serial numbers D0-D9, the ECC values ​​are: D0: 12, D1: 34, D2: 56, D3:23, D4: 67, D5: 8, D6: 45, D7: 19, D8: 73, D9: 31; the offset data ΔV are: D0: 0.00, D1: 0.02, D2: 0.04, D3: 0.06, D4: 0.08, D5: 0.10, D6: 0.12, D7: 0.14,D8: 0.16, D9: 0.18.

[0075] Step 202: Obtain the maximum value of the number of error bits, the minimum value of the number of error bits, and the maximum value and the minimum value of the offset data in a plurality of flash memory particles.

[0076] From the above data, we can see that the minimum value of the ECC value in the die of D0-D9 is 8 and the maximum value is 73. The minimum value of the offset data ΔV is 0.00 and the maximum value is 0.18.

[0077] Step 203: Calculate a normalized value of the number of error bits according to each number of error bits, the maximum number of error bits, and the minimum number of error bits.

[0078] Step 204 , calculating a normalized value of the offset data according to each offset data, the maximum value of the offset data, and the minimum value of the offset data.

[0079] In one embodiment, for the ECC value of each flash memory particle, the normalization formula is:

[0080]

[0081] Among them, ECC norn is the normalized value of the number of error bits of the flash memory particle, ECC is the number of error bits of the flash memory particle, and ECC min is the minimum number of error bits in multiple flash memory particles, ECC max It is the maximum number of error bits in multiple flash memory particles.

[0082] Furthermore, for the offset data ΔV of each flash memory particle, the normalization formula is:

[0083]

[0084] Where, ΔV norn is the normalized value of the offset data of the flash memory particle, ΔV is the offset data of the flash memory particle, and ΔV min is the minimum value of the offset data in multiple flash memory particles, ΔV max It is the maximum value of the offset data in multiple flash memory particles.

[0085] For example, for the die with serial number D0, its ECC is 12 and ΔV is 0.00. Substituting it into the above two formulas for normalization calculation, we can get ECC norn =0.0615, ΔV norn =0.

[0086] Step 205 , weight values ​​are respectively assigned to the number of error bits and the offset data according to the application type of the flash memory particles.

[0087] Step 206, calculate a first product of a normalized value of the number of error bits in each flash memory particle and a corresponding weight value, and a second product of a normalized value of the offset data and a corresponding weight value, and take the sum of the first product and the second product as the evaluation value of the flash memory particle.

[0088] In one embodiment, the weight values ​​of the error bit count and the offset data can be assigned according to the application of the flash memory particle. For example, the weight of the error bit count can be set to 0.5, and the weight of the offset data can be set to 0.5, indicating that the importance of the two indicators of error bit count and offset data is the same when calculating the score. At this time, 0.0615*0.5+0*0.5=0.03075 can be calculated, which is the score corresponding to the die with serial number D0. By analogy, all 9 dies in the above list are calculated, and the comprehensive score of each die is as follows:

[0089]

[0090] Step 207: randomly select a preset number of evaluation values ​​from the evaluation values ​​of all flash memory particles as initial centroids.

[0091] Step 208, calculate the distance from each evaluation value to all initial centroids, and assign all evaluation values ​​to the initial centroids with the closest distance to obtain a preset number of clusters, calculate the mean of all evaluation values ​​in each cluster, and use the mean as the second centroid to iterate the centroids.

[0092] From the above results, D5 (comprehensive score of 0) is the sample with the lowest comprehensive score, while D8 (comprehensive score of 0.88462) is the sample with the highest comprehensive score. Furthermore, based on the comprehensive scores in the table, they can be further classified, specifically into 3 categories. Each category corresponds to a different terminal product. In one embodiment, the K-means clustering algorithm can be used to process it. K-means is an unsupervised learning algorithm used to group data points into K clusters, where K is the number of pre-specified clusters. In this application, K=3.

[0093] Specifically, first randomly select K data points as the initial centroids. In the embodiment of the present application, K=3, so it is necessary to randomly select 3 data points as the initial centroids, and then assign each data point to the cluster where the nearest centroid is located. Specifically, the distance from each data point to all centroids can be calculated and assigned to the nearest centroid. For each cluster, the mean of all data points is calculated and used as the new centroid. If the centroid no longer changes or the maximum number of iterations is reached, the iteration is stopped.

[0094] Among them, the above-mentioned iterative process may include: calculating the distance from each evaluation value to all second centroids, and assigning all evaluation values ​​to the second centroids with the nearest distance to obtain a preset number of clusters, calculating the mean of all values ​​in each cluster, and using the mean as the third centroid, repeatedly calculating the centroid until the centroid no longer changes, and then confirming that the iteration is completed.

[0095] Step 209: When the iteration is completed, the final cluster is used as a preset number of classifications.

[0096] Further, the process of allocating data points and updating the centroid is repeated until the centroid is stable or the maximum number of iterations is reached, and when the iteration is completed, the final cluster is output as a preset number of classifications. Taking the preset number of 3 as an example, the flash memory particles in the cluster corresponding to the centroid with the smallest value can be determined as first-class particles, the flash memory particles in the cluster corresponding to the centroid with the second smallest value can be determined as second-class particles, and the flash memory particles in the cluster corresponding to the centroid with the largest value can be determined as third-class particles.

[0097] For example, three data points can be randomly selected from the score list corresponding to the above nine flash memory particles as the initial centroids. Specifically, D0, D5 and D8 can be selected as the initial centroids. That is, the initial centroid C0: D0 = 0.03076923076923077, the initial centroid C1: D5 = 0.00000000000000000, and C2: D8 = 0.8846153846153846. Calculate the distance from each score to these three centroids and assign them to the nearest centroid. The distance can be the absolute difference between the values. For each cluster, the mean of all scores can be calculated and used as the new centroid.

[0098] Specifically, in the first iteration, D0 can be assigned to C0, D1 to C0, D2 to C2, D3 to C0, D4 to C2, D5 to C1, D6 to C2, D7 to C0, D8 to C2, and D9 to C0. Then the centroid is updated, and it is calculated that C0=0.1892, C1=0, and C2=0.7289. The second iteration is performed with the updated centroid, specifically D0 is assigned to C0, D1 to C0, D2 to C2, D3 to C0, D4 to C2, D5 to C1, D6 to C2, D7 to C0, D8 to C2, and D9 to C0. The centroid is updated again, and it is calculated that C0=0.1892, C1=0, and C2=0.7289. It can be seen that after two iterations, the centroid has not changed, which means that a stable state has been reached and the iteration is ended. Therefore, the final cluster division is as follows: Cluster 1 (C0) includes D0, D1, D3, D7, D9; Cluster 2 (C1) includes D5; Cluster 3 (C2) includes D2, D4, D6, D8. Among them, Cluster 1 (C0) contains data points with relatively small values, which can be classified as SATA storage products. Cluster 2 (C1) contains the data point D5 with the smallest value, which can be classified as PCIE storage products. Cluster 3 (C2) contains data points with relatively large values, which can be classified as USB storage products.

[0099] This embodiment can use the two indicators of ECC value and offset data ΔV to evaluate the quality of the die, and classify the dies based on the comprehensive score, so as to facilitate the subsequent use of flash memory particles in the manufacture of storage products corresponding to the quality level according to the quality of the particles.

[0100] All of the above technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described in detail here.

[0101] As can be seen from the above, the flash memory testing method provided in the embodiment of the present application can obtain the error bit number and the offset data of the read voltage corresponding to each of the multiple flash memory particles, obtain the maximum error bit number, the minimum error bit number, and the maximum offset data and the minimum offset data in the multiple flash memory particles, calculate the normalized value of the error bit number according to each error bit number, the maximum error bit number, and the minimum error bit number, calculate the normalized value of the offset data according to each offset data, the maximum offset data, and the minimum offset data, assign weight values ​​to the error bit number and the offset data according to the application type of the flash memory particle, and calculate Calculate the first product of the normalized value of the number of error bits in each flash memory particle and the corresponding weight value, and the second product of the normalized value of the offset data and the corresponding weight value, take the sum of the first product and the second product as the evaluation value of the flash memory particle, randomly select a preset number of evaluation values ​​from the evaluation values ​​of all flash memory particles as the initial centroid, calculate the distance from each evaluation value to all initial centroids, and assign all evaluation values ​​to the nearest initial centroid to obtain a preset number of clusters, calculate the mean of all evaluation values ​​in each cluster, and use the mean as the second centroid to iterate the centroids, and when the iteration is completed, use the final cluster as the preset number of classifications. The solution provided in the embodiment of the present application can perform normalized weighted averaging on the number of error bits and the offset data of the read voltage of the flash memory particle, thereby calculating the corresponding evaluation value, and classifying based on the evaluation value, thereby improving the accuracy of flash memory particle division.

[0102] In order to implement the above method, an embodiment of the present invention further provides a flash memory testing device, which can be integrated into a computer device such as a mobile phone, a personal computer, a tablet computer, etc.

[0103] For example, Figure 3 FIG. 1 is a schematic diagram of a first structure of a flash memory test device provided by an embodiment of the present invention. The flash memory test device is applied to a storage device, and the storage device includes a storage controller and a processor, and specifically may include:

[0104] An acquisition unit 301 is used to acquire the error bit number and read voltage offset data corresponding to each of a plurality of flash memory particles through a storage controller;

[0105] A first calculation unit 302, configured to obtain, through a processor, a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles;

[0106] A second calculation unit 303 is used to obtain the weight value of the number of error bits and the offset data, and obtain the evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data and the weight value;

[0107] The dividing unit 304 is configured to obtain the test results of the plurality of flash memory particles according to the evaluation value of each of the flash memory particles.

[0108] In one embodiment, see Figure 4 , Figure 4 is a second structural diagram of a flash memory testing device provided by an embodiment of the present invention, wherein:

[0109] The first calculation unit 302 may specifically include:

[0110] An acquisition subunit 3021 is used to acquire a maximum value of the number of error bits, a minimum value of the number of error bits, and a maximum value and a minimum value of the offset data in a plurality of flash memory particles;

[0111] A first calculation subunit 3022, configured to calculate a normalized value of the number of error bits according to each of the number of error bits, the maximum number of error bits, and the minimum number of error bits;

[0112] The second calculation subunit 3023 is used to calculate the normalized value of the offset data according to each of the offset data, the maximum value of the offset data and the minimum value of the offset data.

[0113] Furthermore, the second calculation unit 303 may specifically include:

[0114] An allocating subunit 3031 is used to allocate weight values ​​to the number of error bits and the offset data respectively according to the application type of the flash memory particle;

[0115] The third calculation subunit 3032 is used to calculate the first product of the normalized value of the number of error bits in each of the flash memory particles and the corresponding weight value, calculate the second product of the normalized value of the offset data in each of the flash memory particles and the corresponding weight value, and use the sum of the first product and the second product as the evaluation value of the flash memory particle.

[0116] The flash memory test device proposed in the embodiment of the present invention can obtain the error bit number and the offset data of the read voltage corresponding to each of the multiple flash memory particles through the storage controller, and then the processor obtains the normalized value of the error bit number and the normalized value of the offset data of each flash memory particle, obtains the weight value of the error bit number and the offset data, obtains the evaluation value of each flash memory particle according to the normalized value of the error bit number, the normalized value of the offset data and the weight value, and obtains the test results of multiple flash memory particles according to the evaluation value of each flash memory particle. The solution provided in the embodiment of the present application can perform normalized weighted average on the error bit number and the offset data of the read voltage of the flash memory particles, thereby calculating the corresponding evaluation value, and classifying based on the score, thereby improving the accuracy of flash memory particle classification.

[0117] All of the above technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described in detail here.

[0118] An embodiment of the present application further provides a computer device, including a memory and a processor, wherein the processor is used to execute the process in the flash memory testing method provided in the present embodiment by calling a computer program stored in the memory.

[0119] For example, the computer device mentioned above may be a terminal device with corresponding functions such as a mobile phone, a tablet computer, a personal computer, a cloud computer, etc. Figure 5 , Figure 5 A schematic diagram of the structure of a computer provided in an embodiment of the present application.

[0120] The computer device 400 may include components such as a memory 401 and a processor 402. Those skilled in the art will appreciate that Figure 5 The computer device structure shown in the figure does not constitute a limitation on the computer device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0121] The memory 401 may be used to store applications and data. The applications stored in the memory 401 include executable codes. The applications may be composed of various functional modules. The processor 402 executes various functional applications and data processing by running the applications stored in the memory 401.

[0122] Processor 402 is the control center of the computer device. It uses various interfaces and lines to connect the various parts of the entire computer device. By running or executing applications stored in memory 401 and calling data stored in memory 401, it executes various functions of the computer device and processes data, thereby monitoring the computer device as a whole.

[0123] In this embodiment, the processor 402 in the computer device will load the executable code corresponding to the process of one or more application programs into the memory 401 according to the following instructions, and the processor 402 will run the application program stored in the memory 401 to execute:

[0124] Acquiring the error bit number and read voltage offset data corresponding to each of the plurality of flash memory particles through the storage controller;

[0125] Acquiring, by the processor, a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles;

[0126] Obtaining weight values ​​of the number of error bits and the offset data, and obtaining an evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data, and the weight value;

[0127] The test results of the plurality of flash memory particles are obtained according to the evaluation value of each of the flash memory particles.

[0128] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0129] To this end, an embodiment of the present application provides a storage medium in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any data calculation method provided in the embodiment of the present application. For example, the instructions can execute the following steps:

[0130] Acquiring the error bit number and read voltage offset data corresponding to each of the plurality of flash memory particles through the storage controller;

[0131] Acquiring, by the processor, a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles;

[0132] Obtaining weight values ​​of the number of error bits and the offset data, and obtaining an evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data, and the weight value;

[0133] The test results of the plurality of flash memory particles are obtained according to the evaluation value of each of the flash memory particles.

[0134] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0135] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0136] Since the instructions stored in the storage medium can execute the steps in any data calculation method provided in the embodiments of the present application, the beneficial effects that can be achieved by any data calculation method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0137] In the embodiments of the computer device and the readable storage medium provided in the present application, all the technical features of the embodiments of the above-mentioned method are included. The expansion and explanation content of the specification are the same as the adaptability of the embodiments of the above-mentioned positioning method, and will not be repeated here.

[0138] An embodiment of the present application also provides a chip, including a memory and a processor, wherein the memory is used to store programs, and the processor is used to call and run programs from the memory, so that a device equipped with the chip executes the methods in various possible embodiments as described above.

[0139] In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described in detail in a certain embodiment, please refer to the detailed description of the flash memory testing device above, and will not be repeated here.

[0140] The flash memory testing method provided in the embodiment of the present application belongs to the same concept as the flash memory testing device in the above embodiment. The specific implementation process is detailed in the flash memory testing device embodiment and will not be repeated here.

[0141] It should be noted that, for the flash memory testing method described in the embodiment of the present application, ordinary technicians in this field can understand that all or part of the process of implementing the flash memory testing method described in the embodiment of the present application can be completed by controlling the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, such as stored in a memory, and executed by at least one processor, and the execution process may include the process of the embodiment of the flash memory testing method. Among them, the storage medium can be a disk, an optical disk, a read-only memory, a random access memory (Random Access Memory, RAM), etc.

[0142] The above is a detailed introduction to a flash memory testing method, device, storage medium and computer equipment provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0143] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A flash memory testing method, applied to a flash memory testing device, wherein the flash memory testing device comprises a processor and a storage controller, wherein: include: The number of error bits and read voltage offset data corresponding to each of the plurality of flash memory particles are obtained through the storage controller, wherein the read voltage offset data is calculated by the voltage value of the flash memory particle in the current state and the preset reference voltage, and the step of calculating by the voltage value of the flash memory particle in the current state and the preset reference voltage includes: obtaining the information of the word line currently in use, and then matching the target storage page for the currently used word line based on the pre-created correspondence between the storage page and the region, and then performing a read operation on the target storage page using the reference voltage candidate table in the flash memory test device, wherein the reference voltage candidate table includes a plurality of candidate reference voltages, and each read operation uses a different reference voltage, and the corresponding error bit rate is recorded, and finally the error bit rates corresponding to all read operations are counted, and the reference voltage corresponding to the minimum error bit rate is found, and the reference voltage corresponding to the minimum error bit rate is determined as the offset voltage amount in the current use stage; Acquiring, by the processor, a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles; Obtaining weight values ​​of the number of error bits and the offset data, and obtaining an evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data, and the weight value; A preset number of evaluation values ​​are randomly selected from the evaluation values ​​of all flash memory particles as initial centroids, the distance from each evaluation value to all initial centroids is calculated, and all evaluation values ​​are assigned to the initial centroids with the closest distance to obtain a preset number of clusters, the mean of all evaluation values ​​in each cluster is calculated, and the mean is used as the second centroid, the distance from each evaluation value to all second centroids is calculated, and all evaluation values ​​are assigned to the second centroids with the closest distance to obtain a preset number of clusters, the mean of all evaluation values ​​in each cluster is calculated, and the mean is used as the third centroid, the centroids are calculated repeatedly until the centroids no longer change, then it is confirmed that the centroid iteration is completed, and the final clusters are used as the preset number of classifications to obtain the test results of the multiple flash memory particles.

2. The flash memory testing method according to claim 1, wherein: Obtaining a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles, including: Obtaining the maximum value of the number of error bits, the minimum value of the number of error bits, and the maximum value and the minimum value of the offset data of multiple flash memory particles; Calculating a normalized value of the number of error bits according to each of the number of error bits, the maximum number of error bits, and the minimum number of error bits; The normalized value of the offset data is calculated according to each of the offset data, the maximum value of the offset data and the minimum value of the offset data.

3. The flash memory testing method according to claim 2, wherein: Obtaining the weight values ​​of the number of error bits and the offset data, and obtaining the evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data, and the weight value, including: According to the application type of the flash memory particles, weight values ​​are respectively assigned to the number of error bits and the offset data; Calculating a first product of a normalized value of the number of error bits in each of the flash memory particles and a corresponding weight value; Calculating a second product of a normalized value of the offset data in each of the flash memory particles and a corresponding weight value; The sum of the first product and the second product is used as an evaluation value of the flash memory particle.

4. The flash memory testing method according to claim 1, wherein: The final clusters are a preset number of categories, including: The flash memory particles in the cluster corresponding to the centroid with the smallest value are determined as first-class particles; The flash memory particles in the cluster corresponding to the centroid with the second smallest value are determined as second-class particles; The flash memory particles in the cluster corresponding to the centroid with the largest value are determined as third-class particles.

5. The flash memory testing method according to claim 1, wherein: The method further comprises: Calculate the variance of the flash memory particle evaluation value in each category, and the mean difference of the flash memory particle evaluation values ​​between different categories; The number of the categories is adjusted according to the variance and mean difference.

6. A flash memory testing device, comprising a processor and a storage controller, characterized in that: include: an acquisition unit, used for acquiring the number of error bits and read voltage offset data corresponding to each of the plurality of flash memory particles through the storage controller, wherein the read voltage offset data is calculated by comparing the voltage value of the flash memory particle in the current state with a preset reference voltage, and the step of calculating by comparing the voltage value of the flash memory particle in the current state with the preset reference voltage comprises: acquiring the information of the word line currently in use, and then matching the target storage page for the word line currently in use based on the pre-created correspondence between the storage page and the region, and then performing a read operation on the target storage page using the reference voltage candidate table in the flash memory test device, wherein the reference voltage candidate table contains a plurality of candidate reference voltages, and each read operation uses a different reference voltage, and records the corresponding error bit rate, and finally statistics the error bit rates corresponding to all read operations, and finds the reference voltage corresponding to the minimum error bit rate, and determines the reference voltage corresponding to the minimum error bit rate as the offset voltage amount in the current use stage; A first calculation unit, configured to obtain, through the processor, a normalized value of the number of error bits and a normalized value of the offset data of each of the flash memory particles; A second calculation unit, used to obtain the weight value of the number of error bits and the offset data, and obtain the evaluation value of each of the flash memory particles according to the normalized value of the number of error bits, the normalized value of the offset data and the weight value; A partitioning unit is used to randomly select a preset number of evaluation values ​​from the evaluation values ​​of all flash memory particles as initial centroids, calculate the distance from each evaluation value to all initial centroids, and distribute all evaluation values ​​to the initial centroids with the closest distance to obtain a preset number of clusters, calculate the mean of all evaluation values ​​in each cluster, and use the mean as the second centroid, calculate the distance from each evaluation value to all second centroids, and distribute all evaluation values ​​to the second centroids with the closest distance to obtain a preset number of clusters, calculate the mean of all evaluation values ​​in each cluster, and use the mean as the third centroid, repeatedly calculate the centroids until the centroids no longer change, then confirm that the centroid iteration is completed, and use the final clusters as the preset number of classifications to obtain the test results of the multiple flash memory particles.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 5.

8. A computer device comprising a memory and a processor, characterized in that: The processor executes the method according to any one of claims 1 to 5 by calling the computer program stored in the memory.

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