Capacitor chip structure and manufacturing method

Abstract

The disclosed embodiment provides a capacitor chip structure and a manufacturing method, the manufacturing method comprising: forming a first conductive layer on a first surface of a glass substrate; forming a capacitor dielectric layer on a side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covers the side wall of the first conductive layer, the capacitor dielectric layer is provided with a first through hole, the first through hole penetrates the capacitor dielectric layer and exposes a portion of the surface of the first conductive layer; forming a second conductive layer on a side of the capacitor dielectric layer away from the first conductive layer; the boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer; forming an insulating layer on a side of the second conductive layer away from the capacitor dielectric layer; forming a first electrical connection structure; and forming a second electrical connection structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a capacitor chip structure and a manufacturing method. Background Art

[0002] Multi-layer ceramic capacitors (MLCC) are made of ceramic dielectric diaphragms with printed electrodes (inner electrodes) stacked in an offset manner, sintered at a high temperature once to form a ceramic chip, and then sealed with a metal layer (outer electrode) at both ends of the chip to form a monolithic structure, so it is also called a monolithic capacitor.

[0003] At present, the substrate of the capacitor chip structure in the chip-type multilayer ceramic capacitor is mostly made of silicon substrate. The supporting strength of the silicon substrate is not strong enough, and the capacitor chip structure needs to be packaged twice before it can be used. Summary of the invention

[0004] The present disclosure provides a capacitor chip structure and a manufacturing method to improve the support strength of a substrate in the capacitor chip structure and reduce packaging difficulty.

[0005] The present disclosure provides a method for manufacturing a capacitor chip structure, comprising:

[0006] Providing a glass substrate, the glass substrate comprising a first surface and a second surface disposed opposite to each other;

[0007] forming a first conductive layer on a first surface of the glass substrate;

[0008] A capacitor dielectric layer is formed on a side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covers a side wall of the first conductive layer, and the capacitor dielectric layer is provided with a first through hole, the first through hole penetrates the capacitor dielectric layer and exposes a portion of the surface of the first conductive layer;

[0009] A second conductive layer is formed on a side of the capacitor dielectric layer away from the first conductive layer; the boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer;

[0010] An insulating layer is formed on a side of the second conductive layer away from the capacitor dielectric layer, the insulating layer also covers the side wall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the side wall of the capacitor dielectric layer and the side wall of the first through hole; the insulating layer is provided with a second through hole and a third through hole penetrating the insulating layer, the second through hole exposes a part of the surface of the second conductive layer;

[0011] forming a first electrical connection structure, wherein a central portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate and the second through hole is electrically connected to the second conductive layer; and an edge portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate;

[0012] A second electrical connection structure is formed, wherein the central portion of the second electrical connection structure is located where the third through hole is electrically connected to the first conductive layer, and the edge portion of the second electrical connection structure is located on a surface of the insulating layer away from the glass substrate.

[0013] Optionally, providing a glass substrate includes:

[0014] providing a motherboard of a glass substrate;

[0015] Forming a first conductive layer on the first surface of the glass substrate comprises:

[0016] A plurality of first conductive layers are formed on the first surface of the mother plate of the glass substrate, and a cutting path is formed between two adjacent first conductive layers;

[0017] Forming a capacitor dielectric layer on a side of the first conductive layer away from the glass substrate comprises:

[0018] forming a capacitor dielectric layer on a side of the first conductive layer away from the glass substrate motherboard;

[0019] Before forming the first electrical connection structure, the method further includes: cutting the motherboard of the glass substrate along the cutting path to cut into a plurality of glass substrate sub-boards, wherein the glass substrate sub-boards serve as glass substrates for a single-grain capacitor chip structure.

[0020] Optionally, when forming a second conductive layer on a side of the capacitor dielectric layer away from the first conductive layer, the method further includes:

[0021] forming a third conductive layer, wherein the third conductive layer and the second conductive layer are disposed on the same layer;

[0022] The third conductive layer and the second conductive layer are insulated by the insulating layer;

[0023] The central portion of the third conductive layer is located at the first through hole and is electrically connected to the first conductive layer, and the edge portion of the third conductive layer is located at a side of the capacitor dielectric layer away from the first conductive layer;

[0024] A central portion of the second electrical connection structure is located in the third through hole and is electrically connected to the first conductive layer through the third conductive layer.

[0025] Optionally, forming an insulating layer on a side of the second conductive layer away from the capacitor dielectric layer includes:

[0026] A passivation layer is formed on the side of the second conductive layer away from the capacitor dielectric layer, and the passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer and the sidewall of the first through hole.

[0027] Optionally, after forming a passivation layer on a side of the second conductive layer away from the capacitor dielectric layer, the method further comprises:

[0028] A buffer layer is formed on a side of the passivation layer away from the second conductive layer, and the buffer layer also covers the sidewalls of the passivation layer in the second through hole and the third through hole.

[0029] Optionally, forming an insulating layer on a side of the second conductive layer away from the capacitor dielectric layer includes:

[0030] forming a passivation layer on a side of the second conductive layer away from the capacitor dielectric layer, the passivation layer also being located on a side of the third conductive layer away from the first conductive layer;

[0031] The passivation layer also covers the side wall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the side wall of the capacitor dielectric layer, and a portion of the surface of the third conductive layer away from the first conductive layer;

[0032] The third conductive layer and the second conductive layer are insulated by the passivation layer.

[0033] Optionally, after forming a passivation layer on a side of the second conductive layer away from the capacitor dielectric layer, the method further includes:

[0034] A buffer layer is formed on a side of the passivation layer away from the second conductive layer and the third conductive layer, and the buffer layer also covers the sidewalls of the passivation layer in the second through hole and the third through hole.

[0035] Optionally, the capacitor chip structure includes two oppositely disposed first long sides and two oppositely disposed first short sides in a cross-sectional shape parallel to the first surface, the first long sides and the first short sides are disposed perpendicularly, and the length of the first long side is greater than the length of the first short side;

[0036] The second through hole is located at the first end of the capacitor chip structure, the third through hole is located at the second end of the capacitor chip structure, and the direction in which the first end of the capacitor chip structure points to the second end of the capacitor chip structure is parallel to the first long side.

[0037] Optionally, forming the first electrical connection structure includes:

[0038] forming a fourth conductive layer in the second through hole and on a portion of the surface of the insulating layer away from the glass substrate;

[0039] A first pad is formed on a side of the fourth conductive layer away from the insulating layer.

[0040] Optionally, forming a first pad on a side of the fourth conductive layer away from the insulating layer includes:

[0041] A first pad formed on a side of the fourth conductive layer away from the insulating layer, the cross-sectional pattern of which on the first surface includes two oppositely disposed second long sides and two oppositely disposed second short sides;

[0042] The second long side is arranged in parallel with the first short side, the second short side is arranged in parallel with the first long side, and the length of the second long side is greater than the length of the second short side;

[0043] The length of the second short side is less than one third of the length of the first long side.

[0044] Optionally, the length of the second short side is greater than or equal to 10% of the length of the first long side, and less than or equal to 30% of the length of the first long side;

[0045] And / or, the length of the second long side is greater than or equal to 40% of the length of the first short side, and less than or equal to 90% of the length of the first short side.

[0046] Optionally, on one side of the first end of the capacitor chip structure, a distance between the second long side and the first short side close to the first end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns;

[0047] And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the second short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

[0048] Optionally, forming the second electrical connection structure includes:

[0049] forming a fifth conductive layer in the third through hole and on a portion of the surface of the insulating layer away from the glass substrate;

[0050] A second pad is formed on a side of the fifth conductive layer away from the insulating layer.

[0051] Optionally, forming a second pad on a side of the fifth conductive layer away from the insulating layer includes:

[0052] A second pad formed on a side of the fifth conductive layer away from the insulating layer, the cross-sectional shape of which on the first surface includes two third long sides and two third short sides that are oppositely disposed;

[0053] The third long side is arranged in parallel with the first short side, the third short side is arranged in parallel with the first long side, the length of the third long side is greater than the length of the third short side, and the length of the third short side is less than one third of the length of the first long side.

[0054] Optionally, the length of the third short side is greater than or equal to 10% of the length of the first long side, and less than or equal to 30% of the length of the first long side;

[0055] And / or, the length of the third long side is greater than or equal to 40% of the length of the first short side, and less than or equal to 90% of the length of the first short side.

[0056] Optionally, on one side of the second end of the capacitor chip structure, a distance between the third long side close to the second end of the capacitor chip structure and the first short side is greater than or equal to 15 microns and less than or equal to 40 microns;

[0057] And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the third short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

[0058] Optionally, a thickness of the first pad is greater than or equal to 15 microns and less than or equal to 60 microns.

[0059] Optionally, a thickness of the second pad is greater than or equal to 15 microns and less than or equal to 60 microns.

[0060] Optionally, a value by which a boundary of the second conductive layer is retracted toward a center of the capacitor chip structure relative to a boundary of the first conductive layer is greater than or equal to 3 micrometers.

[0061] Optionally, the plane size of the motherboard of the glass substrate includes any one of 550×650 mm, 680×880 mm, 730×920 mm, 1100×1300 mm and 1300×1500 mm.

[0062] Optionally, cutting the motherboard of the glass substrate along the cutting road to cut into a plurality of glass substrates comprises:

[0063] The mother plate of the glass substrate is cut from the cutting street to be cut into N glass substrates, where the number N is greater than or equal to 4 and less than or equal to 20.

[0064] The present disclosure also provides a capacitor chip structure, which is prepared by the manufacturing method of the capacitor chip structure described in any of the above embodiments of the present disclosure.

[0065] The manufacturing method of the capacitor chip structure provided by the embodiment of the present disclosure selects a glass substrate as a substrate, which can provide greater structural strength relative to a silicon substrate, so that the capacitor chip structure does not need secondary packaging to improve its structural strength, reduces the packaging difficulty, and makes the capacitor chip structure have a better quality factor (Q value). Among them, the capacitor dielectric layer is used to insulate the first conductive layer and the second conductive layer, the first conductive layer is used as the first plate of the capacitor, and the electrical signal is obtained through the second electrical connection structure; the second conductive layer is used as the second plate of the capacitor, and the electrical signal is obtained through the first electrical connection structure. The boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer, so that the surface and side walls of the non-electrically connected part of the first conductive layer and the second electrical connection structure are covered by the capacitor dielectric layer, and the first conductive layer and the second conductive layer are better electrically isolated. Among them, the insulating layer covers the surface and side walls of the capacitor dielectric layer that are not covered by the second conductive layer, and the insulating layer also covers the surface and side walls of the non-electrically connected part of the second conductive layer and the first electrical connection structure, as well as the surface of the non-electrically connected part of the first conductive layer and the second electrical connection structure. The capacitor dielectric layer and the insulating layer play the role of insulating packaging for the capacitor chip structure. Furthermore, the first electrical connection structure and the second electrical connection structure are located on the same surface of the capacitor chip structure, which reduces the difficulty of mounting the capacitor chip structure and facilitates electrical connection with other electrical components.

[0066] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be described in detail one by one below. It should be noted that the drawings in the following description only relate to the embodiments of the present disclosure, but not to limit the present disclosure. It must also be pointed out that the various features shown in the drawings are not drawn to scale. In fact, for the sake of clarity, it is sometimes necessary to arbitrarily increase or decrease the size of various features.

[0068] Figure 1 :A process flow chart related to a method for manufacturing a capacitor chip structure.

[0069] Figures 2 to 9 : Show Figure 1 Schematic cross-sectional view of the various process steps associated with the manufacturing method.

[0070] Fig.10:A process flow chart related to a method for manufacturing a capacitor chip structure.

[0071] Fig.11 :A process flow chart related to a method for manufacturing a capacitor chip structure.

[0072] Figures 12 to 17 : Show Fig.11 Schematic cross-sectional view of the various process steps associated with the manufacturing method.

[0073] Figures 1 to 17 The reference numerals in the figures are as follows:

[0074] 100: glass substrate; 101: first surface; 102: second surface; 110: first conductive layer; 120: capacitor dielectric layer; 130: second conductive layer; 301: insulating layer; 135: passivation layer; 140: buffer layer; 300: first through hole; 150: second through hole; 160: third through hole; 302: first electrical connection structure; 303: second electrical connection structure; 170: fourth conductive layer; 190: first solder pad; 180: fifth conductive layer; 200: second solder pad: 304: first long side; 305: first short side; 306: second long side; 307: second short side; 308: third long side; 309: third short side; L1: length of first long side; W1: length of first short side; L2: length of second short side; W2: length of second long side; L3: length of third short side; W3: length of third long side; 400: third conductive layer. DETAILED DESCRIPTION

[0075] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, in order to simplify the drawings, well-known structures and devices can be simplified for display. And it should be noted that, in the absence of conflict, the embodiments in the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0076] In order to improve the support strength of the substrate in the capacitor chip structure and reduce the packaging difficulty, the embodiment of the present disclosure provides the following technical solutions:

[0077] Figure 1 The following is a method for manufacturing a capacitor chip structure, which discloses the process steps related to the embodiment, referred to as embodiment 1. The manufacturing method includes:

[0078] S11: providing a glass substrate, wherein the glass substrate comprises a first surface and a second surface which are opposite to each other.

[0079] S12: forming a first conductive layer on the first surface of the glass substrate.

[0080] S13: forming a capacitor dielectric layer on a side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covers the side wall of the first conductive layer, and the capacitor dielectric layer is provided with a first through hole, which penetrates the capacitor dielectric layer and exposes a portion of the surface of the first conductive layer.

[0081] S14: forming a second conductive layer on a side of the capacitor dielectric layer away from the first conductive layer; a boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to a boundary of the first conductive layer.

[0082] S15: An insulating layer is formed on a side of the second conductive layer away from the capacitor dielectric layer, the insulating layer also covers the side wall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the side wall of the capacitor dielectric layer and the side wall of the first through hole; the insulating layer is provided with a second through hole and a third through hole penetrating the insulating layer, the second through hole exposes a portion of the surface of the second conductive layer, and the third through hole is connected to the first through hole.

[0083] S16: forming a first electrical connection structure, wherein a central portion of the first electrical connection structure is located at the second through hole and is electrically connected to the second conductive layer, and an edge portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate.

[0084] S17: forming a second electrical connection structure, wherein a central portion of the second electrical connection structure is located where the third through hole is electrically connected to the first conductive layer, and an edge portion of the second electrical connection structure is located on a surface of the insulating layer away from the glass substrate.

[0085] Figures 2 to 9 The figure shows a schematic cross-sectional view of each process step related to the manufacturing method of the capacitor chip structure disclosed in the present invention (Embodiment 1). The following is a detailed description of each related process step in conjunction with the accompanying drawings.

[0086] Figure 2 Detailed process diagram of process steps related to process step S11 of the method for manufacturing a capacitor chip structure (Embodiment 1) of the present disclosure. A glass substrate 100 is provided, and the glass substrate 100 includes a first surface 101 and a second surface 102 .

[0087] Figure 3 The detailed process diagram of the process steps related to the process step S12 of the manufacturing method of the capacitor chip structure disclosed in the present invention (embodiment 1) is shown in FIG. A first conductive layer 110 is deposited on the first surface 101 of the glass substrate 100 by a deposition process, and the first conductive layer 110 serves as the lower electrode of the capacitor.

[0088] Figure 4-Figure 7 It is a detailed process schematic diagram of process steps related to process steps S13-S15 of the method for manufacturing the capacitor chip structure (Example 1) of the present disclosure.

[0089] like Figure 4 As shown, a capacitor dielectric layer 120 is formed by a deposition process on a side of the first conductive layer 110 away from the glass substrate 100. The capacitor dielectric layer 120 covers the sidewall of the first conductive layer 110.

[0090] like Figure 5 As shown, a second conductive layer 130 is formed by a deposition process on a side of the capacitor dielectric layer 120 away from the first conductive layer 110, and the second conductive layer 130 is patterned so that the boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110, and the second conductive layer 130 serves as the upper electrode of the capacitor. The second conductive layer 130 includes any one of Ti, Al, Cu, Cr, Mo, W and TiW or a stack of two or more thereof. Preferably, the surface material of the second conductive layer 130 is any one of Ti, Cr and TiW or a stack of two or more thereof, which have good adhesion to other materials, are conducive to good adhesion to the materials attached to their surfaces, and increase reliability. As shown Figure 6 As shown, the capacitor dielectric layer 120 is patterned and etched to form a first through hole 300 in the capacitor dielectric layer 120. The first through hole 300 penetrates the capacitor dielectric layer 120 and exposes a portion of the surface of the first conductive layer 110. The capacitor dielectric layer 120 includes any one of silicon oxide, silicon nitride, strontium zirconate, barium titanate, and a combination of at least two of them.

[0091] An insulating layer 301 is formed on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the insulating layer 301 also covers the side wall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, the side wall of the capacitor dielectric layer 120, and the side wall of the first through hole 300; the insulating layer 301 is provided with a second through hole 150 and a third through hole 160 penetrating the insulating layer 301, the second through hole 150 exposes a part of the surface of the second conductive layer 130, and the third through hole 160 is connected to the first through hole 300. The insulating layer 301 includes a passivation layer 135, or the insulating layer 301 includes a passivation layer 135 and a buffer layer 140. The insulating layer 301 is formed on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, including the following steps:

[0092] like Figure 6As shown, a passivation layer 135 is formed on a side of the second conductive layer 130 away from the capacitor dielectric layer 120. The passivation layer 135 is patterned and etched to form a sub-through hole 300a and a sub-through hole 300b in the passivation layer 135. The sub-through hole 300a exposes the second conductive layer 130, and the sub-through hole 300b exposes the first conductive layer 110. The passivation layer 135 also covers the sidewalls of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, the sidewalls of the capacitor dielectric layer 120, and the sidewalls of the first through hole 300. The passivation layer 135 includes silicon oxide, silicon nitride, or a stacked combination of the two.

[0093] like Figure 7 As shown, a buffer layer 140 is formed on the side of the passivation layer 135 away from the second conductive layer 130. The buffer layer 140 is a photosensitive material, specifically a polyimide material. The buffer layer 140 is patterned by a photolithography process so that the buffer layer 140 also covers the sidewalls of the passivation layer 135 in the second through hole 150 and the third through hole 160, and a sub-through hole exposing the first conductive layer 110 and the second conductive layer 130 is formed in the buffer layer 140.

[0094] Specifically, the passivation layer 135 covers the surface and sidewall of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The passivation layer 135 also covers the surface and sidewall of the non-electrically connected portion of the second conductive layer 130 and the first electrical connection structure 302, and the surface of the non-electrically connected portion of the first conductive layer 110 and the second electrical connection structure 303. The capacitor dielectric layer 120 and the passivation layer 135 play the role of insulating packaging for the capacitor chip structure. The passivation layer 135 includes any one of silicon oxide and silicon nitride or a combination of them. The buffer layer 140 is located on the side of the passivation layer 135 away from the second conductive layer 130. The buffer layer 140 also covers the sidewalls of the passivation layer 135 in the second through hole 150 and the third through hole 160, so that the capacitor dielectric layer 120, the passivation layer 135 and the buffer layer 140 play the role of insulating packaging for the capacitor chip structure. And the buffer layer 140 can provide stress buffering during the use of the capacitor chip structure patch, thereby improving the reliability of the capacitor chip structure.

[0095] Figure 8 The figure shows a top view of a capacitor chip structure, and the position of the AA′ section is marked in the figure. Fig. 9 is a cross-sectional schematic diagram of a capacitor chip structure. Figure 8 AA' section of the plan view shown.

[0096] Figure 8-Figure 9 It is a detailed process schematic diagram of process steps related to process steps S16-S17 of the method for manufacturing the capacitor chip structure (Example 1) of the present disclosure.

[0097] like Figure 8 and Fig. 9 As shown, the first electrical connection structure 302 is formed by electroplating process, the central portion of the first electrical connection structure 302 is located at the second through hole 150 and electrically connected to the second conductive layer 130 , and the edge portion of the first electrical connection structure 302 is located at the surface of the insulating layer 301 away from the glass substrate 100 .

[0098] like Figure 8 and Fig. 9 As shown, the second electrical connection structure 303 is formed by electroplating process, the central portion of the second electrical connection structure 303 is located at the third through hole 160 and electrically connected to the first conductive layer 110 , and the edge portion of the second electrical connection structure 303 is located at the surface of the insulating layer 301 away from the glass substrate 100 .

[0099] The manufacturing method of the capacitor chip structure provided by the embodiment of the present disclosure selects a glass substrate 100 as a substrate, which can provide greater structural strength than a silicon substrate, so that the capacitor chip structure does not need secondary packaging to improve its structural strength, reduces the packaging difficulty, and makes the capacitor chip structure have a better quality factor (Q value). Among them, the capacitor dielectric layer 120 is used to insulate the first conductive layer 110 and the second conductive layer 130. The first conductive layer 110 is used as the first plate of the capacitor to obtain an electrical signal through the second electrical connection structure 303; the second conductive layer 130 is used as the second plate of the capacitor to obtain an electrical signal through the first electrical connection structure 302. The boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110, so that the surface and sidewall of the non-electrically connected part of the first conductive layer 110 and the second electrical connection structure 303 are covered by the capacitor dielectric layer 120, so as to achieve better electrical isolation between the first conductive layer 110 and the second conductive layer 130. Among them, the insulating layer 301 covers the surface and side walls of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The insulating layer 301 also covers the surface and side walls of the non-electrically connected portion of the second conductive layer 130 and the first electrical connection structure 302, as well as the surface of the non-electrically connected portion of the first conductive layer 110 and the second electrical connection structure 303. The capacitor dielectric layer 120 and the insulating layer 301 play the role of insulating packaging for the capacitor chip structure. The first electrical connection structure 302 and the second electrical connection structure 303 are located on the same surface of the capacitor chip structure, which reduces the difficulty of mounting the capacitor chip structure and facilitates electrical connection with other electrical components.

[0100] Optional, such as Figure 8As shown, the capacitor chip structure includes two oppositely disposed first long sides 304 and two oppositely disposed first short sides 305 in a cross-sectional shape parallel to the first surface 101, the first long sides 304 and the first short sides 305 are disposed vertically, and the length L1 of the first long side 304 is greater than the length W1 of the first short side 305; Figure 2 As shown, the second through hole 150 is located at the first end of the capacitor chip structure, the third through hole 160 is located at the second end of the capacitor chip structure, and the first end of the capacitor chip structure points to the direction of the second end of the capacitor chip structure and is arranged parallel to the first long side 304.

[0101] Specifically, the second through hole 150 and the third through hole 160 are respectively located at the two ends of the capacitor chip structure along the direction of the first long side 304, so that the first electrical connection structure 302 and the second electrical connection structure 303 are respectively located at the two ends of the capacitor chip structure along the direction of the first long side 304, and the distance between the first electrical connection structure 302 and the second electrical connection structure 303 can be set farther, thereby better realizing the electrical isolation between the first electrical connection structure 302 and the second electrical connection structure 303.

[0102] Optionally, forming the first electrical connection structure 302 and forming the second electrical connection structure 303 using an electroplating process includes:

[0103] like Fig. 9 As shown, the fourth conductive layer 170 and the fifth conductive layer 180 are formed in the second through hole 150, the third through hole 160 and the surface of the insulating layer 301 away from the glass substrate 100 by using an electroplating process. Fig. 9 As shown, the first pad 190 is formed on the side of the fourth conductive layer 170 away from the insulating layer 301 by using an electroplating process. The second pad 200 is formed on the side of the fifth conductive layer 180 away from the insulating layer 301.

[0104] The specific steps of the electroplating process are as follows: depositing the electroplating seed layer, the material is Ti / Cu stacking, and the process used is PVD or evaporation process; forming the pattern area of ​​the fourth conductive layer 170 and the fifth conductive layer 180 through the photolithography process, the area to be electroplated is not covered by the photoresist, and the area not to be electroplated is covered by the photoresist. Electroplating Cu or Cu / Ni stacking (together with the electroplating seed layer, collectively referred to as the fourth conductive layer 170 and the fifth conductive layer 180), and then electroplating solder (SnAg alloy) to form the first solder pad 190 and the second solder pad 200 of the solder pad (PAD); then removing the electroplating photoresist; and finally removing the electroplating seed layer outside the solder PAD area.

[0105] Optionally, the fourth conductive layer 170 includes a stack of Ti and Cu or a stack of Ti, Cu and Ni. The first pad 190 includes a SnAg alloy. The fifth conductive layer 180 includes a stack of Ti and Cu or a stack of Ti, Cu and Ni. The second pad 200 includes a SnAg alloy.

[0106] Optionally, forming the first pad 190 on a side of the fourth conductive layer 170 away from the insulating layer 301 includes:

[0107] A first pad 190 is formed on a side of the fourth conductive layer 170 away from the insulating layer 301, and the cross-sectional figure on the first surface 101 includes two oppositely arranged second long sides 306 and two oppositely arranged second short sides 307; the second long side 306 and the first short side 305 are arranged in parallel, the second short side 307 and the first long side 304 are arranged in parallel, the length W2 of the second long side 306 is greater than the length L2 of the second short side 307; the length L2 of the second short side 307 is less than one third of the length L1 of the first long side 304, so as to maximize the area of ​​the first pad 190, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0108] Optional, such as Figure 8 As shown, the length L2 of the second short side 307 is greater than or equal to 10% of the length L1 of the first long side 304, and less than or equal to 30% of the length L1 of the first long side 304; and / or, the length W2 of the second long side 306 is greater than or equal to 40% of the length W1 of the first short side 305, and less than or equal to 90% of the length W1 of the first short side 305, so as to maximize the area of ​​the first pad 190, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0109] Optional, such as Figure 8 As shown, on one side of the first end of the capacitor chip structure, the spacing d1 between the second long side 306 and the first short side 305 close to the first end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns; and / or, on one side of the first end of the capacitor chip structure, the shortest spacing d2 between the second short side 307 and the first long side 304 is greater than or equal to 15 microns and less than or equal to 40 microns, so as to maximize the area of ​​the first pad 190, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0110] Optionally, forming the second pad 200 on a side of the fifth conductive layer 180 away from the insulating layer 301 includes:

[0111] A second pad 200 is formed on one side of the fifth conductive layer 180 away from the insulating layer 301, and the cross-sectional figure on the first surface 101 includes two relatively arranged third long sides 308 and two relatively arranged third short sides 309; the third long side 308 is arranged in parallel with the first short side 305, the third short side 309 is arranged in parallel with the first long side 304, the length W3 of the third long side 308 is greater than the length L3 of the third short side 309, and the length L3 of the third short side 309 is less than one third of the length L1 of the first long side 304, so as to maximize the area of ​​the second pad 200, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0112] Optional, such as Figure 8 As shown, the length of the third short side 309 is greater than or equal to 10% of the length of the first long side 304, and less than or equal to 30% of the length of the first long side 304; and / or, the length W3 of the third long side 308 is greater than or equal to 40% of the length W1 of the first short side 305, and less than or equal to 90% of the length of the first short side 305, so as to maximize the area of ​​the second pad 200, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0113] Optional, such as Figure 8 As shown, on one side of the second end of the capacitor chip structure, the spacing d3 between the third long side 308 and the first short side 305 close to the second end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns; and / or, on one side of the first end of the capacitor chip structure, the shortest spacing d4 between the third short side 309 and the first long side 304 is greater than or equal to 15 microns and less than or equal to 40 microns, so as to maximize the area of ​​the second pad 200, which is beneficial to the heat dissipation and reliability of the capacitor chip structure.

[0114] Optional, such as Fig. 9 As shown, the thickness of the first pad 190 is greater than or equal to 15 microns and less than or equal to 60 microns, which is convenient for mounting and connecting with other electrical components.

[0115] Optional, such as Fig. 9 As shown, the thickness of the second pad 200 is greater than or equal to 15 microns and less than or equal to 60 microns, which is convenient for mounting and connecting with other electrical components.

[0116] Optional, such as Fig. 9 As shown, the value of the boundary of the second conductive layer 130 being retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110 is greater than or equal to 3 micrometers.

[0117] The boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure by a value greater than or equal to 3 microns relative to the boundary of the first conductive layer 110, so as to provide more space for the insulating layer 301 covering the surface of the capacitor dielectric layer 120, so as to achieve better electrical isolation between the first conductive layer 110 and the second conductive layer 130 by covering the surface and side walls of the non-electrically connected parts of the first conductive layer 110 and the second electrical connection structure 303 through the capacitor dielectric layer 120.

[0118] Fig.10 The following is a method for manufacturing a capacitor chip structure, which discloses the process steps related to the embodiment, referred to as embodiment 2. The manufacturing method includes:

[0119] S21: providing a mother plate of a glass substrate, wherein the mother plate of the glass substrate comprises a first surface and a second surface which are arranged opposite to each other.

[0120] S22: forming a plurality of first conductive layers spaced apart from each other on the first surface of the mother plate of the glass substrate; a cutting path is formed between two adjacent first conductive layers.

[0121] S23: forming a capacitor dielectric layer on a side of the first conductive layer away from the motherboard of the glass substrate; the capacitor dielectric layer also covers the side wall of the first conductive layer, and the capacitor dielectric layer is provided with a first through hole, which penetrates the capacitor dielectric layer and exposes a portion of the surface of the first conductive layer.

[0122] S24: forming a second conductive layer on a side of the capacitor dielectric layer away from the first conductive layer; a boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to a boundary of the first conductive layer.

[0123] S25: An insulating layer is formed on a side of the second conductive layer away from the capacitor dielectric layer, the insulating layer also covers the side wall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the side wall of the capacitor dielectric layer and the side wall of the first through hole; the insulating layer is provided with a second through hole and a third through hole penetrating the insulating layer, the second through hole exposes a portion of the surface of the second conductive layer, and the third through hole is connected to the first through hole.

[0124] S26: cutting the motherboard of the glass substrate along the cutting path to cut into a plurality of glass substrate sub-boards, the glass substrate sub-boards being used as glass substrates of the single-chip capacitor chip structure.

[0125] S27: forming a first electrical connection structure, wherein a central portion of the first electrical connection structure is located at the second through hole and is electrically connected to the second conductive layer, and an edge portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate.

[0126] S28: forming a second electrical connection structure, wherein a central portion of the second electrical connection structure is located where the third through hole is electrically connected to the first conductive layer, and an edge portion of the second electrical connection structure is located on a surface of the insulating layer away from the glass substrate.

[0127] Fig.10 The method and method of the capacitor chip structure of the second embodiment shown in FIG. Figure 1 The difference between the first embodiment and the second embodiment is that the second embodiment has a process step S26, which cuts the glass substrate motherboard into a plurality of glass substrate sub-boards and then performs subsequent process steps to form the first electrical connection structure and the second electrical connection structure in S27 and S28.

[0128] The plane size of the motherboard of the glass substrate includes any one of 550×650 mm, 680×880 mm, 730×920 mm, 1100×1300 mm and 1300×1500 mm. The plane size of the motherboard of the glass substrate is the size used for display panel manufacturing, wherein the plane size of 550×650 mm is the plane size of the 3rd generation line of the display panel, the plane size of 680×880 mm is the plane size of the 3.5th generation line of the display panel, the plane size of 730×920 mm is the plane size of the 4th generation line or the 4.5th generation line of the display panel, 1100×1300 mm is the plane size of the 5th generation line of the display panel, and 1300×1500 mm is the plane size of the 5.5th generation line of the display panel.

[0129] Optionally, the motherboard of the glass substrate is cut along the cutting path to be cut into N glass substrate sub-boards, where the number N is greater than or equal to 4 and less than or equal to 20.

[0130] A first conductive layer 110 is deposited on the first surface 101 of the motherboard of the glass substrate by a deposition process, and a plurality of first conductive layers 110 are formed by a patterned etching process, and the first conductive layers 110 are used as the lower electrodes of the capacitor. A plurality of first conductive layers 110 are formed on the first surface 101 of the glass substrate, and a cutting path is formed between two adjacent first conductive layers 110.

[0131] The motherboard of the glass substrate is cut along the cutting path to be cut into a plurality of glass substrate sub-boards. In this step, the motherboard of the glass substrate with a large area is cut into a plurality of glass substrate sub-boards with small areas so that the electroplating process can be processed and implemented on the glass substrate sub-boards with small areas. The cut glass substrate sub-boards with small areas can be rectangular, square or circular, and the size can be determined according to the size requirements of the electroplating process production line for the glass substrate sub-boards.

[0132] The reason why the large-area glass substrate motherboard is cut into small-area glass substrate daughter boards and then the electroplating process is implemented is that the required electroplating process is widely used in semiconductor-related wafer fabs, packaging plants, or printed circuit board (PCB) manufacturing-related factories. The substrate sizes based on the production and manufacturing of these factories are basically much smaller than the substrates in the display panel industry. Of course, it is also possible to customize electroplating process equipment suitable for large-area substrates, but this requires the introduction of additional equipment investment and corresponding process development costs. Therefore, after the large-area glass substrate motherboard is cut into small-area glass substrate daughter boards, mature equipment and mature processes are used to continue the process processing to form the first electrical connection structure and the second electrical connection structure until the capacitor is manufactured, which is conducive to controlling the manufacturing cost. After the full process of capacitor manufacturing is completed, the glass substrate daughter board is cut from the cutting path to obtain a single-particle finished capacitor. Specifically, for standard capacitor products with a size of 0.4×0.2 mm, about 4.02 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 550×650 mm, about 6.73 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 680×880 mm, about 7.56 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 730×920 mm, about 16.09 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 1100×1300 mm, and about 21.94 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 1300×1500 mm.

[0133] Fig.11 The following is a method for manufacturing a capacitor chip structure, which discloses the process steps related to the embodiment, referred to as embodiment 3. The manufacturing method includes:

[0134] S31: providing a glass substrate, wherein the glass substrate comprises a first surface and a second surface which are opposite to each other.

[0135] S32: forming a first conductive layer on the first surface of the glass substrate.

[0136] S33: forming a capacitor dielectric layer on a side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covers the side wall of the first conductive layer, and the capacitor dielectric layer is provided with a first through hole, which penetrates the capacitor dielectric layer and exposes a portion of the surface of the first conductive layer.

[0137] S34: A second conductive layer and a third conductive layer are formed on a side of the capacitor dielectric layer away from the first conductive layer; the boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer; the third conductive layer and the second conductive layer are arranged on the same layer; the central portion of the third conductive layer is located in the first through hole and is electrically connected to the first conductive layer, and the edge portion of the third conductive layer is located on a side of the capacitor dielectric layer away from the first conductive layer.

[0138] S35: An insulating layer is formed on a side of the second conductive layer away from the capacitor dielectric layer, the insulating layer also covers the side wall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the side wall of the capacitor dielectric layer and the side wall of the first through hole; the insulating layer is provided with a second through hole and a third through hole penetrating the insulating layer, the second through hole exposes a portion of the surface of the second conductive layer; the third conductive layer and the second conductive layer are insulated by the insulating layer.

[0139] S36: forming a first electrical connection structure, wherein a central portion of the first electrical connection structure is located at the second through hole and is electrically connected to the second conductive layer, and an edge portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate.

[0140] S37: forming a second electrical connection structure, wherein the central portion of the second electrical connection structure is located at the third through hole and is electrically connected to the first conductive layer through the third conductive layer, and the edge portion of the second electrical connection structure is located at the surface of the insulating layer away from the glass substrate.

[0141] Fig.11 The method and method of the capacitor chip structure of the third embodiment shown in FIG. Figure 1 In the first embodiment shown, the manufacturing process steps S31-S33 before forming the second conductive layer 130 on the side of the capacitor dielectric layer 120 away from the first conductive layer 110 are the same, and the difference between the two is the following points:

[0142] 1) The capacitor chip structure also includes a third conductive layer 400, which is arranged on the same layer as the second conductive layer 130; the third conductive layer 400 and the second conductive layer 130 are insulated by an insulating layer 301; the central portion of the third conductive layer 400 is located in the first through hole 300 and is electrically connected to the first conductive layer 110, and the edge portion of the third conductive layer 400 is located on a side of the capacitor dielectric layer 120 away from the first conductive layer 110; the central portion of the second electrical connection structure 303 is located in the third through hole 160, and is electrically connected to the first conductive layer 110 through the third conductive layer 400.

[0143] The third conductive layer 400 and the second conductive layer 130 are disposed in the same layer. This means that the third conductive layer 400 and the second conductive layer 130 are formed by etching the same metal layer.

[0144] 2) The insulating layer 301 includes a passivation layer 135; the passivation layer 135 is located on a side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the passivation layer 135 is also located on a side of the third conductive layer 400 away from the first conductive layer 110; the passivation layer 135 also covers the side wall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110 and the side wall of the capacitor dielectric layer 120 and a portion of the surface of the third conductive layer 400 away from the first conductive layer 110; the third conductive layer 400 and the second conductive layer 130 are insulated by the passivation layer 135.

[0145] 3) The insulating layer 301 further includes a buffer layer 140 . The buffer layer 140 is located on a side of the passivation layer 135 away from the second conductive layer 130 and the third conductive layer 400 . The buffer layer 140 also covers the sidewalls of the passivation layer 135 in the second through hole 150 and the third through hole 160 .

[0146] Figure 12-Figure 17 The schematic cross-sectional view of each relevant process step corresponding to S34-S37 of the manufacturing method of the capacitor chip structure disclosed in the present invention (Example 3) is shown. The relevant processes are described in detail below in conjunction with the accompanying drawings.

[0147] like Fig.12 As shown, a capacitor dielectric layer 120 is formed by a deposition process on a side of the first conductive layer 110 away from the glass substrate 100. The capacitor dielectric layer 120 covers the sidewall of the first conductive layer 110. The capacitor dielectric layer 120 is subjected to pattern etching, and a first through hole 300 is formed in the capacitor dielectric layer 120. The first through hole 300 penetrates the capacitor dielectric layer 120 and exposes a portion of the surface of the first conductive layer 110.

[0148] like Fig.13As shown, a conductive layer is formed by a deposition process on the side of the capacitor dielectric layer 120 away from the first conductive layer 110, and after patterning the conductive layer, a second conductive layer 130 and a third conductive layer 400 are obtained. The boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110, and the third conductive layer 400 and the second conductive layer 130 are arranged in the same layer; the central part of the third conductive layer 400 is located in the first through hole 300 and is electrically connected to the first conductive layer 110, and the edge part of the third conductive layer 400 is located on the side of the capacitor dielectric layer 120 away from the first conductive layer 110. The second conductive layer 130 serves as the upper electrode of the capacitor, and the electrical signal is obtained through the third conductive layer 400 and the second electrical connection structure 303. The second conductive layer 130 and the third conductive layer 400 include any one of Ti, Al, Cu, Cr, Mo, W and TiW, or a stack of two or more thereof. Preferably, the surface material of the second conductive layer 130 and the surface material of the third conductive layer 400 are any one of Ti, Cr and TiW or a stack of two or more thereof, which have good adhesion to other materials, are conducive to good adhesion to the materials attached to their surfaces, and increase reliability.

[0149] An insulating layer 301 is formed on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the insulating layer 301 also covers the side wall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110, the side wall of the capacitor dielectric layer 120, and the side wall of the first through hole 300; the insulating layer 301 is provided with a second through hole 150 and a third through hole 160 penetrating the insulating layer 301, the second through hole 150 exposes a part of the surface of the second conductive layer 130, and the third conductive layer 400 and the second conductive layer 130 are insulated by the insulating layer 301. The insulating layer 301 includes a passivation layer 135, or the insulating layer 301 includes a passivation layer 135 and a buffer layer 140. The insulating layer 301 is formed on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, including the following steps:

[0150] like Fig.14As shown, a passivation layer 135 is formed on the side of the second conductive layer 130 away from the capacitor dielectric layer 120, and the passivation layer 135 is also located on the side of the third conductive layer 400 away from the first conductive layer 110. The passivation layer 135 is patterned and etched to form a sub-through hole 300a and a sub-through hole 300b in the passivation layer 135. Among them, the sub-through hole 300a exposes the second conductive layer 130, and the sub-through hole 300b exposes the first conductive layer 110. The passivation layer 135 also covers the side wall of the second conductive layer 130, the side of the capacitor dielectric layer 120 away from the first conductive layer 110 and the side wall of the capacitor dielectric layer 120, and the partial surface of the third conductive layer 400 away from the first conductive layer 110. The third conductive layer 400 and the second conductive layer 130 are insulated by the passivation layer 135. The passivation layer 135 includes silicon oxide, silicon nitride, or a stacked combination of the two.

[0151] like Fig.15 As shown, a buffer layer 140 is formed on the side of the passivation layer 135 away from the second conductive layer 130 and the third conductive layer 400. The buffer layer 140 is a photosensitive material, specifically a polyimide material. The buffer layer 140 is patterned by a photolithography process so that the buffer layer 140 also covers the sidewalls of the passivation layer 135 in the second through hole 150 and the third through hole 160, and a sub-through hole exposing the first conductive layer 110 and the second conductive layer 130 is formed in the buffer layer 140.

[0152] Fig.16 The figure shows a top view of a capacitor chip structure, and the position of the AA′ section is marked in the figure. Fig.17 is a cross-sectional schematic diagram of a capacitor chip structure. Fig.16 AA' section of the plan view shown.

[0153] Figure 16-Figure 17 It is a detailed process schematic diagram of process steps related to process steps S36-S77 of the method for manufacturing the capacitor chip structure (Example 3) of the present disclosure.

[0154] like Fig.16 and Fig.17 As shown, the first electrical connection structure 302 is formed by electroplating process, the central portion of the first electrical connection structure 302 is located at the second through hole 150 and electrically connected to the second conductive layer 130 , and the edge portion of the first electrical connection structure 302 is located at the surface of the insulating layer 301 away from the glass substrate 100 .

[0155] like Fig.16 and Fig.17As shown, the second electrical connection structure 303 is formed by electroplating process, the central part of the second electrical connection structure 303 is located at the third through hole 160 and is electrically connected to the first conductive layer 110 through the third conductive layer 400, and the edge part of the second electrical connection structure 303 is located at the surface of the insulating layer 301 away from the glass substrate 100.

[0156] The manufacturing method of the capacitor chip structure provided by the embodiment of the present disclosure selects a glass substrate 100 as a substrate, which can provide greater structural strength than a silicon substrate, so that the capacitor chip structure does not need secondary packaging to improve its structural strength, reduces the packaging difficulty, and makes the capacitor chip structure have a better quality factor (Q value). Among them, the capacitor dielectric layer 120 is used to insulate the first conductive layer 110 and the second conductive layer 130. The first conductive layer 110 is used as the first plate of the capacitor to obtain electrical signals through the third conductive layer 400 and the second electrical connection structure 303; the second conductive layer 130 is used as the second plate of the capacitor to obtain electrical signals through the first electrical connection structure 302. The boundary of the second conductive layer 130 is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer 110, so that the surface and sidewall of the non-electrically connected part of the first conductive layer 110 and the second electrical connection structure 303 are covered by the capacitor dielectric layer 120, so as to achieve better electrical isolation between the first conductive layer 110 and the second conductive layer 130. Among them, the insulating layer 301 covers the surface and side walls of the capacitor dielectric layer 120 that are not covered by the second conductive layer 130. The insulating layer 301 also covers the surface and side walls of the non-electrically connected portion of the second conductive layer 130 and the first electrical connection structure 302, as well as the surface of the non-electrically connected portion of the first conductive layer 110 and the second electrical connection structure 303. The capacitor dielectric layer 120 and the insulating layer 301 play the role of insulating packaging for the capacitor chip structure. The first electrical connection structure 302 and the second electrical connection structure 303 are located on the same surface of the capacitor chip structure, which reduces the difficulty of mounting the capacitor chip structure and facilitates electrical connection with other electrical components.

[0157] The passivation layer 135 is provided with a sub-via hole 300a, exposing the second conductive layer 130. The passivation layer 135 is also provided with a sub-via hole 300b, exposing the third conductive layer 400.

[0158] Optionally, in the embodiment of the present disclosure, the glass substrate 100 is a motherboard of a glass substrate.

[0159] The plane size of the motherboard of the glass substrate includes any one of 550×650 mm, 680×880 mm, 730×920 mm, 1100×1300 mm and 1300×1500 mm. The plane size of the motherboard of the glass substrate is the size used for display panel manufacturing, wherein the plane size of 550×650 mm is the plane size of the 3rd generation line of the display panel, the plane size of 680×880 mm is the plane size of the 3.5th generation line of the display panel, the plane size of 730×920 mm is the plane size of the 4th generation line or the 4.5th generation line of the display panel, 1100×1300 mm is the plane size of the 5th generation line of the display panel, and 1300×1500 mm is the plane size of the 5.5th generation line of the display panel.

[0160] Optionally, the motherboard of the glass substrate is cut along the cutting path to be cut into N glass substrate sub-boards, where the number N is greater than or equal to 4 and less than or equal to 20.

[0161] A first conductive layer 110 is deposited on the first surface 101 of the motherboard of the glass substrate by a deposition process, and a plurality of first conductive layers 110 are formed by a patterned etching process, and the first conductive layers 110 are used as the lower electrodes of the capacitor. A plurality of first conductive layers 110 are formed on the first surface 101 of the glass substrate, and a cutting path is formed between two adjacent first conductive layers 110.

[0162] The motherboard of the glass substrate is cut along the cutting path to be cut into a plurality of glass substrate sub-boards. In this step, the motherboard of the glass substrate with a large area is cut into a plurality of glass substrate sub-boards with small areas so that the electroplating process can be processed and implemented on the glass substrate sub-boards with small areas. The cut glass substrate sub-boards with small areas can be rectangular, square or circular, and the size can be determined according to the size requirements of the electroplating process production line for the glass substrate sub-boards.

[0163] The reason why the large-area glass substrate motherboard is cut into small-area glass substrate daughter boards is that the required electroplating process is widely used in semiconductor-related wafer fabs, packaging plants, or printed circuit board (PCB) manufacturing-related factories. The substrate sizes based on these factories are basically much smaller than the substrates in the display panel industry. Of course, electroplating process equipment suitable for large-area substrates can also be customized, but this requires the introduction of additional equipment investment and corresponding process development costs. Therefore, after the large-area glass substrate motherboard is cut into small-area glass substrate daughter boards, mature equipment and mature processes are used to continue the process processing to form the first electrical connection structure and the second electrical connection structure until the capacitor is manufactured, which is conducive to controlling the manufacturing cost. After the full-process capacitor manufacturing process is completed, the glass substrate daughter board is cut from the cutting path to obtain a single-particle finished capacitor. Specifically, for standard capacitor products with a size of 0.4×0.2mm, about 4.02 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 550×650 mm, about 6.73 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 680×880 mm, about 7.56 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 730×920 mm, about 16.09 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 1100×1300 mm, and about 21.94 million capacitor finished particles can be cut from a glass substrate motherboard with a size of 1300×1500 mm.

[0164] The embodiments of the present disclosure also provide a capacitor chip structure, which is prepared by any method for manufacturing a capacitor chip structure described in the implementation of the present disclosure, and has the beneficial effects of any method for manufacturing a capacitor chip structure described in the implementation of the present disclosure, which will not be repeated here.

[0165] It must be noted that the above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be covered by the protection scope of the present disclosure.

Claims

1. A method for manufacturing a capacitor chip structure, characterized in that: include: Providing a glass substrate, the glass substrate comprising a first surface and a second surface disposed opposite to each other; forming a first conductive layer on a first surface of the glass substrate; A capacitor dielectric layer is formed on a side of the first conductive layer away from the glass substrate; the capacitor dielectric layer also covers a side wall of the first conductive layer, and the capacitor dielectric layer is provided with a first through hole, the first through hole penetrates the capacitor dielectric layer and exposes a portion of the surface of the first conductive layer; A second conductive layer is formed on a side of the capacitor dielectric layer away from the first conductive layer; the boundary of the second conductive layer is retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer; An insulating layer is formed on a side of the second conductive layer away from the capacitor dielectric layer, the insulating layer also covers the side wall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the side wall of the capacitor dielectric layer and the side wall of the first through hole; the insulating layer is provided with a second through hole and a third through hole penetrating the insulating layer, the second through hole exposes a part of the surface of the second conductive layer; forming a first electrical connection structure, wherein a central portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate and the second through hole is electrically connected to the second conductive layer; and an edge portion of the first electrical connection structure is located at a surface of the insulating layer away from the glass substrate; A second electrical connection structure is formed, wherein the central portion of the second electrical connection structure is located where the third through hole is electrically connected to the first conductive layer, and the edge portion of the second electrical connection structure is located on a surface of the insulating layer away from the glass substrate.

2. The method for manufacturing a capacitor chip structure according to claim 1, characterized in that: Glass substrates include: providing a motherboard of a glass substrate; Forming a first conductive layer on the first surface of the glass substrate comprises: A plurality of first conductive layers are formed on the first surface of the mother plate of the glass substrate, and a cutting path is formed between two adjacent first conductive layers; Forming a capacitor dielectric layer on a side of the first conductive layer away from the glass substrate comprises: forming a capacitor dielectric layer on a side of the first conductive layer away from the glass substrate motherboard; Before forming the first electrical connection structure, the method further includes: cutting the motherboard of the glass substrate along the cutting path to cut into a plurality of glass substrate sub-boards, wherein the glass substrate sub-boards serve as glass substrates for a single-grain capacitor chip structure.

3. The method for manufacturing a capacitor chip structure according to claim 1 or 2, characterized in that: When a second conductive layer is formed on a side of the capacitor dielectric layer away from the first conductive layer, the method further includes: forming a third conductive layer, wherein the third conductive layer and the second conductive layer are disposed on the same layer; The third conductive layer and the second conductive layer are insulated by the insulating layer; The central portion of the third conductive layer is located at the first through hole and is electrically connected to the first conductive layer, and the edge portion of the third conductive layer is located at a side of the capacitor dielectric layer away from the first conductive layer; A central portion of the second electrical connection structure is located in the third through hole and is electrically connected to the first conductive layer through the third conductive layer.

4. The method for manufacturing a capacitor chip structure according to claim 1 or 2, characterized in that: Forming an insulating layer on a side of the second conductive layer away from the capacitor dielectric layer comprises: A passivation layer is formed on the side of the second conductive layer away from the capacitor dielectric layer, and the passivation layer also covers the sidewall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the sidewall of the capacitor dielectric layer and the sidewall of the first through hole.

5. The method for manufacturing a capacitor chip structure according to claim 4, characterized in that: After forming a passivation layer on a side of the second conductive layer away from the capacitor dielectric layer, the method further comprises: A buffer layer is formed on a side of the passivation layer away from the second conductive layer, and the buffer layer also covers the sidewalls of the passivation layer in the second through hole and the third through hole.

6. The method for manufacturing a capacitor chip structure according to claim 3, characterized in that: Forming an insulating layer on a side of the second conductive layer away from the capacitor dielectric layer comprises: forming a passivation layer on a side of the second conductive layer away from the capacitor dielectric layer, the passivation layer also being located on a side of the third conductive layer away from the first conductive layer; The passivation layer also covers the side wall of the second conductive layer, the side of the capacitor dielectric layer away from the first conductive layer, the side wall of the capacitor dielectric layer, and a portion of the surface of the third conductive layer away from the first conductive layer; The third conductive layer and the second conductive layer are insulated by the passivation layer.

7. The method for manufacturing a capacitor chip structure according to claim 6, characterized in that: After forming a passivation layer on a side of the second conductive layer away from the capacitor dielectric layer, the method further comprises: A buffer layer is formed on a side of the passivation layer away from the second conductive layer and the third conductive layer, and the buffer layer also covers the sidewalls of the passivation layer in the second through hole and the third through hole.

8. The method for manufacturing a capacitor chip structure according to claim 1 or 2, characterized in that: The capacitor chip structure comprises two oppositely disposed first long sides and two oppositely disposed first short sides in a cross-sectional shape parallel to the first surface, the first long sides and the first short sides are arranged perpendicularly, and the length of the first long side is greater than the length of the first short side; The second through hole is located at the first end of the capacitor chip structure, the third through hole is located at the second end of the capacitor chip structure, and the direction in which the first end of the capacitor chip structure points to the second end of the capacitor chip structure is parallel to the first long side.

9. The method for manufacturing a capacitor chip structure according to claim 8, characterized in that: Forming a first electrical connection structure includes: forming a fourth conductive layer in the second through hole and on a portion of the surface of the insulating layer away from the glass substrate; A first pad is formed on a side of the fourth conductive layer away from the insulating layer.

10. The method for manufacturing a capacitor chip structure according to claim 9, characterized in that: Forming a first pad on a side of the fourth conductive layer away from the insulating layer comprises: A first pad formed on a side of the fourth conductive layer away from the insulating layer, the cross-sectional pattern of which on the first surface includes two oppositely disposed second long sides and two oppositely disposed second short sides; The second long side is arranged in parallel with the first short side, the second short side is arranged in parallel with the first long side, and the length of the second long side is greater than the length of the second short side; The length of the second short side is less than one third of the length of the first long side.

11. The method for manufacturing a capacitor chip structure according to claim 10, characterized in that: The length of the second short side is greater than or equal to 10% of the length of the first long side and less than or equal to 30% of the length of the first long side; And / or, the length of the second long side is greater than or equal to 40% of the length of the first short side, and less than or equal to 90% of the length of the first short side.

12. The method for manufacturing a capacitor chip structure according to claim 10, characterized in that: On one side of the first end of the capacitor chip structure, a distance between the second long side and the first short side close to the first end of the capacitor chip structure is greater than or equal to 15 microns and less than or equal to 40 microns; And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the second short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

13. The method for manufacturing a capacitor chip structure according to claim 8, characterized in that: Forming a second electrical connection structure includes: forming a fifth conductive layer in the third through hole and on a portion of the surface of the insulating layer away from the glass substrate; A second pad is formed on a side of the fifth conductive layer away from the insulating layer.

14. The method for manufacturing a capacitor chip structure according to claim 13, characterized in that: Forming a second pad on a side of the fifth conductive layer away from the insulating layer comprises: A second pad formed on a side of the fifth conductive layer away from the insulating layer, the cross-sectional shape of which on the first surface includes two third long sides and two third short sides that are oppositely disposed; The third long side is arranged in parallel with the first short side, the third short side is arranged in parallel with the first long side, the length of the third long side is greater than the length of the third short side, and the length of the third short side is less than one third of the length of the first long side.

15. The method for manufacturing a capacitor chip structure according to claim 14, characterized in that: The length of the third short side is greater than or equal to 10% of the length of the first long side, and less than or equal to 30% of the length of the first long side; And / or, the length of the third long side is greater than or equal to 40% of the length of the first short side, and less than or equal to 90% of the length of the first short side.

16. The method for manufacturing a capacitor chip structure according to claim 14, characterized in that: On one side of the second end of the capacitor chip structure, a distance between the third long side close to the second end of the capacitor chip structure and the first short side is greater than or equal to 15 microns and less than or equal to 40 microns; And / or, on one side of the first end of the capacitor chip structure, the shortest distance between the third short side and the first long side is greater than or equal to 15 microns and less than or equal to 40 microns.

17. The method for manufacturing a capacitor chip structure according to claim 9, characterized in that: The thickness of the first pad is greater than or equal to 15 micrometers and less than or equal to 60 micrometers.

18. The method for manufacturing a capacitor chip structure according to claim 13, characterized in that: The thickness of the second pad is greater than or equal to 15 micrometers and less than or equal to 60 micrometers.

19. The method for manufacturing a capacitor chip structure according to claim 1 or 2, characterized in that: The value of the boundary of the second conductive layer being retracted toward the center of the capacitor chip structure relative to the boundary of the first conductive layer is greater than or equal to 3 micrometers.

20. The method for manufacturing a capacitor chip structure according to claim 2, characterized in that: The plane size of the mother plate of the glass substrate includes any one of 550×650 mm, 680×880 mm, 730×920 mm, 1100×1300 mm and 1300×1500 mm.

21. The method for manufacturing a capacitor chip structure according to claim 20, characterized in that: The motherboard of the glass substrate is cut from the cutting road to be cut into a plurality of glass substrate daughter boards, comprising: The mother plate of the glass substrate is cut along the cutting road to be cut into N glass substrate sub-plates, where the number N is greater than or equal to 4 and less than or equal to 20.

22. A capacitor chip structure, characterized in that: The capacitor chip structure is prepared by the manufacturing method of any one of claims 1-21.

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