Method for forming self-aligned multiple patterns and semiconductor device

Abstract

The invention discloses a self-aligned multiple pattern forming method and a semiconductor device, and relates to the field of semiconductors. The forming method of the self-aligned multiple patterns comprises the following steps: providing a semiconductor substrate with a target layer, and forming a mandrel layer and a sacrificial layer on the target layer; etching the mandrel layer and the sacrificial layer to form a mandrel mask pattern; deposition is carried out on the target layer and the mandrel mask pattern, a first side wall layer, a second side wall layer and a third side wall layer are formed in sequence, and gaps of the second side wall layer are filled with the third side wall layer; removing the second side wall layer and the third side wall layer in the horizontal direction to expose the top surface of the first side wall layer; removing the exposed second side wall layer; removing the first side wall layer in the horizontal direction to expose the sacrificial layer; removing the exposed sacrificial layer and the core shaft layer; and etching the target layer, and forming a predetermined pattern on the target layer. The problem that a current self-alignment dual process is difficult to meet the small-size requirement is solved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a method for forming self-aligned multiple patterns and a semiconductor device. Background Art

[0002] The manufacture of semiconductor devices usually requires a series of process flows. The process includes multiple steps such as deposition, lithography, and etching. Each step will affect the characteristic size and morphology of each device on the semiconductor chip, thereby affecting the device performance. However, with the development of semiconductor technology, the requirements for characteristic size are getting higher and higher. When the semiconductor process enters 14nm and below, the critical size and spacing of semiconductor logic devices using FinFET technology have been reduced to below 20nm and 48nm respectively. Due to the limitations of 193nm lithography technology, single lithography is difficult to achieve. The industry usually uses double patterning process to achieve smaller size processes. Double patterning process generally includes self-aligned double patterning process, secondary etching double patterning process and single etching double patterning process. Among them, the self-aligned double patterning process is widely used in the manufacture of various semiconductor devices due to its excellent line width and spacing control effect, and on this basis, the self-aligned quadruple patterning process has been derived.

[0003] However, the self-aligned double process in the related art can only realize a 1 / 2 size lithography pattern, and it is difficult to further reduce the minimum size to meet the requirements of higher density semiconductor integrated circuits. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a method for forming a self-aligned multiple pattern and a semiconductor device, which can solve the problem that the current self-aligned double process is difficult to meet the small size requirements.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] The present application provides a method for forming a self-aligned multiple pattern, comprising the following steps:

[0007] Providing a semiconductor substrate having a target layer, and forming a mandrel layer and a sacrificial layer stacked on the target layer;

[0008] etching the mandrel layer and the sacrificial layer to form a plurality of mandrel mask patterns;

[0009] Deposition is performed on the target layer and each of the mandrel mask patterns to sequentially form a first spacer layer, a second spacer layer and a third spacer layer, wherein the third spacer layer fills the gap of the second spacer layer;

[0010] Removing the second spacer layer and the third spacer layer in a horizontal direction to expose a top surface of the first spacer layer;

[0011] removing the exposed second sidewall layer;

[0012] Removing the first spacer layer in a horizontal direction to expose the sacrificial layer;

[0013] removing the exposed sacrificial layer and the mandrel layer below the sacrificial layer;

[0014] The target layer is etched using the remaining first spacer layer and the third spacer layer as masks to form a predetermined pattern on the target layer.

[0015] An embodiment of the present application also provides a semiconductor device, including a structure manufactured by the above-mentioned self-aligned multiple pattern forming method.

[0016] The embodiments of the present application can effectively alleviate the problems of low efficiency in size reduction of the self-aligned double process and complicated technical steps and high cost of the self-aligned quadruple process. Its critical dimensions can be further reduced compared with the self-aligned double patterning process under the same lithography conditions. At the same time, its process steps are less than those of the self-aligned quadruple process, thereby improving production efficiency and reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a self-aligned double patterning process in the related art;

[0018] Figure 2 A schematic diagram of a self-aligned quadruple patterning process in the related art;

[0019] Figure 3 A specific process flow chart of a self-aligned quadruple pattern in the related art;

[0020] Figure 4 A schematic diagram of a self-aligned multiple patterning process in the related art;

[0021] Figure 5 A schematic diagram of a self-aligned multiple process flow disclosed in an embodiment of the present application;

[0022] Figure 6 This is a specific flow chart of the method for forming self-aligned multiple patterns disclosed in an embodiment of the present application.

[0023] Description of reference numerals:

[0024] 10-semiconductor substrate; 11-target layer;

[0025] 20- a second mask layer;

[0026] 30- mandrel layer;

[0027] 40-sacrificial layer;

[0028] 50-a first mask layer;

[0029] 60-photoresist layer;

[0030] 71 - a first side wall layer; 72 - a second side wall layer; 73 - a third side wall layer. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0033] The wearable device provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0034] In the related art, some self-aligned double patterning processes generally include: 1) mandrel lithography; 2) mandrel etching; 3) atomic layer sidewall deposition; 4) sidewall etching; 5) mandrel removal; 6) pattern transfer using the sidewall as a hard mask, such as Figure 1 shown.

[0035] However, the above self-aligned dual process can only realize a 1 / 2 size photolithography pattern, and it is difficult to further reduce the minimum size to meet the requirements of higher density semiconductor integrated circuits.

[0036] Other self-aligned quadruple patterning processes generally include: 1) first layer mandrel lithography; 2) first layer mandrel etching; 3) first layer atomic layer sidewall deposition; 4) first layer sidewall etching; 5) first layer mandrel removal; 6) second layer mandrel etching using the first layer sidewall as a hard mask; 7) second layer atomic layer sidewall deposition; 8) second layer sidewall etching; 9) second layer mandrel removal; 10) pattern transfer using the second layer sidewall as a hard mask. Figure 2 and Figure 3 shown.

[0037] The above-mentioned self-aligned quadruple patterning process can achieve the transfer of 1 / 4 pattern on the basis of the self-aligned double patterning process. However, its steps require etching-atomic layer deposition-etching-atomic layer deposition-etching, which makes the process more complicated and increases the process cost.

[0038] Some other graphic processes include: 1) mandrel lithography; 2) mandrel etching; 3) two layers of atomic layer sidewall deposition; 4) sidewall etching; 5) atomic layer sidewall deposition layer 1 removal; 6) image transfer using the mandrel layer and atomic layer sidewall deposition layer 2 as hard masks. This process performs two atomic layer depositions in the atomic layer sidewall, and the size that can be reduced is limited. Figure 4 shown.

[0039] Based on the above situation, the present application proposes a new self-aligned multiple process technology in order to solve the problems of the size reduction efficiency of the above-mentioned self-aligned double process technology and the complicated process steps and high cost of the self-aligned quadruple process technology. The key size of the technology is further reduced compared with the self-aligned double patterning process under the same lithography conditions. At the same time, the process steps are less than the self-aligned quadruple process, which can improve production efficiency and reduce manufacturing costs.

[0040] The present application discloses a method for forming a self-aligned multiple pattern, such as Figure 5 and Figure 6 As shown, the disclosed forming method comprises the following steps:

[0041] S100, providing a semiconductor substrate 10 having a target layer 11, and forming a stacked mandrel layer 30 and a sacrificial layer 40 on the target layer 11. Specifically, the mandrel layer 30 may be located on the surface of the target layer 11, and the sacrificial layer 40 is located on the side of the mandrel layer 30 away from the target layer 11.

[0042] S200 , etching the mandrel layer 30 and the sacrificial layer 40 to form a plurality of mandrel mask patterns.

[0043] Specifically, after forming the stacked mandrel and sacrificial layer 40 on the target layer 11, the mandrel layer 30 and the sacrificial layer 40 are photoetched to form a patterned photolithography layer, thereby forming a plurality of mandrel mask patterns. A photoresist layer 60 may be provided on the surface of the sacrificial layer 40 facing away from the mandrel layer 30 to facilitate the photolithography process.

[0044] Exemplarily, a plurality of mandrel mask patterns are arranged on the top surface of the target layer 11 , and each two adjacent mandrel mask patterns are spaced apart.

[0045] In addition, during the etching process of the mandrel layer 30 , it is necessary to ensure that the sacrificial layer 40 has a sufficient thickness to ensure the normal progress of the subsequent deposition process.

[0046] S300 , depositing on the target layer 11 and each mandrel mask pattern to sequentially form a first spacer layer 71 , a second spacer layer 72 and a third spacer layer 73 , wherein the third spacer layer 73 fills the gap of the second spacer layer 72 .

[0047] Specifically, atomic layer deposition is performed on the top surface of the target layer 11 and the top surface of the side of each mandrel mask pattern to form a first spacer layer 71, and the target layer 11 and each mandrel mask pattern are covered by the first spacer layer 71. It should be noted here that, since two adjacent mandrel mask patterns are arranged at intervals, when the first spacer layer 71 is deposited on the surface of each mandrel mask pattern, a certain gap is formed between the first spacer layers 71 on the outer sides of each of the two adjacent mandrel mask patterns.

[0048] Then, atomic layer deposition is performed on each surface of the first spacer layer 71 to form a second spacer layer 72 on the surface of the first spacer layer 71. It should be noted that the second spacer layer 72 covers the first spacer layer 71, and there is also a certain gap between the second spacer layers 72 on the surface of the first spacer layer 71 outside each of two adjacent mandrel mask patterns.

[0049] Then, atomic layer deposition is performed on each surface of the second spacer layer 72 to form a third spacer layer 73 on the surface of the second spacer layer 72 . Meanwhile, the gaps in the second spacer layer 72 are filled by the third spacer layer 73 .

[0050] In some embodiments, the first sidewall layer 71 covers the sidewall and top of the core axis mask pattern, the second sidewall layer 72 covers the sidewall and top of the first sidewall layer 71, the second sidewall layer 72 has a gap between two adjacent core axis mask patterns, the third sidewall layer 73 covers the top of the second sidewall layer 72, and the third sidewall layer 73 fills the gap.

[0051] In some embodiments, the materials of the first spacer 71 , the second spacer 72 and the third spacer 73 are different; or, the materials of the first spacer 71 and the second spacer 72 are different, and the materials of the first spacer 71 and the third spacer 73 are the same.

[0052] Furthermore, the first spacer layer 71 has a high etching selectivity ratio with respect to the second spacer layer 72 , and the third spacer layer 73 has a high etching selectivity ratio with respect to the second spacer layer 72 .

[0053] Exemplarily, the first side wall layer 71, the second side wall layer 72 and the third side wall layer 73 are all atomic deposition layers, and the materials of the three can be atomic layer deposited silicon oxide (e.g., SiO2), silicon nitride (SiN) and atomic layer deposited silicon oxide (e.g., SiO2), respectively. The two materials (i.e., SiO2 and SiN) have mature atomic layer deposition processes and can achieve high selectivity etching with each other.

[0054] In addition, the sacrificial layer 40 has a high etching selectivity relative to the first spacer layer 71 and the third spacer layer 73 ; during the process of etching the sacrificial layer 40 and the mandrel layer 30 , the sacrificial layer 40 may also have a high etching selectivity relative to the mandrel layer 30 .

[0055] S400 , removing the second spacer layer 72 and the third spacer layer 73 in a horizontal direction to expose a top surface of the first spacer layer 71 .

[0056] Specifically, the top of the third side wall layer 73 and the top of the second side wall layer 72 can be etched away in the horizontal direction, and the horizontal height position can be flush with the position of the top surface of the first side wall layer 71. In this way, after the top of the third side wall layer 73 and the top of the second side wall layer 72 are etched away, the top surface of the first side wall layer 71 is exposed.

[0057] S500 , removing the exposed second spacer layer 72 .

[0058] Specifically, the exposed second spacer layer 72 may be etched away along the vertical direction, so as to expose the top surface and the side surface of the first spacer layer 71 .

[0059] Exemplarily, the sacrificial layer 40 is etched vertically downwards by an etching process having an ultra-high selectivity ratio to the first spacer layer 71 and the second spacer layer 72 .

[0060] Among them, the etching process can use CH3F as the main etching gas, which can achieve a selectivity of SiN to SiO2 of more than 1:20.

[0061] S600 , removing the first spacer layer 71 in the horizontal direction to expose the sacrificial layer 40 .

[0062] Specifically, the top of the first spacer layer 71 and a portion of the top of the third spacer layer 73 may be etched away in the horizontal direction, and the sacrificial layer 40 may be exposed by removing the top of the first spacer layer 71 .

[0063] S700 , removing the exposed sacrificial layer 40 and the mandrel layer 30 under the sacrificial layer 40 .

[0064] Specifically, the exposed sacrificial layer 40 and the mandrel layer 30 located below the sacrificial layer 40 may be etched away in the vertical direction. In addition, in this process, the first spacer layer 71 is not etched, but is retained.

[0065] S800 , etching the target layer 11 by using the remaining first spacer layer 71 and the third spacer layer 73 as masks to form a predetermined pattern on the target layer 11 .

[0066] Exemplarily, the second mask layer 20 is etched downward using the remaining first sidewall layer 71 and the third sidewall layer 73 as a mask, the pattern is transferred to the second mask layer 20, and finally the pattern is transferred to the target layer 11, and other film layers outside the target layer 11 are removed by wet etching, dry etching or chemical mechanical polishing (CMP).

[0067] In addition, the above steps S400, S500, S600 and S800 can be completed by one etching process.

[0068] Based on the above steps, the embodiments of the present application can effectively alleviate the problems of low efficiency of size reduction of the self-aligned double process and complicated technical steps and high cost of the self-aligned quadruple process. Its critical size can be further reduced compared with the self-aligned double patterning process under the same lithography conditions. At the same time, its process steps are less than those of the self-aligned quadruple process, thereby improving production efficiency and reducing manufacturing costs.

[0069] In some embodiments, before forming the mandrel layer 30 and the sacrificial layer 40 stacked on the target layer 11, the method for forming the self-aligned multiple patterns further includes:

[0070] The second mask layer 20 is formed on the target layer 11 , and the mandrel layer 30 and the sacrificial layer 40 which are stacked are formed on the second mask layer 20 .

[0071] Specifically, the second mask layer 20 is first formed on the surface of the target layer 11 to be etched, and then the mandrel layer 30 is formed on the surface of the second mask layer 20, and the sacrificial layer 40 is formed on the surface of the mandrel layer 30. Exemplarily, the second mask layer 20, the mandrel layer 30 and the sacrificial layer 40 are sequentially deposited on the surface of the target layer 11 to be etched.

[0072] Exemplarily, the second mask layer 20 may have a high etching selectivity ratio with respect to the target layer 11 .

[0073] In addition, after forming the mandrel layer 30 and the sacrificial layer 40 stacked on the target layer 11, the method for forming the self-aligned multiple patterns further includes:

[0074] A first mask layer 50 is formed on the sacrificial layer 40 .

[0075] Specifically, the first mask layer 50 is deposited on the surface of the sacrificial layer 40 facing away from the mandrel layer 30 .

[0076] In addition, a photoresist layer 60 may be provided on the surface of the first mask layer 50 and photolithography may be performed to form a patterned photolithography layer.

[0077] In the implementation of the present application, the first mask layer 50 is etched using the patterned photoresist layer as a mask to form a patterned first mask layer 50; then the sacrificial layer 40 and the mandrel layer 30 are etched downward using the first mask layer 50 as a hard mask. During the etching process of the mandrel layer 30, an etching process with a high selectivity ratio for the sacrificial layer 40 can be selected.

[0078] Among them, the etching process with high selectivity can use O2 as the main etching gas, and the O2 flow rate is selected as 100sccm-300sccm. The auxiliary gas can be selected as SO2 or COS, and the auxiliary gas flow rate is selected as 0-300sccm. The auxiliary gas is selected to obtain a vertical morphology. In addition, the upper electrode power can be selected in the range of 300W-1000W, the lower electrode power can be selected in the range of 0-400W, and the etching pressure is selected as 5-20mT to ensure that the sacrificial layer 40 has sufficient thickness, and the etching finally stops on the second mask layer 20. Among them, the thickness of the sacrificial layer 40 can be 1 / 2 of the original thickness or more.

[0079] In the embodiment of the present application, the materials of the first mask layer 50 , the sacrificial layer 40 and the second mask layer 20 are different.

[0080] The material of the first mask layer 50 may include bottom anti-reflection carbon (Bottom Anti-Reflection Carbon, Barc); the material of the second mask layer 20 may be polysilicon (poly); the material of the sacrificial layer 40 may be silicon oxynitride (SiON). In addition, the material of the mandrel layer 30 may be diamond-like carbon (DLC).

[0081] In some embodiments, the second spacer layer 72 and the third spacer layer 73 are removed in a horizontal direction to expose the top surface of the first spacer layer 71, including:

[0082] The second spacer layer 72 and the third spacer layer 73 are etched by an anisotropic dry etching process to remove the second spacer layer 72 and the third spacer layer 73 in a horizontal direction.

[0083] Among them, in the above-mentioned anisotropic dry etching process, the pressure in the etching process chamber can be selected as 5-30 Torr, the upper electrode power can be selected as 300W-1000W, the main etching gas can be selected as CF4, and the flow rate of the main etching gas can be selected as 50sccm-200sccm.

[0084] In addition, a low bias voltage is selected, wherein the lower electrode power can be selected to be 50W-100W, and the low lower electrode power will produce a low bias voltage; a certain amount of polymer gas (i.e., etching gas) is also selected, specifically including at least one of CHF3 or CH2F2 in the hydrocarbon fluorine gas, and the flow rate range of the etching gas can be 20sccm-40sccm. Compared with using a lower flow rate, using too high a flow rate will reduce the etching speed.

[0085] In the embodiment of the present application, the first spacer layer 71 in the horizontal direction is removed to expose the sacrificial layer 40, including:

[0086] The first spacer layer 71 is etched by an anisotropic dry etching process to remove the first spacer layer 71 in a horizontal direction, thereby exposing the top of the sacrificial layer 40 .

[0087] It should be noted that the anisotropic dry etching process used in this step is substantially the same as the etching process in the above-mentioned step S400. In addition, the specific process parameters can be adjusted according to the actual situation. In the process, a low bias voltage and a certain amount of polymer gas (such as carbon, hydrogen, and fluorine gas) can be used to increase the longitudinal and lateral etching ratios, selectively remove the first sidewall layer 71 in the horizontal direction and retain the first sidewall layer 71 in the vertical direction, so that the sacrificial layer 40 is exposed.

[0088] In some embodiments, in the anisotropic dry etching process, a low bias voltage may be selected, and the low lower electrode power may generate a low bias voltage, wherein the lower electrode power may range from 50 W to 100 W. A certain amount of polymer gas (i.e., etching gas) is also selected, specifically including carbon, hydrogen and fluorine gas, and the flow rate of the etching gas may range from 20 sccm to 40 sccm. Compared with a lower flow rate, using too high a flow rate may reduce the etching speed.

[0089] Based on this, the ratio of horizontal to vertical etching can be increased, and the horizontal etching can be minimized while the vertical etching is achieved, thereby retaining the first sidewall layer 71 in the vertical direction. Exemplarily, the horizontal to vertical ratio can reach 1:30 or more. It should be noted here that since the height of the first sidewall layer 71 in the vertical direction is much higher than the height of the deposition layer in the horizontal direction, when the deposition layer with a thickness in the horizontal direction is removed, a first sidewall layer 71 with a sufficient height can be ensured to remain.

[0090] Similarly, when the first spacer layer 71 in the horizontal direction is removed, the third spacer layer 73 will also lose a certain height accordingly. However, since the third spacer layer 73 has a sufficient vertical and horizontal etching ratio, a sufficient height will eventually remain to support the subsequent steps.

[0091] Based on the above-mentioned method for forming self-aligned multiple patterns, an embodiment of the present application further discloses a semiconductor device, including a structure manufactured by the above-mentioned method for forming self-aligned multiple patterns.

[0092] To sum up, compared with the self-aligned double patterning technology in which one pattern forms two target layers 11, and two groups form three target layers 11, the self-aligned multiple patterning process in the embodiment of the present application is two patterns to form five target layers 11, which is equivalent to one pattern forming 2.5 target layers 11, and has better actual size reduction efficiency, thereby being able to meet the requirements of higher density semiconductor integrated circuits.

[0093] The self-aligned multiple patterning process steps in the embodiment of the present application can be divided into five process steps, namely, deposition, first etching, atomic layer deposition, second etching, and mask removal. Compared with the self-aligned quadruple patterning process technology, namely, deposition, first etching, first atomic layer deposition, second etching, second atomic layer deposition, third etching, and mask removal, namely, seven process steps, the embodiment of the present application has relatively fewer process steps, thereby improving production efficiency and reducing manufacturing costs.

[0094] It can be seen that the method for forming self-aligned multiple patterns in the embodiment of the present application can achieve the dual effects of using fewer process steps and reducing critical dimensions, which can not only meet process requirements but also improve production efficiency and reduce costs.

[0095] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for forming a self-aligned multiple pattern, characterized in that: The following steps are involved: Providing a semiconductor substrate having a target layer, and forming a mandrel layer and a sacrificial layer stacked on the target layer; etching the mandrel layer and the sacrificial layer to form a plurality of mandrel mask patterns; Deposition is performed on the target layer and each of the mandrel mask patterns to sequentially form a first spacer layer, a second spacer layer and a third spacer layer, wherein the third spacer layer fills the gap of the second spacer layer; Removing the second spacer layer and the third spacer layer in a horizontal direction to expose a top surface of the first spacer layer; removing the exposed second sidewall layer; Removing the first spacer layer in a horizontal direction to expose the sacrificial layer; removing the exposed sacrificial layer and the mandrel layer below the sacrificial layer; The target layer is etched using the remaining first spacer layer and the third spacer layer as masks to form a predetermined pattern on the target layer.

2. The method for forming self-aligned multiple patterns according to claim 1, wherein: Before forming a stacked mandrel layer and a sacrificial layer on the target layer, the forming method further includes: forming a second mask layer on the target layer, and forming a stacked mandrel layer and a sacrificial layer on the second mask layer; or, After forming a stacked mandrel layer and a sacrificial layer on the target layer, the forming method further includes: A first mask layer is formed on the sacrificial layer.

3. The method for forming self-aligned multiple patterns according to claim 2, wherein: The first mask layer, the sacrificial layer and the second mask layer are made of different materials.

4. The method for forming self-aligned multiple patterns according to claim 2 or 3, characterized in that: The second mask layer has a high etching selectivity relative to the target layer; The sacrificial layer has a high etching selectivity ratio relative to the first spacer layer and the third spacer layer; The material of the first mask layer includes bottom anti-reflective carbon material.

5. The method for forming self-aligned multiple patterns according to claim 4, wherein: During etching of the sacrificial layer and the mandrel layer, the sacrificial layer has a high etching selectivity ratio relative to the mandrel layer.

6. The method for forming self-aligned multiple patterns according to claim 1, wherein: The first sidewall layer covers the sidewall and top of the core axis mask pattern, the second sidewall layer covers the sidewall and top of the first sidewall layer, and the second sidewall layer has a gap between two adjacent core axis mask patterns; the third sidewall layer covers the top of the second sidewall layer, and the third sidewall layer fills the gap.

7. The method for forming self-aligned multiple patterns according to claim 1 or 6, characterized in that: The materials of the first spacer layer, the second spacer layer and the third spacer layer are different; Alternatively, the first spacer layer and the second spacer layer are made of different materials, and the first spacer layer and the third spacer layer are made of the same material.

8. The method for forming self-aligned multiple patterns according to claim 7, wherein: The first spacer layer has a high etching selectivity ratio relative to the second spacer layer; The third spacer layer has a high etching selectivity ratio relative to the second spacer layer.

9. The method for forming self-aligned multiple patterns according to claim 1, wherein: The removing the second spacer layer and the third spacer layer in a horizontal direction to expose the top surface of the first spacer layer includes: The second spacer layer and the third spacer layer are etched by an anisotropic dry etching process to remove the second spacer layer and the third spacer layer in a horizontal direction.

10. The method for forming self-aligned multiple patterns according to claim 9, wherein: In the anisotropic dry etching process, the power of the lower electrode ranges from 50W to 100W, the etching gas includes at least one of CHF3 or CH2F2, and the flow rate of the etching gas ranges from 20sccm to 40sccm.

11. The method for forming self-aligned multiple patterns according to claim 9, wherein: In the anisotropic dry etching process, the power of the upper electrode ranges from 300W to 1000W, the main etching gas includes CF4, and the flow rate of the main etching gas ranges from 50sccm to 200sccm.

12. The method for forming self-aligned multiple patterns according to claim 1, wherein: The removing of the first spacer layer in the horizontal direction to expose the sacrificial layer includes: The first spacer layer is etched by an anisotropic dry etching process to remove the first spacer layer in a horizontal direction and expose the top of the sacrificial layer.

13. The method for forming self-aligned multiple patterns according to claim 12, wherein: In the anisotropic dry etching process, the power of the lower electrode is in the range of 50W-100W, the etching gas includes carbon hydrogen fluorine gas, and the flow rate of the etching gas is in the range of 20sccm-40sccm.

14. The method for forming self-aligned multiple patterns according to claim 12, wherein: In the anisotropic dry etching process, the power of the upper electrode ranges from 300W to 1000W, the main etching gas includes CF4, and the flow rate of the main etching gas ranges from 50sccm to 200sccm.

15. A semiconductor device, characterized in that: A structure comprising a self-aligned multiple patterning method as claimed in any one of claims 1 to 14.

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