Transistor and manufacturing method thereof
By introducing a stress control layer into a high electron mobility transistor to control its thickness and stress magnitude, the problem of difficulty in realizing depletion and enhanced transistors in the prior art is solved, reducing process difficulty and achieving flexible adjustment of threshold voltages .
Patent Information
- Application Number
- CN202411032621.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-30
- Publication Date
- 2024-12-17
AI Technical Summary
The prior art is difficult to implement depletion-type and enhanced high-electron mobility transistors in the same structure, and the process is difficult.
The growth of different types of transistors is achieved by sequentially forming the channel layer, barrier layer and stress control layer on the substrate, and adjusting the threshold voltage of the transistor by controlling the thickness and stress magnitude of the stress control layer during the growth process.
实现了在同一结构中生长出不同阈值电压的晶体管,降低了晶体管制作工艺难度,能够根据需要调节阈值电压以获得耗尽型或增强型晶体管。
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Figure CN119153331A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Art
[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor that is widely used in various electrical appliances.
[0003] The related technology provides a transistor structure, which includes a channel layer and a barrier layer stacked in sequence on a substrate, a source and a drain penetrating the barrier layer and connected to the channel layer, and a gate located in the barrier layer and arranged between the source and the drain.
[0004] The above structure is a depletion-mode HEMT. If an enhancement-mode HEMT is to be realized, an additional P-type GaN layer needs to be provided in the above transistor structure, which makes the process difficult. Summary of the invention
[0005] The disclosed embodiment provides a transistor and a method for manufacturing the same transistor, which can realize a depletion-mode HEMT and an enhancement-mode HEMT using the same structure, and the manufacturing process is easy. The technical solution is as follows:
[0006] In one aspect, a method for manufacturing a transistor is provided, the method comprising:
[0007] forming a channel layer on a substrate;
[0008] forming a barrier layer on the channel layer;
[0009] Fabricating a stress regulating layer on the barrier layer, wherein the stress and thickness of the stress regulating layer applied during the growth process are related to the threshold voltage of the transistor;
[0010] Manufacturing a source electrode and a drain electrode, wherein the source electrode sequentially penetrates the stress regulation layer and the barrier layer and contacts the channel layer, and the drain electrode sequentially penetrates the stress regulation layer and the barrier layer and contacts the channel layer;
[0011] A gate is manufactured, wherein the gate is located in the stress regulating layer and between the source and the drain.
[0012] Optionally, the stress regulating layer is a silicon nitride stress regulating layer;
[0013] Producing a stress regulating layer on the barrier layer, comprising:
[0014] In the process of manufacturing the stress regulating layer by adopting the PECVD process, the stress applied by the stress regulating layer during the growth process is controlled by controlling the frequency of the PECVD equipment and the ratio of Si to N.
[0015] Alternatively, forming a stress regulating layer on the barrier layer comprises:
[0016] In the process of manufacturing the stress regulating layer by using the LPCVD process, the stress applied by the stress regulating layer during the growth process is controlled by controlling the ratio of Si and N.
[0017] Optionally, when the frequency of the PECVD device is low frequency, the stress applied by the stress regulating layer during the growth process is compressive stress; when the frequency of the PECVD device is high frequency, the stress applied by the stress regulating layer during the growth process is tensile stress;
[0018] As the ratio of Si to N increases, the tensile stress applied by the stress regulation layer during the growth process increases. As the ratio of Si to N decreases, the compressive stress applied by the stress regulation layer during the growth process increases.
[0019] Optionally, the method further comprises:
[0020] Before manufacturing the stress regulating layer, determining the thickness of the stress regulating layer based on the target threshold voltage of the transistor;
[0021] The stress applied by the stress regulating layer during the growth process is determined based on the target threshold voltage of the transistor and the thickness of the stress regulating layer.
[0022] Optionally, the thickness of the stress regulation layer is in the range of 20 to 80 nm.
[0023] Optionally, the thickness of the stress regulating layer is negatively correlated with the threshold voltage of the transistor.
[0024] Optionally, when the stress regulating layer applies tensile stress during the growth process, the magnitude of the stress applied by the stress regulating layer during the growth process is negatively correlated with the magnitude of the threshold voltage of the transistor;
[0025] In the case where the stress regulating layer applies compressive stress during the growth process, the magnitude of the stress applied by the stress regulating layer during the growth process is positively correlated with the magnitude of the threshold voltage of the transistor.
[0026] In another aspect, a transistor is provided, the transistor comprising:
[0027] A substrate, a channel layer, a barrier layer and a stress regulation layer sequentially stacked on the substrate;
[0028] a source electrode and a drain electrode, wherein the source electrode sequentially penetrates the stress regulation layer and the barrier layer and contacts the channel layer, and the drain electrode sequentially penetrates the stress regulation layer and the barrier layer and contacts the channel layer;
[0029] The gate is located in the stress regulating layer and between the source and the drain.
[0030] Optionally, the material of the stress regulating layer is Si x N, where x ranges from 1.2 to 5.
[0031] Optionally, the tensile stress of the stress regulating layer is 0 to 320 MPa.
[0032] Optionally, the compressive stress of the stress regulating layer is 0 to 800 MPa;
[0033] Alternatively, the compressive stress of the stress regulating layer is greater than or equal to 30 GPa.
[0034] Optionally, the thickness of the stress regulation layer is in the range of 20 to 80 nm.
[0035] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0036] In the disclosed embodiment, a channel layer, a barrier layer, and a stress regulating layer are sequentially formed on the substrate, wherein the stress magnitude and thickness magnitude of the stress regulating layer applied during the growth process are related to the threshold voltage magnitude of the transistor, that is, the transistor can adjust the stress magnitude and thickness magnitude of the stress regulating layer applied during the growth process as needed, thereby obtaining a transistor with a target threshold voltage. Therefore, this method can use the same structure to grow and produce transistors with different threshold voltages, and can obtain both depletion-type transistors and enhancement-type transistors through threshold voltage adjustment, thereby reducing the difficulty of transistor manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0038] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0039] Figure 2 A schematic diagram of the structure of another transistor provided in an embodiment of the present disclosure;
[0040] Figure 3is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure;
[0041] Figure 4 is a flow chart of another method for manufacturing a transistor provided by an embodiment of the present disclosure;
[0042] Figure 5 This is a schematic diagram comparing threshold voltages of a 40nm stress regulation layer under different stresses provided by an embodiment of the present disclosure;
[0043] Figure 6 is a schematic diagram comparing the threshold voltage ranges of the stress regulation layers of 20, 40, 60 and 80 nm provided in the embodiments of the present disclosure;
[0044] Figure 7 is a schematic diagram of changing the device type by stress according to an embodiment of the present disclosure;
[0045] Figure 8 It is a schematic diagram of changing the device type through stress provided by an embodiment of the present disclosure.
[0046] The reference numerals are as follows:
[0047] 100: substrate; 101: channel layer; 102: barrier layer; 103: stress regulation layer; 104: source; 105: drain; 106: gate; 107: nucleation layer; 108: buffer layer; 109: interlayer insulation layer. DETAILED DESCRIPTION
[0048] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0049] Figure 1 A schematic diagram of a transistor structure provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a substrate 100 , a channel layer 101 , a barrier layer 102 , a stress regulating layer 103 , a source 104 , a drain 105 and a gate 106 .
[0050] Among them, the channel layer 101, the barrier layer 102 and the stress regulation layer 103 are stacked on the substrate 100 in sequence, the source electrode 104 penetrates the stress regulation layer 103 and the barrier layer 102 in sequence and contacts the channel layer 101, the drain electrode 105 penetrates the stress regulation layer 103 and the barrier layer 102 in sequence and contacts the channel layer 101, the gate electrode 106 is located in the stress regulation layer 103, and the gate electrode 106 is located between the source electrode 104 and the drain electrode 105.
[0051] In the disclosed embodiment, a channel layer, a barrier layer, and a stress regulating layer are sequentially formed on the substrate, wherein the stress magnitude and thickness magnitude of the stress regulating layer applied during the growth process are related to the threshold voltage magnitude of the transistor, that is, the transistor can adjust the stress magnitude and thickness magnitude of the stress regulating layer applied during the growth process as needed, thereby obtaining a transistor with a target threshold voltage. Therefore, this method can use the same structure to grow and produce transistors with different threshold voltages, and can obtain both depletion-type transistors and enhancement-type transistors through threshold voltage adjustment, thereby reducing the difficulty of transistor manufacturing process.
[0052] The stress and thickness of the stress regulating layer 103 applied during the growth process are related to the threshold voltage of the transistor.
[0053] In the embodiment of the present disclosure, the substrate 100 may be a Si substrate, a SiC substrate, a sapphire substrate, or the like.
[0054] In the embodiment of the present disclosure, the channel layer 101 may be a non-doped GaN channel layer.
[0055] The thickness of the channel layer 101 may be 1-5 μm.
[0056] Exemplarily, the thickness of the channel layer 101 is 3 μm.
[0057] In the embodiment of the present disclosure, the barrier layer 102 may be Al x Ga 1-x N barrier layer, the barrier layer 102 and the channel layer 101 form a two-dimensional electron gas (2DEG), wherein the value of x is 0.1-0.3.
[0058] The barrier layer 102 may have a thickness of 3-30 nm.
[0059] Exemplarily, the thickness of the barrier layer 102 is 20 nm.
[0060] In the disclosed embodiment, the thickness of the stress regulation layer 103 is in the range of 20 to 80 nm.
[0061] In this implementation, by using the stress regulating layer 103 within the above thickness range, transistors with various threshold voltages can be realized by adjusting the stress.
[0062] Exemplarily, the thickness of the stress regulation layer 103 may be 20, 40, 60 or 80 nm.
[0063] The above thicknesses can be used to realize transistors with various threshold voltages, and the above thicknesses are selected as options to facilitate determination of the corresponding relationship among thickness, stress and threshold voltage.
[0064] In the embodiment of the present disclosure, the thickness of the stress regulating layer 103 is negatively correlated with the threshold voltage of the transistor. That is, the greater the thickness of the stress regulating layer 103, the smaller the threshold voltage of the transistor.
[0065] In the embodiment of the present disclosure, when the stress regulating layer 103 applies tensile stress during the growth process, the magnitude of the stress (magnitude of the tensile stress) applied by the stress regulating layer 103 during the growth process is negatively correlated with the magnitude of the threshold voltage of the transistor;
[0066] When the stress regulating layer 103 applies compressive stress during the growth process, the magnitude of the stress (magnitude of the compressive stress) applied by the stress regulating layer 103 during the growth process is positively correlated with the magnitude of the threshold voltage of the transistor.
[0067] In an implementation of the present disclosure, based on the above relationship, after determining the target threshold voltage, the target threshold voltage can be achieved by adjusting the thickness and the stress magnitude.
[0068] In another implementation of the present disclosure, before manufacturing a transistor, the corresponding relationship between the thickness of the stress regulation layer 103, the stress of the stress regulation layer 103 and the threshold voltage of the transistor can be determined through experiments. In subsequent manufacturing, the thickness can be determined first based on the target threshold voltage, and then the stress can be determined.
[0069] In the embodiment of the present disclosure, the material of the stress regulating layer 103 is Si x N, where x ranges from 1 to 5.
[0070] In the embodiment of the present disclosure, the stress regulation layer 103 can be manufactured by using a plasma enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process.
[0071] In the process of manufacturing the stress regulating layer 103 by using the PECVD process, the stress applied by the stress regulating layer 103 during the growth process is controlled by controlling the frequency of the PECVD equipment and the ratio of Si to N.
[0072] In the process of manufacturing the stress regulating layer 103 by using the LPCVD process, the stress applied by the stress regulating layer 103 during the growth process is controlled by controlling the ratio of Si and N.
[0073] Taking the LPCVD process as an example, when Si:N=5:1, the stress is 100Mpa, and when Si:N=1:1, the stress is 1000Mpa.
[0074] Exemplarily, the value of x is 1.2 to 5.
[0075] In this implementation, when x takes a value within the above range, a stress regulation effect can be achieved, and the stress regulation effect can change the threshold voltage of the transistor within a required range.
[0076] In the embodiment of the present disclosure, by controlling the frequency of the device and / or the ratio of Si and N, the silicon nitride composition and the size of the optical band gap can be changed, thereby adjusting the stress applied by the stress regulation layer 103 during the growth process, and the process is convenient and easy to implement.
[0077] In the embodiment of the present disclosure, the PECVD equipment can adjust the frequency, including low frequency (LF) and high frequency (HF).
[0078] In the embodiment of the present disclosure, when the frequency of the PECVD device is low frequency, the stress applied by the stress regulating layer 103 during the growth process is compressive stress; when the frequency of the PECVD device is high frequency, the stress applied by the stress regulating layer 103 during the growth process is tensile stress;
[0079] As the ratio of Si to N increases, the tensile stress applied by the stress regulation layer 103 during the growth process increases. As the ratio of Si to N decreases, the compressive stress applied by the stress regulation layer 103 during the growth process increases.
[0080] In an implementation of the present disclosure, based on the above relationship, after the target stress is determined, the target stress can be achieved by adjusting the frequency and / or the ratio of Si to N.
[0081] In another implementation of the present disclosure, before manufacturing a transistor, the relationship between the frequency of the device and / or the ratio of Si to N and the stress magnitude can be determined through experiments, and the frequency and / or the ratio of Si to N can be determined based on the target stress during subsequent manufacturing.
[0082] During the experiment, the stress of the stress regulating layer can be measured by mechanical method, interference method, diffraction method, etc. Among them, the mechanical method and interference method indirectly infer the stress by measuring the bending degree of the substrate, while the diffraction method obtains stress information by measuring the change of the lattice constant of the film. In addition, the X-ray diffraction method can also characterize the internal stress.
[0083] Exemplarily, the tensile stress of the stress regulating layer 103 is 0 to 320 MPa.
[0084] For example, the tensile stress of the stress regulating layer 103 is 0 to 100 MPa.
[0085] In this implementation, the transistor type is a normally-on device by applying tensile stress of several hundred MPa.
[0086] Exemplarily, the compressive stress of the stress regulation layer 103 is 0 to 800 MPa.
[0087] For example, the compressive stress of the stress regulating layer 103 is 0 to 100 MPa.
[0088] In this implementation, by applying a compressive stress of several hundred MPa, the transistor type is made into a normally-on device and is easier to turn off.
[0089] Exemplarily, the compressive stress of the stress regulation layer 103 is greater than or equal to 30 GPa.
[0090] Under this compressive stress, the transistor structure provided by the embodiment of the present disclosure can achieve a positive threshold voltage, that is, the device type is an enhancement type transistor.
[0091] In the embodiment of the present disclosure, the source electrode 104 and the drain electrode 105 may each include a Ti sublayer, an Al sublayer, a Ni sublayer and an Au sublayer stacked in sequence.
[0092] In the embodiment of the present disclosure, the Ti sublayer and the Ni sublayer in the source and the drain are used to improve the adhesion between the sublayers and between the sublayers and the barrier layer, the Al sublayer is used to ensure the conductivity of the electrode, and the Au sublayer is used to protect the other sublayers to prevent the source and the drain from being oxidized or corroded.
[0093] In the source electrode 104 and the drain electrode 105 , the thickness of the Ti sublayer may be 5 to 30 nm, the thickness of the Al sublayer may be 100 to 200 nm, the thickness of the Ni sublayer may be 30 to 80 nm, and the thickness of the Au sublayer may be 30 to 80 nm.
[0094] Exemplarily, in the source 104 and the drain 105 , the thickness of the Ti sublayer is 20 nm, the thickness of the Al sublayer is 120 nm, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.
[0095] In the embodiment of the present disclosure, the gate 106 includes a Ni sublayer and an Au sublayer, wherein the Ni sublayer is used to improve the adhesion between the sublayers, and the Au sublayer is used to protect the other sublayers from being oxidized or corroded.
[0096] In the gate 106 , the thickness of the Ni sub-layer may be 10 to 50 nm, and the thickness of the Au sub-layer may be 10 to 50 nm.
[0097] Exemplarily, in the gate 106 , the thickness of the Ni sub-layer is 40 nm, and the thickness of the Au sub-layer is 50 nm.
[0098] Figure 2 FIG. 1 is a schematic diagram of another transistor structure provided by an embodiment of the present disclosure. Figure 2 As shown, the transistor may further include a nucleation layer 107 and a buffer layer 108 , wherein the nucleation layer 107 and the buffer layer 108 are sequentially stacked between the substrate 100 and the channel layer 101 .
[0099] In the embodiment of the present disclosure, the nucleation layer 107 may be an AlN nucleation layer.
[0100] The thickness of the nucleation layer 107 may be 100-300 nm.
[0101] Exemplarily, the thickness of the nucleation layer 107 is 200 nm.
[0102] In the embodiment of the present disclosure, the buffer layer 108 may be a GaN buffer layer and / or an AlGaN buffer layer.
[0103] The thickness of the buffer layer 108 is 500-2000 nm.
[0104] Exemplarily, the thickness of the buffer layer 108 is 1000 nm.
[0105] In the embodiment of the present disclosure, if the thickness of the buffer layer is relatively thick, the manufacturing cost will increase. If the thickness of the buffer layer is relatively thin, it will be detrimental to the buffering effect of the buffer layer, and a good growth interface cannot be formed on the surface of the buffer layer, which is detrimental to the growth of subsequent device layers.
[0106] Alternatively, if Figure 2 As shown, the transistor may further include an interlayer insulating layer 109 , wherein the interlayer insulating layer 109 is located between the source and the drain and covers the gate.
[0107] In the embodiment of the present disclosure, the interlayer insulating layer 109 may be a SiN layer, a SiO 2 layer or an Al 2 O 3 layer.
[0108] In the embodiment of the present disclosure, the thickness of the interlayer insulating layer 109 may be 0.1-10 μm.
[0109] Illustratively, the thickness of the interlayer insulating layer 109 is 5 μm.
[0110] Figure 3 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure, which is used to manufacture the transistor described above. Figure 3 The method steps include:
[0111] S11. Fabricating a channel layer on a substrate.
[0112] S12, forming a barrier layer on the channel layer.
[0113] S13, forming a stress regulating layer on the barrier layer, wherein the stress and thickness of the stress regulating layer applied during the growth process are related to the threshold voltage of the transistor.
[0114] S14, manufacturing a source electrode and a drain electrode, wherein the source electrode sequentially penetrates the stress regulation layer and the barrier layer and contacts the channel layer, and the drain electrode sequentially penetrates the stress regulation layer and the barrier layer and contacts the channel layer.
[0115] S15, manufacturing a gate, wherein the gate is located in the stress regulating layer and between the source and the drain.
[0116] In the disclosed embodiment, a channel layer, a barrier layer, and a stress regulating layer are sequentially formed on the substrate, wherein the stress magnitude and thickness magnitude of the stress regulating layer applied during the growth process are related to the threshold voltage magnitude of the transistor, that is, the transistor can adjust the stress magnitude and thickness magnitude of the stress regulating layer applied during the growth process as needed, thereby obtaining a transistor with a target threshold voltage. Therefore, this method can use the same structure to grow and produce transistors with different threshold voltages, and can obtain both depletion-type transistors and enhancement-type transistors through threshold voltage adjustment, thereby reducing the difficulty of transistor manufacturing process.
[0117] Figure 4 is a flow chart of another method for manufacturing a transistor provided by an embodiment of the present disclosure, which is used to manufacture the transistor described above. Figure 4 The method steps include:
[0118] S21. Growing a nucleation layer on the substrate.
[0119] In the embodiment of the present disclosure, the substrate is one of a Si substrate, a SiC substrate, a sapphire substrate and the like.
[0120] In the embodiment of the present disclosure, the nucleation layer 107 may be an AlN nucleation layer.
[0121] The thickness of the nucleation layer 107 may be 100-300 nm.
[0122] Exemplarily, the thickness of the nucleation layer 107 is 200 nm.
[0123] In the embodiments of the present disclosure, high-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as a carrier gas, high-purity NH3 is used as a nitrogen source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources, trimethylindium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethylaluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl)magnesium (CP2Mg) is used as a P-type dopant.
[0124] S22. Growing a buffer layer on the nucleation layer.
[0125] In the embodiment of the present disclosure, the buffer layer 108 may be a GaN buffer layer and / or an AlGaN buffer layer.
[0126] The thickness of the buffer layer 108 is 500-2000 nm.
[0127] Exemplarily, the thickness of the buffer layer 108 is 1000 nm.
[0128] In the embodiment of the present disclosure, if the thickness of the buffer layer is relatively thick, the manufacturing cost will increase. If the thickness of the buffer layer is relatively thin, it will be detrimental to the buffering effect of the buffer layer, and a good growth interface cannot be formed on the surface of the buffer layer, which is detrimental to the growth of subsequent device layers.
[0129] S23 . Growing a channel layer on the buffer layer.
[0130] In the embodiment of the present disclosure, the channel layer 101 may be a non-doped GaN channel layer.
[0131] The thickness of the channel layer 101 may be 1-5 μm.
[0132] Exemplarily, the thickness of the channel layer 101 is 3 μm.
[0133] S24. Growing a barrier layer on the channel layer.
[0134] In the embodiment of the present disclosure, the barrier layer 102 may be Al x Ga 1-x N barrier layer, the barrier layer 102 and the channel layer 101 form a two-dimensional electron gas (2DEG), wherein the value of x is 0.1-0.3.
[0135] The barrier layer 102 may have a thickness of 3-30 nm.
[0136] Exemplarily, the thickness of the barrier layer 102 is 20 nm.
[0137] S25, forming a stress regulating layer on the barrier layer, wherein the stress and thickness of the stress regulating layer applied during the growth process are related to the threshold voltage of the transistor.
[0138] In the embodiment of the present disclosure, the stress regulation layer 103 may be a silicon nitride stress regulation layer.
[0139] In the disclosed embodiment, the thickness of the stress regulation layer 103 is in the range of 20 to 80 nm.
[0140] In this implementation, by using the stress regulating layer 103 within the above thickness range, transistors with various threshold voltages can be realized by adjusting the stress.
[0141] Exemplarily, the thickness of the stress regulation layer 103 may be 20, 40, 60 or 80 nm.
[0142] The above thicknesses can be used to realize transistors with various threshold voltages, and the above thicknesses are selected as options to facilitate determination of the corresponding relationship among thickness, stress and threshold voltage.
[0143] In the embodiment of the present disclosure, the thickness of the stress regulating layer 103 is negatively correlated with the threshold voltage of the transistor. That is, the greater the thickness of the stress regulating layer 103, the smaller the threshold voltage of the transistor.
[0144] In the embodiment of the present disclosure, when the stress regulating layer 103 applies tensile stress during the growth process, the magnitude of the stress applied by the stress regulating layer 103 during the growth process is negatively correlated with the magnitude of the threshold voltage of the transistor;
[0145] When the stress regulating layer 103 applies compressive stress during the growth process, the magnitude of the stress applied by the stress regulating layer 103 during the growth process is positively correlated with the magnitude of the threshold voltage of the transistor.
[0146] In an implementation of the present disclosure, based on the above relationship, after determining the target threshold voltage, the target threshold voltage can be achieved by adjusting the thickness and the stress magnitude.
[0147] In another implementation of the present disclosure, before manufacturing a transistor, the corresponding relationship between the thickness of the stress regulation layer 103, the stress of the stress regulation layer 103 and the threshold voltage of the transistor can be determined through experiments. In subsequent manufacturing, the thickness can be determined first based on the target threshold voltage, and then the stress can be determined.
[0148] Optionally, the method further comprises:
[0149] Before manufacturing the stress regulating layer 103 , determining the thickness of the stress regulating layer 103 based on the target threshold voltage of the transistor;
[0150] The stress applied by the stress regulating layer 103 during the growth process is determined based on the target threshold voltage of the transistor and the thickness of the stress regulating layer 103 .
[0151] In the embodiment of the present disclosure, the stress regulation layer 103 can be manufactured by using a plasma enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process.
[0152] In the process of manufacturing the stress regulating layer 103 by using the PECVD process, the stress applied by the stress regulating layer 103 during the growth process is controlled by controlling the frequency of the PECVD equipment and the ratio of Si to N.
[0153] In the process of manufacturing the stress regulating layer 103 by using the LPCVD process, the stress applied by the stress regulating layer 103 during the growth process is controlled by controlling the ratio of Si and N.
[0154] Taking the LPCVD process as an example, when Si:N=5:1, the stress is 100Mpa, and when Si:N=1:1, the stress is 1000Mpa.
[0155] In the embodiment of the present disclosure, by controlling the frequency of the device and / or the ratio of Si and N, the silicon nitride composition and the size of the optical band gap can be changed, thereby adjusting the stress applied by the stress regulation layer 103 during the growth process, and the process is convenient and easy to implement.
[0156] In the embodiment of the present disclosure, when the frequency of the PECVD device is low frequency, the stress applied by the stress regulating layer 103 during the growth process is compressive stress; when the frequency of the PECVD device is high frequency, the stress applied by the stress regulating layer 103 during the growth process is tensile stress;
[0157] As the ratio of Si to N increases, the tensile stress applied by the stress regulation layer 103 during the growth process increases. As the ratio of Si to N decreases, the compressive stress applied by the stress regulation layer 103 during the growth process increases.
[0158] In an implementation of the present disclosure, based on the above relationship, after the target stress is determined, the target stress can be achieved by adjusting the frequency and / or the ratio of Si to N.
[0159] In another implementation of the present disclosure, before manufacturing a transistor, the relationship between the frequency of the device and / or the ratio of Si to N and the stress magnitude can be determined through experiments, and the frequency and / or the ratio of Si to N can be determined based on the target stress during subsequent manufacturing.
[0160] During the experiment, the stress of the stress regulating layer can be measured by mechanical method, interference method, diffraction method, etc. Among them, the mechanical method and interference method indirectly infer the stress by measuring the bending degree of the substrate, while the diffraction method obtains stress information by measuring the change of the lattice constant of the film. In addition, the X-ray diffraction method can also characterize the internal stress.
[0161] In the disclosed embodiment, the stress regulating layer acts as a field effect control layer to reduce gate leakage and increase gate withstand voltage. The barrier layer is affected by applying internal stress during the growth of the stress regulating layer, thereby achieving the purpose of adjusting the threshold voltage in a small range.
[0162] The application of tensile stress will cause the threshold voltage to be slightly negatively biased, and the application of compressive stress will cause the threshold voltage to be slightly positively biased. The following is an explanation based on the simulation result diagram.
[0163] Figure 5 : This is a schematic diagram of the threshold voltage comparison under different stresses of the 40nm stress regulation layer provided by the embodiment of the present disclosure. The horizontal axis is the threshold voltage, in V; the vertical axis is the current, in A. Different curves represent the application of different stresses. It can be seen that when the current is 1E-7A, the threshold voltage is about -15.8V when no stress is applied, and the threshold voltage decreases by about 1V when a tensile of 100Mpa is applied, and the threshold voltage of the device increases by about 1V when a compressive of 100Mpa is applied.
[0164] Figure 6 This is a schematic diagram comparing the threshold voltage ranges of the stress control layers of 20, 40, 60 and 80 nm provided in the embodiments of the present disclosure. The horizontal axis is stress, in MPa, negative stress represents compressive stress, and positive stress represents tensile stress; the vertical axis is threshold voltage, in V. Figure 6 The simulation shows the overall trend of the threshold voltage within the range of 100Mpa of positive and negative stress. The actual stress regulation range can be much higher than 100Mpa to achieve the regulation of the threshold voltage. It can be seen that changing the thickness of the stress regulation layer can greatly increase or decrease the range of the threshold voltage, and then achieve precise control of the threshold voltage based on stress regulation at the same thickness.
[0165] The disclosed embodiment regulates the threshold voltage by means of the stress of the stress regulating layer. Applying compressive stress can effectively shift the threshold voltage positively. Conventional HEMT devices are normally-on D-mode type (threshold voltage is less than 0). By applying dielectric layer stress, the device type is changed to normally-off E-mode (threshold voltage is greater than 0).
[0166] Figure 7 It is a schematic diagram of changing the device type through stress provided by an embodiment of the present disclosure. Figure 7 The linear coordinates are shown. Figure 8 yes Figure 7 The corresponding log coordinate transfer curve. Figure 7 and Figure 8 In the figure, the horizontal axis is the threshold voltage, unit is V; the vertical axis is the current, unit is A.
[0167] like Figure 7 and Figure 8 As shown, the threshold voltage Vth of the transfer curve when no stress is initially added is <0. When 30 GPa compressive stress is added, it can be seen from the transfer curve that the threshold voltage at this time is greater than 0.
[0168] The generation principle of 2deg is the mixed effect of spontaneous polarization and piezoelectric polarization. This stress is equivalent to regulating the degree of piezoelectric polarization, which can control the concentration of 2deg.
[0169] It should be noted that the above Figures 5 to 8 The SiN thickness and stress are limited. In addition, the thickness and parameters of other film layers in the transistor also have a certain influence on the threshold voltage. The present disclosure does not elaborate on the influence of other film layers, and mainly discusses the SiN thickness and stress.
[0170] Exemplarily, when the stress regulating layer is not stressed, there is an electron concentration under the gate, and the electron gas concentration is uniformly distributed laterally, which is a normally open device. When 100Mpa stress is applied, the electron concentration contour curves upward, and it is still a normally open type, but it is easier to turn off. When 5Gpa stress is applied, there is only a thin layer of electrons, and only a small voltage needs to be applied to the gate to turn it off. When 30Gpa stress is applied, there is no electron concentration under the gate, the threshold voltage becomes positive, and the device type becomes enhanced.
[0171] That is, as the applied stress increases, the two-dimensional electron gas in the channel begins to be gradually depleted, the concentration decreases, and the corresponding threshold voltage gradually shifts positively. When the applied stress reaches 30Gpa, the electron gas is depleted and the channel is pinched off. At this time, when the gate voltage is zero, the device exhibits a non-conducting characteristic, and it turns on again when a positive voltage is applied, that is, it is converted into an E-mode normally-off device.
[0172] S26, manufacturing a gate, wherein the gate is located in the stress regulating layer.
[0173] In the embodiment of the present disclosure, the gate 106 includes a Ni sublayer and an Au sublayer, wherein the Ni sublayer is used to improve the adhesion between the sublayers, and the Au sublayer is used to protect the other sublayers from being oxidized or corroded.
[0174] In the gate 106 , the thickness of the Ni sub-layer may be 10 to 50 nm, and the thickness of the Au sub-layer may be 10 to 50 nm.
[0175] Exemplarily, in the gate 106 , the thickness of the Ni sub-layer is 40 nm, and the thickness of the Au sub-layer is 50 nm.
[0176] S27, making an interlayer insulating layer, wherein the interlayer insulating layer covers the gate.
[0177] In the embodiment of the present disclosure, the interlayer insulating layer 109 may be a SiN layer, a SiO 2 layer or an Al 2 O 3 layer.
[0178] In the embodiment of the present disclosure, the thickness of the interlayer insulating layer 109 may be 0.1-10 μm.
[0179] Illustratively, the thickness of the interlayer insulating layer 109 is 5 μm.
[0180] S28. Make a source and a drain, wherein the source sequentially penetrates the interlayer insulating layer, the barrier layer and the stress regulation layer to contact the channel layer, and the drain sequentially penetrates the interlayer insulating layer, the barrier layer and the stress regulation layer to contact the channel layer.
[0181] Figure 2 The figure shows only a cross-sectional view of the transistor. Figure 2 The portion of the drain electrode extending out of the interlayer insulating layer is not shown in the cross section.
[0182] In the embodiment of the present disclosure, the source electrode 104 and the drain electrode 105 may each include a Ti sublayer, an Al sublayer, a Ni sublayer and an Au sublayer stacked in sequence.
[0183] In the embodiment of the present disclosure, the Ti sublayer and the Ni sublayer in the source and the drain are used to improve the adhesion between the sublayers and between the sublayers and the barrier layer, the Al sublayer is used to ensure the conductivity of the electrode, and the Au sublayer is used to protect the other sublayers to prevent the source and the drain from being oxidized or corroded.
[0184] In the source electrode 104 and the drain electrode 105 , the thickness of the Ti sublayer may be 5 to 30 nm, the thickness of the Al sublayer may be 100 to 200 nm, the thickness of the Ni sublayer may be 30 to 80 nm, and the thickness of the Au sublayer may be 30 to 80 nm.
[0185] Exemplarily, in the source 104 and the drain 105 , the thickness of the Ti sublayer is 20 nm, the thickness of the Al sublayer is 120 nm, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.
[0186] The transistor manufactured by the solution provided in the embodiment of the present disclosure can be a Metal Insulation Semiconductor Field Effect Transistor (MISFET). The threshold voltage can be regulated by controlling the stress of the stress regulation layer 103, and an enhancement transistor can be realized without designing a P-type GaN layer (that is, without using P-GaN gate technology, only the stress regulation layer is adjusted to convert the D-mode into an E-mode type device), thereby realizing a normally-off safety device.
[0187] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A method for manufacturing a transistor, It is characterized in that The method comprises: Fabricating a channel layer (101) on a substrate (100); Fabricating a barrier layer (102) on the channel layer (101); Manufacturing a stress regulating layer (103) on the barrier layer (102), wherein the stress magnitude and thickness of the stress regulating layer (103) applied during the growth process are related to the threshold voltage magnitude of the transistor; A source electrode (104) and a drain electrode (105) are fabricated, wherein the source electrode (104) sequentially penetrates the stress regulating layer (103) and the barrier layer (102) to contact the channel layer (101), and the drain electrode (105) sequentially penetrates the stress regulating layer (103) and the barrier layer (102) to contact the channel layer (101); A gate (106) is manufactured, wherein the gate (106) is located on the stress regulating layer (103) and between the source (104) and the drain (105).
2. The method according to claim 1, It is characterized in that The stress regulating layer (103) is a silicon nitride stress regulating layer; Producing a stress regulating layer (103) on the barrier layer (102), comprising: In the process of manufacturing the stress regulating layer (103) by using the PECVD process, the stress applied by the stress regulating layer (103) during the growth process is controlled by controlling the frequency of the PECVD equipment and the ratio of Si to N; Alternatively, forming a stress regulating layer (103) on the barrier layer (102) comprises: In the process of manufacturing the stress regulating layer (103) by using the LPCVD process, the ratio of Si and N is controlled to control the magnitude of the stress applied by the stress regulating layer (103) during the growth process.
3. The method according to claim 2, It is characterized in that When the frequency of the PECVD device is low frequency, the stress applied by the stress regulating layer (103) during the growth process is compressive stress; when the frequency of the PECVD device is high frequency, the stress applied by the stress regulating layer (103) during the growth process is tensile stress; As the ratio of Si to N increases, the tensile stress applied by the stress regulating layer (103) during the growth process increases, and as the ratio of Si to N decreases, the compressive stress applied by the stress regulating layer (103) during the growth process increases.
4. The method according to any one of claims 1 to 3, It is characterized in that The method further comprises: Before manufacturing the stress regulating layer (103), determining the thickness of the stress regulating layer (103) based on the target threshold voltage of the transistor; Based on the target threshold voltage of the transistor and the thickness of the stress regulating layer (103), the magnitude of the stress applied by the stress regulating layer (103) during the growth process is determined.
5. The method according to any one of claims 1 to 3, It is characterized in that The thickness of the stress regulating layer (103) is negatively correlated with the threshold voltage of the transistor; When the stress regulating layer (103) applies tensile stress during the growth process, the magnitude of the stress applied by the stress regulating layer (103) during the growth process is negatively correlated with the magnitude of the threshold voltage of the transistor; When the stress regulating layer (103) applies compressive stress during the growth process, the magnitude of the stress applied by the stress regulating layer (103) during the growth process is positively correlated with the magnitude of the threshold voltage of the transistor.
6. A transistor, It is characterized in that The transistor comprises: A substrate (100), a channel layer (101), a barrier layer (102) and a stress regulating layer (103) sequentially stacked on the substrate (100); A source electrode (104) and a drain electrode (105), wherein the source electrode (104) sequentially penetrates the stress regulation layer (103) and the barrier layer (102) to contact the channel layer (101), and the drain electrode (105) sequentially penetrates the stress regulation layer (103) and the barrier layer (102) to contact the channel layer (101); The gate (106) is located in the stress regulating layer (103) and between the source (104) and the drain (105).
7. The transistor according to claim 6, It is characterized in that The material of the stress regulating layer (103) is Si x N, where x ranges from 1.2 to 5.
8. The transistor according to claim 6 or 7, It is characterized in that The tensile stress of the stress regulating layer (103) is 0 to 320 MPa.
9. The transistor according to claim 6 or 7, It is characterized in that The compressive stress of the stress regulating layer (103) is 0 to 800 MPa; Alternatively, the compressive stress of the stress regulating layer (103) is greater than or equal to 30 GPa.
10. The transistor according to claim 6 or 7, It is characterized in that The thickness of the stress regulating layer (103) is in the range of 20 to 80 nm.