Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: providing a substrate; sequentially forming a first metal layer and a first mask layer on the substrate, wherein the first metal layer and the first mask layer cover the gate precursor layer and the source-drain region; selectively removing the first mask layer and the first metal layer on the top surface and the side wall of the gate precursor layer, and reserving the first mask layer and the first metal layer on the source and drain regions; forming a second metal layer on the substrate; and enabling the residual first metal layer to react with the silicon material in the source-drain region to form a first metal silicide layer, and enabling the second metal layer to react with the silicon material in the gate precursor layer to form a second metal silicide layer. According to the preparation method, the thickness of the metal silicide of the grid electrode is not limited by the thickness of the metal silicide of the source-drain region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Polysilicon materials are usually used as gates in semiconductor devices. Gate resistance is an important factor affecting the switching speed of semiconductor devices. The resistance of polysilicon is relatively high, and it is gradually difficult to meet the switching speed requirements of the device. In the production process of traditional semiconductor devices, further depositing metal on the surface of polysilicon material and heat treating it to form metal silicide can reduce the gate resistance. However, in the process of forming metal silicide, metal is also deposited on the surface of silicon material in the source and drain regions and simultaneously forms metal silicide, which causes the thickness of the metal silicide in the source and drain regions to be basically the same as the thickness of the metal silicide in the gate. The thickness of the metal silicide on the source and drain regions is relatively limited, which also limits the further increase of the thickness of the metal silicide in the gate. Summary of the invention

[0003] Based on this, it is necessary to provide a method for preparing a semiconductor structure to address the problems in the above background technology, wherein the thickness of the metal silicide of the gate is not limited by the thickness of the metal silicide of the source and drain regions.

[0004] According to some embodiments of the present disclosure, a method for preparing a semiconductor structure is provided, which comprises the following steps:

[0005] Providing a substrate, the substrate comprising an active region and a gate precursor layer disposed on the active region, the active region comprising two source and drain regions respectively located on both sides of the gate precursor layer, and the gate precursor layer and the source and drain regions both having silicon material;

[0006] forming a first metal layer and a first mask layer in sequence on the substrate, wherein the first metal layer and the first mask layer cover the gate precursor layer and the source and drain regions;

[0007] Selectively removing the first mask layer and the first metal layer located on the top surface and the sidewall of the gate precursor layer, and retaining the first mask layer and the first metal layer located on the source and drain regions;

[0008] forming a second metal layer on the substrate;

[0009] The remaining first metal layer and the silicon material in the source and drain regions are reacted to form a first metal silicide layer, and the second metal layer and the silicon material in the gate precursor layer are reacted to form a second metal silicide layer.

[0010] In some embodiments of the present disclosure, the step of selectively removing the first mask layer and the first metal layer includes:

[0011] The first mask layer and the first metal layer are etched using a first plasma, and the etching direction of the first plasma is controlled to be inclined relative to a normal direction of the substrate.

[0012] In some embodiments of the present disclosure, in the process of etching the first mask layer and the first metal layer using the first plasma, the acute angle between the etching direction of the first plasma and the normal direction of the substrate is controlled to be 30°~45°.

[0013] In some embodiments of the present disclosure, after selectively removing the first mask layer and the first metal layer and before forming the second metal layer, the following steps are further included:

[0014] forming a second mask layer on the substrate, wherein the second mask layer covers the gate precursor layer and the first mask layer;

[0015] The second mask layer located on the top surface of the gate precursor layer is selectively removed, and at least a portion of the second mask layer located on the sidewall of the gate precursor layer remains.

[0016] In some embodiments of the present disclosure, the step of selectively removing the second mask layer includes:

[0017] The second mask layer is etched using a second plasma, and the etching direction of the second plasma is controlled to be inclined relative to the normal direction of the substrate, and the acute angle formed between the etching direction of the second plasma and the normal direction of the substrate is greater than the acute angle formed between the etching direction of the first plasma and the normal direction of the substrate.

[0018] In some embodiments of the present disclosure, in the process of etching the second mask layer using the second plasma, the acute angle between the etching direction of the second plasma and the normal direction of the substrate is controlled to be 60°~75°.

[0019] In some embodiments of the present disclosure, the substrate also includes a gate dielectric layer located between the active area and the gate precursor layer, and in the step of forming the second metal silicide layer, the formed second metal silicide layer directly contacts the gate dielectric layer; and / or, the substrate also includes a gate sidewall, and the gate sidewall is arranged on the side wall of the gate precursor layer.

[0020] In some embodiments of the present disclosure, the thickness of the second metal silicide layer is greater than the thickness of the first metal silicide layer; and / or,

[0021] The thickness of the second metal layer is greater than that of the first metal layer.

[0022] In some embodiments of the present disclosure, the step of forming the first metal silicide layer and the second metal silicide layer includes: performing a first heat treatment and a second heat treatment on the substrate, the first metal layer and the second metal layer in sequence, during the first heat treatment, the heat treatment temperature is 250°C~400°C, and the heat treatment time is 30s~60s, and during the second heat treatment, the heat treatment temperature is 450°C~600°C, and the heat treatment time is 10s~60s.

[0023] Furthermore, the present disclosure also provides a semiconductor structure, which includes an active region, a gate dielectric layer and a gate, wherein the gate dielectric layer is disposed between the active region and the gate, the active region includes two source and drain regions respectively located on both sides of the gate, a first metal silicide layer is disposed in the source and drain regions, and a second metal silicide layer is disposed in the gate;

[0024] The thickness of the first metal silicide layer is less than the thickness of the second metal silicide layer, and the second metal silicide layer directly contacts the gate dielectric layer.

[0025] In the method for preparing a semiconductor structure of at least one embodiment of the present disclosure, a first metal layer and a first mask layer are first formed, and then a portion of the first mask layer and the first metal layer are selectively removed, and then a second metal layer is formed. The first metal layer is located on the surface of the source and drain regions, and the second metal layer is located on the surface of the gate precursor layer, and the first metal layer and the second metal layer are prepared separately, so the type and / or thickness of the metal formed on the surface of the source and drain regions and the gate precursor layer may be different. This makes the thickness of the first metal silicide layer and the second metal silicide layer formed subsequently different, that is, the preparation method can achieve a large difference in the thickness of the first metal silicide layer and the second metal silicide layer. Therefore, the preparation method can avoid the limitation of the gate metal silicide thickness existing in the traditional technology.

[0026] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic diagram of the steps of a method for preparing a semiconductor structure;

[0029] Figure 2 is a schematic diagram of a cross-sectional structure of a semiconductor substrate;

[0030] Figure 3 For Figure 2 A schematic diagram of a structure for forming a gate precursor layer based on the structure shown;

[0031] Figure 4 For Figure 3 A schematic diagram of a structure in which source and drain regions are formed on the basis of the structure shown;

[0032] Figure 5 For Figure 4 A schematic diagram of a structure in which a first metal layer and a first mask layer are formed on the basis of the structure shown;

[0033] Figure 6 For Figure 5 A schematic diagram of a structure in which the first metal layer is selectively removed based on the structure shown;

[0034] Figure 7 For Figure 6 A schematic diagram of a structure in which a second mask layer is formed on the basis of the structure shown;

[0035] Figure 8 For Figure 7 A schematic diagram of a structure in which the second mask layer is selectively removed based on the structure shown;

[0036] Fig. 9 For Figure 8 A schematic diagram of a structure in which a second metal layer is formed on the basis of the structure shown;

[0037] Fig.10 For Fig. 9 A schematic diagram of a structure in which a first metal silicide layer and a second metal silicide layer are formed on the basis of the structure shown;

[0038] Fig.11 For Fig.10 Schematic diagram of the structure in which the second metal layer, the second mask layer, the first mask layer and the first metal layer are removed based on the structure shown.

[0039] The reference numerals and their meanings are as follows:

[0040] 100, semiconductor substrate; 101, shallow trench isolation structure; 110, active region; 111, source and drain region; 120, gate precursor layer; 130, gate dielectric layer; 140, gate sidewall; 150, first metal silicide layer; 160, second metal silicide layer; 210, first metal layer; 220, first mask layer; 230, second mask layer; 240, second metal layer. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present invention, a more comprehensive description of the present invention is provided below. The preferred embodiments of the present invention are given herein. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the content of the present invention more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this document pertains. The terms used herein in the specification of this document are only for describing specific embodiments and are not intended to limit this document.

[0043] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to, or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to, or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to other elements or features. It should be understood that the spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used may be interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "a", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Figure 1 Schematic diagram of the steps of a method for preparing a semiconductor structure disclosed in the present invention. Figure 1 As shown, the method for preparing the semiconductor structure includes steps S1 to S5, which are specifically as follows.

[0047] Step S1, providing a substrate, the substrate comprising an active area 110 and a gate precursor layer 120 disposed on the active area 110, the active area 110 comprising two source and drain regions 111 respectively located on both sides of the gate precursor layer 120, and both the gate precursor layer 120 and the source and drain regions 111 contain silicon material.

[0048] Figure 2~Figure 4 The process of providing a substrate in the present disclosure is schematically shown. As some examples of this embodiment, the step of providing a substrate includes: providing a semiconductor substrate 100 including an active region 110 , forming a gate precursor layer 120 on the semiconductor substrate 100 , and forming a source and drain region 111 in the active region 110 .

[0049] in, Figure 2 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor substrate 100. Figure 2 As shown, as some examples of this embodiment, a plurality of shallow trench isolation structures 101 may be provided in the semiconductor substrate 100 , and the shallow trench isolation structures 101 isolate a plurality of active regions 110 in the semiconductor substrate 100 .

[0050] As some examples of this embodiment, the material of the semiconductor substrate 100 may include a semiconductor material, and the semiconductor material may be, for example, one or more of silicon, germanium, a silicon-germanium alloy, gallium nitride, and silicon carbide.

[0051] As some examples of this embodiment, the material of the active region 110 in the semiconductor substrate 100 may be silicon.

[0052] Figure 3 For Figure 2 A schematic diagram of a structure of forming a gate precursor layer 120 based on the structure shown in FIG. Figure 3As shown, the gate precursor layer 120 is disposed on the active region 110 and covers a portion of the active region 110 .

[0053] As some examples of this embodiment, the step of forming the gate precursor layer 120 includes: depositing a silicon material layer covering the semiconductor substrate 100 on the semiconductor substrate 100 , and etching the silicon material layer to form the gate precursor layer 120 .

[0054] In this example, the silicon material layer may be deposited by chemical vapor deposition.

[0055] In this example, the silicon material layer may be etched in an anisotropic manner, such as dry etching.

[0056] In this example, the gate precursor layer 120 is composed of a silicon material. Further, the gate precursor layer 120 may be composed of polysilicon.

[0057] Reference Figure 3 As shown in some examples of this embodiment, the substrate further includes a gate dielectric layer 130 disposed between the active region 110 and the gate precursor layer 120. In this example, the material of the gate dielectric layer 130 can be formed on the semiconductor substrate 100 before forming the gate precursor layer 120. In addition, in the step of etching the silicon material layer, the material of the gate dielectric layer 130 can be etched based on the same mask pattern to form the gate dielectric layer 130.

[0058] As some examples of this embodiment, the material of the gate dielectric layer 130 is an insulating material. Further, the material of the gate dielectric layer 130 is selected from one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0059] Figure 4 For Figure 3 A schematic diagram of a structure in which a source / drain region 111 is formed on the basis of the structure shown in FIG. Figure 4 As shown, as some examples of this embodiment, before forming the source and drain regions 111 , a step of forming a gate spacer 140 on the semiconductor substrate 100 may be further included, and the gate spacer 140 is disposed on the sidewall of the gate precursor layer 120 .

[0060] As some examples of this embodiment, the material of the gate spacer 140 is an insulating material. Further, the material of the gate spacer 140 can be selected from one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0061] Reference Figure 4As shown, gate spacers 140 are disposed on two opposite sidewalls of the gate precursor layer 120. In addition, source and drain regions 111 are formed on the side of the gate spacer 140 away from the gate precursor layer 120. A source and drain region 111 is disposed on both sides of the gate precursor layer 120, and a channel located below the gate precursor layer 120 exists between the two source and drain regions 111.

[0062] As some examples of this embodiment, the step of forming the source and drain regions 111 includes: implanting doping atoms into the region of the active region 110 that is not shielded by the gate precursor layer 120 and annealing to form the source and drain regions 111 .

[0063] In this embodiment, both the gate precursor layer 120 and the source / drain region 111 contain silicon material, and the silicon material is used to participate in the formation of metal silicide in the subsequent preparation process.

[0064] Step S2 , forming a first metal layer 210 and a first mask layer 220 in sequence on the substrate, wherein the first metal layer 210 and the first mask layer 220 cover the gate precursor layer 120 and the source and drain regions 111 .

[0065] Figure 5 For Figure 4 A schematic diagram of a structure in which a first metal layer 210 and a first mask layer 220 are formed on the basis of the structure shown in FIG. Figure 5 As shown, the first metal layer 210 and the first mask layer 220 are sequentially stacked on the substrate, the first metal layer 210 covers the top surface of the gate precursor layer 120 and the source and drain regions 111, and the first metal layer 210 also extends to cover the sidewalls of the gate precursor layer 120. The first mask layer 220 covers the first metal layer 210, and the first mask layer 220 is used to shield the first metal layer 210.

[0066] Reference Figure 5 As shown, in this embodiment, the first metal layer 210 may directly contact the surface of the source and drain regions 111 .

[0067] As some examples of this embodiment, the material of the first metal layer 210 may be selected from materials that can be combined with silicon and form metal silicide. For example, the material of the first metal layer 210 may be selected from at least one of titanium, nickel, platinum and cobalt.

[0068] As some examples of this embodiment, the first metal layer 210 may be formed by chemical vapor deposition or physical vapor deposition.

[0069] As some examples of this embodiment, the thickness of the first metal layer 210 is 10nm-15nm. By forming the first metal layer 210 with this thickness range, a metal silicide with a suitable thickness can be formed in the source and drain regions 111 in subsequent processes to prevent it from penetrating the source and drain regions 111 and causing leakage.

[0070] In some examples, the thickness of the first metal layer 210 may be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm, or the thickness of the first metal layer 210 may be between any two of the above thicknesses.

[0071] In this embodiment, the first mask layer 220 is used to shield the first metal layer 210 to separate the first metal layer 210 thereunder and the second metal layer 240 subsequently prepared thereon.

[0072] As some examples of this embodiment, the material of the first mask layer 220 is different from the material of the first metal layer 210. Further, the material of the first mask layer 220 is selected from an insulating material. For example, the material of the first mask layer 220 can be selected from one of silicon oxide, silicon nitride and silicon oxynitride.

[0073] As some examples of this embodiment, the first mask layer 220 may be formed by chemical vapor deposition.

[0074] As some examples of this embodiment, the thickness of the first mask layer 220 may be 10 nm to 20 nm. By forming the first mask layer 220 with a thickness within this range, the first metal layer 210 can be better protected in subsequent processes.

[0075] In some examples, the thickness of the first mask layer 220 may be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, or 20 nm, or the thickness of the first mask layer 220 may be between any two of the above thicknesses.

[0076] Step S3 , selectively removing the first mask layer 220 and the first metal layer 210 located on the top and sidewalls of the gate precursor layer 120 , and retaining the first mask layer 220 and the first metal layer 210 located on the source and drain regions 111 .

[0077] Figure 6 For Figure 5 A schematic diagram of a structure in which the first metal layer 210 is selectively removed based on the structure shown. Figure 6 As shown, the first metal layer 210 located on the top surface and sidewalls of the gate precursor layer 120 is removed, while the first metal layer 210 located on the source and drain regions 111 is retained.

[0078] In this embodiment, the remaining first metal layer 210 covers the entire source and drain region 111 .

[0079] As some examples of this embodiment, the step of selectively removing the first mask layer 220 and the first metal layer 210 includes: etching the first mask layer 220 and the first metal layer 210 using a first plasma, and controlling the etching direction of the first plasma to be inclined relative to the normal direction of the substrate.

[0080] Reference Figure 6 , Figure 6 The arrow in the figure indicates the direction of the first plasma etching. By controlling the inclination of the etching direction of the first plasma, the first mask layer 220 and the first metal layer 210 located on the top surface and the side wall of the first mask layer 220 can be selectively removed. Moreover, due to the shielding of the gate sidewall 140 and the gate precursor layer 120, at least part of the first mask layer 220 and the first metal layer 210 located on the source and drain region 111 will not be etched and are therefore retained.

[0081] Reference Figure 6 As shown, in this embodiment, the first metal layer 210 located on the sidewall of the gate precursor layer 120 is removed. The main function of removing this part of the first metal layer 210 is to control the thickness of the metal silicide formed subsequently. If this part of the first metal layer 210 is not effectively removed, the thickness of the metal silicide formed subsequently is relatively thick, which is easy to penetrate the source and drain regions 111 and cause leakage.

[0082] Reference Figure 6 As shown in some examples of this embodiment, in the process of using the first plasma to etch the first mask layer 220 and the first metal layer 210, the acute angle α between the etching direction of the first plasma and the normal direction of the substrate is controlled to be 30° to 45°. By controlling the acute angle range, the first metal layer 210 on the source and drain regions 111 can be prevented from being over-etched as much as possible, thereby ensuring that the area of ​​the metal silicide formed subsequently is large.

[0083] In some examples, the acute angle α formed between the etching direction of the first plasma and the normal direction of the substrate is 30°, 32°, 34°, 36°, 38°, 40°, 42°, 44°, or 45°, or the acute angle α formed between the etching direction of the first plasma and the normal direction of the substrate may also be between any two of the above angles.

[0084] Step S4, forming a second metal layer 240 on the substrate.

[0085] Figure 7~Figure 9 For Figure 6Schematic diagram of the process of forming the second metal layer 240 on the basis of the structure shown. As some examples of this embodiment, after the first mask layer 220 and the first metal layer 210 are selectively removed and before the second metal layer 240 is formed, the following steps are also included: forming a second mask layer 230 on the substrate, the second mask layer 230 covering the gate precursor layer 120 and the first mask layer 220; selectively removing the second mask layer 230 located on the top surface of the gate precursor layer 120, and retaining at least a portion of the second mask layer 230 located on the sidewall of the gate precursor layer 120.

[0086] in, Figure 7 For Figure 6 A schematic diagram of a structure in which a second mask layer 230 is formed on the basis of the structure shown in FIG. Figure 7 As shown, the second mask layer 230 is entirely covered on the surface of the substrate, specifically, the second mask layer 230 covers the top surface of the gate precursor layer 120 and the top surface of the first mask layer 220, and the second mask layer 230 also extends to cover the sidewall of the gate precursor layer 120. The second mask layer 230 is used to further shield the first metal layer 210 and to separate the first metal layer 210 and the second metal layer 240 formed subsequently.

[0087] As some examples of this embodiment, the material of the second mask layer 230 is different from the material of the first metal layer 210. Further, the material of the second mask layer 230 is selected from an insulating material. For example, the material of the second mask layer 230 can be selected from one of silicon oxide, silicon nitride, and silicon oxynitride. In this example, the material of the second mask layer 230 is the same as the material of the first mask layer 220.

[0088] As some examples of this embodiment, the second mask layer 230 may be formed by chemical vapor deposition.

[0089] As some examples of this embodiment, the thickness of the second mask layer 230 may be 10 nm to 30 nm. By forming the second mask layer 230 with a thickness within this range, a better isolation effect can be achieved for the first metal layer 210 .

[0090] In some examples, the thickness of the second mask layer 230 may be 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, 22 nm, 25 nm, 28 nm, or 30 nm, or the thickness of the second mask layer 230 may be between any two of the above thicknesses.

[0091] Figure 8 For Figure 7 A schematic diagram of a structure in which the second mask layer 230 is selectively removed based on the structure shown. Figure 8As shown, the second mask layer 230 on the top surface of the gate precursor layer 120 is selectively removed, and at least a portion of the second mask layer 230 on the sidewall of the gate precursor layer 120 is retained, and the retained second mask layer 230 can completely shield the first metal layer 210 underneath.

[0092] As some examples of this embodiment, the step of selectively removing the second mask layer 230 includes: etching the second mask layer 230 using a second plasma, and controlling the etching direction of the second plasma to be inclined relative to the normal direction of the substrate, and the acute angle formed between the etching direction of the second plasma and the normal direction of the substrate is greater than the acute angle formed between the etching direction of the first plasma and the normal direction of the substrate.

[0093] Reference Figure 8 As shown, Figure 8 The arrow in shows the etching direction of the second plasma. By using the second plasma with a larger inclination angle for etching, it can be ensured that the retained second mask layer 230 fully shields the first metal layer 210.

[0094] Reference Figure 8 As shown in some examples of this embodiment, in the process of etching the second mask layer 230 using the second plasma, the acute angle β between the etching direction of the second plasma and the normal direction of the substrate is controlled to be 60°~75°.

[0095] In some examples, the acute angle β between the etching direction of the second plasma and the normal direction of the substrate is controlled to be 60°, 62°, 64°, 66°, 68°, 70°, 72°, 74°, or 75°, or the acute angle β between the etching direction of the second plasma and the normal direction of the substrate is controlled to be between any two of the above angles.

[0096] Fig. 9 For Figure 8 A schematic diagram of a structure in which a second metal layer 240 is formed on the basis of the structure shown in FIG. Fig. 9 As shown, the second metal layer 240 can cover the entire substrate. The second metal layer 240 and the first metal layer 210 are separated by the second mask layer 230 and the first mask layer 220. It can be understood that the second metal layer 240 should directly contact the gate precursor layer 120 to react and form metal silicide in the subsequent process.

[0097] As some examples of this embodiment, the material of the second metal layer 240 may be selected from a material that can be combined with silicon to form a metal silicide. For example, the material of the second metal layer 240 may be selected from at least one of titanium, nickel, platinum, and cobalt. In this embodiment, the material of the second metal layer 240 may be the same as the material of the first metal layer 210. In other embodiments, the material of the second metal layer 240 may be different from the material of the first metal layer 210.

[0098] As some examples of this embodiment, the second metal layer 240 may be formed by chemical vapor deposition or physical vapor deposition.

[0099] As some examples of this embodiment, the thickness of the second metal layer 240 is greater than the thickness of the first metal layer 210. This can make the thickness of the metal silicide formed by the gate precursor layer 120 larger, thereby improving the conductive performance of the gate precursor layer 120.

[0100] As some examples of this embodiment, the thickness of the second metal layer 240 is 80 nm to 120 nm. By forming the second metal layer 240 with this thickness range, it is possible to ensure that the silicon material in the gate precursor layer 120 is fully reacted to form metal silicide in subsequent processes.

[0101] In some examples, the thickness of the second metal layer 240 is 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, or 120 nm, or the thickness of the second metal layer 240 may be between any two of the above thicknesses.

[0102] In step S5 , the remaining first metal layer 210 reacts with the silicon material in the source / drain region 111 to form a first metal silicide layer 150 , and the second metal layer 240 reacts with the silicon material in the gate precursor layer 120 to form a second metal silicide layer 160 .

[0103] Fig.10 For Fig. 9 Schematic diagram of a structure in which a first metal silicide layer 150 and a second metal silicide layer 160 are formed on the basis of the structure shown.

[0104] Reference Fig.10 As shown in some examples of this embodiment, the first metal silicide layer 150 can be formed in the source and drain regions 111, and the first metal silicide layer 150 can replace part of the source and drain regions 111 and be exposed from the surface of the source and drain regions 111. The first metal silicide layer 150 can provide good conductive contact performance for electrically connecting other components to the source and drain regions 111.

[0105] Reference Fig.10As shown, as some examples of this embodiment, the second metal silicide layer 160 can be formed in the gate precursor layer 120, and the second metal silicide layer 160 can partially or completely replace the gate precursor layer 120. In this embodiment, the second metal silicide layer 160 can completely replace the gate precursor layer 120, and the second metal silicide layer 160 can serve as a gate or a part of the gate.

[0106] In conventional technology, due to the actual carrier concentration, a depletion region is easily formed in the region near the interface of the polysilicon close to the gate dielectric layer 130. As some examples of this embodiment, the second metal silicide layer 160 may directly contact the gate dielectric layer 130, and such a configuration is conducive to avoiding the formation of a depletion region.

[0107] As some examples of this embodiment, the thickness of the first metal silicide layer 150 may be less than the thickness of the second metal silicide layer 160. A thicker second metal silicide layer 160 can make the gate have better conductivity, and a thinner first metal silicide layer 150 is less likely to penetrate the source and drain regions 111.

[0108] As some examples of this embodiment, the steps of forming the first metal silicide layer 150 and the second metal silicide layer 160 include: sequentially performing a first heat treatment and a second heat treatment on the substrate, the first metal layer 210 and the second metal layer 240. The temperature of the first heat treatment is lower than the temperature of the second heat treatment. The first heat treatment is used to diffuse the metal material into the silicon material and react with the silicon material to generate a metal silicide. However, the electrical conductivity of the metal silicide is still poor at this time. Subsequently, a second heat treatment at a higher temperature is used to transform the metal silicide from a high resistance phase to a low resistance phase, thereby obtaining a first metal silicide layer 150 and a second metal silicide layer 160 with better electrical conductivity.

[0109] In this example, during the first heat treatment, the heat treatment temperature is 250° C. to 400° C. Further, the heat treatment temperature may be 250° C., 280° C., 300° C., 320° C., 350° C., 380° C., 400° C., or the heat treatment temperature may be between any two of the above temperatures.

[0110] In this example, during the first heat treatment, the heat treatment time is 30s to 60s. Further, the heat treatment time can be 30s, 35s, 40s, 45s, 50s, 55s, 60s, or the heat treatment time can be between any two of the above times.

[0111] In this example, during the second heat treatment, the heat treatment temperature is 450° C. to 600° C. Further, the heat treatment temperature may be 450° C., 480° C., 500° C., 520° C., 550° C., 580° C., 600° C., or the heat treatment temperature may be between any two of the above temperatures.

[0112] In this example, during the second heat treatment, the heat treatment time is 10s to 60s. Further, the heat treatment time can be 10s, 15s, 20s, 25s, 30s, 35s, 40s, 45s, 50s, 55s, 60s, or the heat treatment time can be between any two of the above times.

[0113] As some examples of this embodiment, the thickness of the second metal silicide layer 160 is 80 nm to 120 nm.

[0114] In some examples, the thickness of the second metal silicide layer 160 may be 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, or 120 nm, or the thickness of the second metal silicide layer 160 may be between any two of the above thicknesses.

[0115] As some examples of this embodiment, the thickness of the first metal silicide layer 150 is 15 nm to 20 nm.

[0116] In some examples, the thickness of the first metal silicide layer 150 may be 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, or 20 nm, or the thickness of the first metal silicide layer 150 may be between any two of the above thicknesses.

[0117] In this embodiment, after forming the first metal silicide layer 150 and the second metal silicide layer 160 , the step of removing the remaining second metal layer 240 , the second mask layer 230 , the first mask layer 220 and the first metal layer 210 is further included. Fig.11 For Fig.10 Schematic diagram of a structure in which the second metal layer 240, the second mask layer 230, the first mask layer 220 and the first metal layer 210 are removed based on the structure shown.

[0118] As some examples of this embodiment, the second metal layer 240 , the second mask layer 230 , the first mask layer 220 , and the first metal layer 210 may be removed by etching.

[0119] Reference Fig.11As shown, after removing the second metal layer 240, the second mask layer 230, the first mask layer 220 and the first metal layer 210, the second metal silicide layer 160 and the first metal silicide layer 150 are exposed from the surface of the substrate. Then, other structures can be further formed on the surface of the substrate according to the requirements of the device to be prepared, which will not be described in detail here.

[0120] In the method for preparing the semiconductor structure of this embodiment, the first metal layer 210 and the first mask layer 220 are first formed, and then a portion of the first mask layer 220 and the first metal layer 210 are selectively removed, and then the second metal layer 240 is formed. The first metal layer 210 is located on the surface of the source and drain region 111, and the second metal layer 240 is located on the surface of the gate precursor layer 120, and the first metal layer 210 and the second metal layer 240 are prepared separately, so the type and / or thickness of the metal formed on the surface of the source and drain region 111 and the gate precursor layer 120 may be different. This makes the thickness of the first metal silicide layer 150 and the second metal silicide layer 160 formed subsequently also different, that is, the preparation method can achieve a large difference in the thickness of the first metal silicide layer 150 and the second metal silicide layer 160. Therefore, the preparation method can avoid the limitation of the gate metal silicide thickness existing in the conventional technology.

[0121] Furthermore, in this embodiment, by designing a thicker second metal layer 240, the thickness of the second metal silicide layer 160 can be significantly increased, so that the silicon material in the gate precursor layer 120 is completely converted into metal silicide, which can avoid the depletion problem existing in traditional polysilicon gates and further improve the performance of the device.

[0122] The present disclosure also provides a semiconductor structure. The schematic diagram of the cross-sectional structure of the semiconductor structure can be referred to as Fig.11 The semiconductor structure includes an active region 110, a gate dielectric layer 130 and a gate, wherein the gate dielectric layer 130 is disposed between the active region 110 and the gate, the active region 110 includes two source and drain regions 111 respectively located on both sides of the gate, a first metal silicide layer 150 is disposed in the source and drain regions 111, and a second metal silicide layer 160 is disposed in the gate. The thickness of the first metal silicide layer 150 is less than that of the second metal silicide layer 160, and the second metal silicide layer 160 is directly in contact with the gate dielectric layer 130.

[0123] In conventional technology, due to the limitation of the actual preparation method, it is usually difficult for metal silicide to completely replace polysilicon, so the material in the gate directly in contact with the gate dielectric layer 130 is still polysilicon. Due to the limitation of the actual carrier concentration, the area near the interface of polysilicon close to the gate dielectric layer 130 is prone to form a depletion region. In this embodiment of the present disclosure, the second metal silicide layer 160 is directly in contact with the gate dielectric layer 130. Since the second metal silicide layer 160 has a conductivity significantly better than that of silicon material, it is more difficult for the interface of the second metal silicide close to the gate dielectric layer 130 to form a depletion region. Therefore, the semiconductor structure can not only reduce the resistance of the gate, but also avoid the problem of gate depletion.

[0124] Please note that the above embodiments are for illustrative purposes only and are not meant to be limiting of this document.

[0125] It should be understood that, unless otherwise specified herein, there is no strict order restriction for the execution of the steps, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the preparation process may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0126] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0127] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, the substrate comprising an active region and a gate precursor layer disposed on the active region, the active region comprising two source and drain regions respectively located on both sides of the gate precursor layer, and the gate precursor layer and the source and drain regions both having silicon material; forming a first metal layer and a first mask layer in sequence on the substrate, wherein the first metal layer and the first mask layer cover the gate precursor layer and the source and drain regions; Selectively removing the first mask layer and the first metal layer located on the top surface and the sidewall of the gate precursor layer, and retaining the first mask layer and the first metal layer located on the source and drain regions; forming a second metal layer on the substrate; The remaining first metal layer and the silicon material in the source and drain regions are reacted to form a first metal silicide layer, and the second metal layer and the silicon material in the gate precursor layer are reacted to form a second metal silicide layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of selectively removing the first mask layer and the first metal layer comprises: The first mask layer and the first metal layer are etched using a first plasma, and the etching direction of the first plasma is controlled to be inclined relative to a normal direction of the substrate.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: In the process of etching the first mask layer and the first metal layer by using the first plasma, the acute angle between the etching direction of the first plasma and the normal direction of the substrate is controlled to be 30°-45°.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: After selectively removing the first mask layer and the first metal layer and before forming the second metal layer, the following steps are also included: forming a second mask layer on the substrate, wherein the second mask layer covers the gate precursor layer and the first mask layer; The second mask layer located on the top surface of the gate precursor layer is selectively removed, and at least a portion of the second mask layer located on the sidewall of the gate precursor layer remains.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The step of selectively removing the second mask layer comprises: The second mask layer is etched using a second plasma, and the etching direction of the second plasma is controlled to be inclined relative to the normal direction of the substrate, and the acute angle formed between the etching direction of the second plasma and the normal direction of the substrate is greater than the acute angle formed between the etching direction of the first plasma and the normal direction of the substrate.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: In the process of etching the second mask layer using the second plasma, the acute angle between the etching direction of the second plasma and the normal direction of the substrate is controlled to be 60°-75°.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The substrate further includes a gate dielectric layer located between the active region and the gate precursor layer, and in the step of forming the second metal silicide layer, the formed second metal silicide layer directly contacts the gate dielectric layer; and / or, The substrate further comprises a gate spacer, and the gate spacer is arranged on the side wall of the gate precursor layer.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The thickness of the second metal silicide layer is greater than the thickness of the first metal silicide layer; and / or, The thickness of the second metal layer is greater than that of the first metal layer.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The steps of forming the first metal silicide layer and the second metal silicide layer include: performing a first heat treatment and a second heat treatment on the substrate, the first metal layer and the second metal layer in sequence, during the first heat treatment, the heat treatment temperature is 250°C~400°C, and the heat treatment time is 30s~60s, and during the second heat treatment, the heat treatment temperature is 450°C~600°C, and the heat treatment time is 10s~60s.

10. A semiconductor structure, characterized in that: The invention comprises an active region, a gate dielectric layer and a gate, wherein the gate dielectric layer is arranged between the active region and the gate, the active region comprises two source and drain regions respectively located on both sides of the gate, a first metal silicide layer is arranged in the source and drain regions, and a second metal silicide layer is arranged in the gate; The thickness of the first metal silicide layer is less than the thickness of the second metal silicide layer, and the second metal silicide layer directly contacts the gate dielectric layer.

Images