Grooving structure, grooving method and scribing process for wafer scribing

Abstract

The invention discloses a grooving structure, a grooving method and a scribing process for wafer scribing, the grooving structure is arranged on a wafer with a front surface and a back surface which are opposite to each other, and the grooving structure comprises the following steps: along a scribing boundary: forming a groove A1 and a groove A2 on one surface of the wafer, and forming a convex block between the groove A1 and the groove A2; grooves B are formed in the positions, corresponding to the protruding blocks, of the other face of the wafer; wherein the width of the convex block is different from that of the groove B. According to the method, the non-communicated grooves are formed in the wafer through etching to replace scribing channels formed by original implicit cutting, so that the cost of wafer scribing can be saved, and the wafer expansion rate is improved; and meanwhile, part of the wafer is remained in the groove on one side to form a convex block, so that the connection stability of the adjacent chips is improved, the irregular fracture of the wafer before the wafer expansion is prevented, and the yield is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer dicing, and in particular to a slotting structure, a slotting method and a dicing process for wafer dicing. Background Art

[0002] Wafer dicing is the last link in the integrated circuit manufacturing process. It is the process of cutting the completed wafer into individual chips. Whether it is traditional chip packaging or advanced wafer-level packaging technology, wafer dicing is an indispensable process.

[0003] For traditional chip packaging, wafer dicing is the front-end process of the packaging process, while for wafer-level packaging, dicing is often the last step of packaging. Both are directly related to the final reliability of the packaged product. For example, for wafers processed by MEMS, wafer dicing is usually divided into two steps: hidden cutting and expansion. After the wafer is processed and manufactured, a dicing lane is left on the wafer. First, the wafer is pasted on a UV film and invisible sliced ​​by laser. The hidden cutting can break the internal structure of the silicon in the dicing lane area. Then the wafer is expanded by an expander to form chips one by one. Finally, the UV film is removed by a debonding machine to remove the chip.

[0004] However, the hidden cutting process is not only costly, but also has very high requirements on the process of wafers and scribe lines. If the cross-sectional structure of the scribe line contains multiple layers of different materials, it may cause the laser power to decrease, and multiple hidden cutting may be required, resulting in a surge in costs. For example, if the scribe line in a certain area is contaminated or has residue, it may cause the expansion of the area to fail, and some chips may be connected together and cannot be used, causing losses.

[0005] The patent document with application number 202011095834.7 discloses a wafer splitting and expanding device and a wafer splitting and expanding method. The splitting adopts an implicit cutting process of the dicing lanes, which has the following problems: complex process, high dicing cost, and difficulty in ensuring the success rate.

[0006] The patent document with application number 202010619237.3 discloses a wafer expansion method including the steps: the wafer splitting method in the scheme also adopts the hidden cutting process of the dicing road, which also has the following problems: complex process, high dicing cost, and difficult to guarantee success rate.

[0007] Therefore, a grooving structure, method and process for wafer dicing are needed to simplify the dicing production process, reduce the dicing process cost and improve the success rate. Summary of the invention

[0008] In view of the above problems, the object of the present invention is to provide a slotting structure, a slotting method and a dicing process for wafer dicing, so as to simplify the dicing production process, reduce the dicing process cost and improve the success rate.

[0009] The object of the present invention can be achieved by the following technical solution: a slotting structure for wafer dicing, the slotting structure is opened on a wafer having a front side and a back side opposite to each other, the slotting structure includes, along the dicing boundary:

[0010] Grooves A1 and A2 are formed on one side of the wafer, and a convex block is formed between the grooves A1 and A2; and grooves B are formed on the other side of the wafer at a position corresponding to the convex block.

[0011] By etching non-connected grooves on both sides of the wafer, instead of the original implicit cutting formed dicing lanes, costs can be saved. At the same time, part of the wafer remains in the groove on one side to form a raised block.

[0012] The width of the protruding block is greater than the width of the groove B, thereby increasing the adhesion of the edges at the boundaries of adjacent chips.

[0013] The width of the protrusion is greater than the width of the groove B, which is beneficial to maintain the stability of the connection between adjacent chips before wafer expansion, prevent irregular breakage of the wafer before wafer expansion, and improve the yield rate

[0014] Furthermore: a groove A1 and a groove A2 are formed on the front side of the wafer, and a groove B is formed on the back side of the wafer at a position corresponding to the protruding block, and the depth of the groove A1 or the groove A2 is less than the depth of the groove B.

[0015] Furthermore: groove A1 and groove A2 are formed on the back of the wafer, and groove B is formed on the front of the wafer at a position corresponding to the protruding block; the sum of the depth of groove A1 or groove A2 and the depth of groove B is less than the thickness of the wafer.

[0016] Through a variety of etching and grooving methods, a variety of dicing and grooving solutions are formed, which can be flexibly selected according to wafer specifications, which is beneficial to improving wafer dicing quality.

[0017] Furthermore, the wafer is an SOI wafer, and the SOI wafer includes bottom silicon, a buried oxide layer and a top silicon which are stacked.

[0018] Furthermore: the groove A1 and / or the groove A2 penetrates through the top silicon to the buried oxide layer, and the groove B penetrates through the bottom silicon to the buried oxide layer.

[0019] Furthermore: the groove B penetrates through the top silicon to the buried oxide layer, and the groove A1 and / or groove A2 penetrates through the bottom silicon to the buried oxide layer.

[0020] By etching the SOI wafer, a groove penetrating into the buried oxide layer is formed, which is beneficial for wafer expansion and separation to obtain high-quality chip monomers.

[0021] A slotting method for forming the above-mentioned slotting structure for wafer dicing comprises the following steps:

[0022] S11, coating a photoresist on the surface of the wafer;

[0023] S12, performing photolithography operation on the photoresist to expose the wafer portion to be etched;

[0024] S13, etching the exposed part of the wafer to form grooves A1 and A2 at the intersection of adjacent chips on the wafer surface, so that a convex block is formed between grooves A1 and A2, and removing excess photoresist;

[0025] S14, coating a photoresist on the other surface of the wafer;

[0026] S15, performing photolithography operation on the photoresist to expose the wafer portion to be etched;

[0027] S16, etching the exposed part of the wafer to form a groove B at a position corresponding to the protruding block, and removing excess photoresist;

[0028] The width of the protruding block is greater than the width of the groove B, thereby increasing the adhesion of the edges at the boundaries of adjacent chips.

[0029] Through the above method, unconnected grooves are formed on the wafer etching to replace the original scribe lines formed by implicit cutting, which can save costs. At the same time, part of the wafer remains in the groove on one side to form a raised block, which can increase the stability of the connection between adjacent chips, prevent irregular breakage of the wafer before expansion, and improve the yield rate.

[0030] Furthermore, the cross-section of a single chip formed by wafer dicing is a square, a rhombus, a regular hexagon or a regular dodecagon.

[0031] A dicing process, based on the above-mentioned grooving method, comprises the following steps:

[0032] S21, coating a photoresist on the surface of the wafer;

[0033] S22, performing photolithography operation on the photoresist to expose the wafer portion to be etched;

[0034] S23, etching the exposed part of the wafer to form groove A1 and groove A2 at the intersection of adjacent chips on the wafer surface, so that a convex block is formed between groove A1 and groove A2, and removing excess photoresist;

[0035] S24, coating a photoresist on the other surface of the wafer;

[0036] S25, performing photolithography operation on the photoresist to expose the wafer portion to be etched;

[0037] S26, etching the exposed portion of the wafer to form a groove B at a position corresponding to the protruding block, and removing excess photoresist;

[0038] The width of the protruding block is greater than the width of the groove B, thereby increasing the adhesion of the edges at the boundaries of adjacent chips.

[0039] Through the above process, unconnected grooves are formed on the wafer etching to replace the original scribe lines formed by implicit cutting, which can save costs. At the same time, part of the wafer remains in the groove on one side to form a raised block, which can increase the stability of the connection between adjacent chips, prevent irregular breakage of the wafer before expansion, and improve the yield rate.

[0040] Beneficial effects of the present invention:

[0041] 1. The present invention forms unconnected grooves on the wafer by etching, replacing the dicing lanes originally formed by implicit cutting, which can save costs in wafer dicing and improve the wafer expansion rate; at the same time, part of the wafer remains in the groove on one side to form a convex block, which increases the stability of the connection between adjacent chips, prevents irregular fractures of the wafer before wafer expansion, and improves the yield rate.

[0042] 2. The present invention uses etched grooves to replace scribe lines. The chips on the wafer can be equilateral rhombuses, regular hexagons or regular dodecagons, so that the grooves on a single chip are staggered and not connected in a straight line, further increasing the stability of a single chip before expansion.

[0043] 3. The present invention forms the grooves through the process of the chip itself, without adding a separate process, thus simplifying the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of a wafer dicing method of the present invention;

[0045] Figure 2 It is a schematic diagram of another wafer dicing method of the present invention;

[0046] Figure 3 A schematic diagram of another wafer dicing method of the present invention;

[0047] Figure 4 It is a schematic diagram of another wafer dicing method of the present invention;

[0048] Figure 5 For the present invention Figure 1-4 A perspective structural diagram of the A component;

[0049] Figure 6 For the present invention Figure 5 Schematic diagram of the cross-sectional structure;

[0050] Figure 7 For the present invention Figure 1-4Another perspective structural diagram of the A component;

[0051] Figure 8 For the present invention Figure 7 Schematic diagram of the cross-sectional structure;

[0052] Fig. 9 For the present invention Figure 1-4 Another perspective structural diagram of the A component;

[0053] Fig.10 For the present invention Fig. 9 Schematic diagram of the cross-sectional structure;

[0054] Fig.11 For the present invention Figure 1-4 Another perspective structural diagram of the A component;

[0055] Fig.12 For the present invention Fig.11 Schematic diagram of the cross-sectional structure;

[0056] Fig.13 It is a schematic diagram of the process of the slotting method of the present invention.

[0057] 100, wafer; 110, chip 1; 120, chip 2; 130, bump; 140, groove A1; 150, groove A2; 160, groove B;

[0058] 200, silicon wafer; 210, top silicon; 220, buried oxide layer; 230, bottom silicon. DETAILED DESCRIPTION

[0059] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0060] Example 1

[0061] The present invention discloses a slotting structure for wafer 100 dicing, comprising wafer 100, which may be a silicon wafer. The slotting structure is formed at the intersection of adjacent chips at the dicing boundary of wafer 100 (ie, the dotted line in the figure).

[0062] like Figure 1-Figure 4 As shown, by dicing the wafer 100, the cross-section of a single chip formed can be a square, a rhombus, a regular hexagon or a regular dodecagon, so that the grooves on the single chip are staggered and not connected in a straight line, further increasing the stability of the single chip before expansion.

[0063] by Figure 1-Figure 4Take the adjacent chips in part A as an example. The structure of part A is as follows: Figure 5 As shown in Figure 6, the front side of the junction of chip 110 and chip 2 120 is etched to form groove A1140 and groove A2150, and the back side is etched to form groove B160. The groove structure formed by groove A1140, groove A2150 and groove B160 replaces the role of the dicing road, avoids separate hidden cutting operations, and can ensure the normal progress of subsequent wafer expansion operations.

[0064] At the same time, the sum of the depth of the groove A1140 or the groove A2150 and the depth of the groove B160 is less than the thickness of the wafer 100, so that the junction of the chip 110 and the chip 2 120 is not prone to breakage before wafer expansion.

[0065] A portion of the wafer 100 remains between the groove A1140 and the groove A2150 to form a protruding block 130, and the width of the protruding block 130 is greater than the width of the groove B160. Such a structure can increase the adhesion of the edges of chip 110 and chip 2 120, and prevent irregular breakage of chip 110 and chip 2 120 before expansion.

[0066] Example 2

[0067] like Figure 7 As shown in or 8, what is different from Example 1 is that groove A1140 and groove A2150 are formed by etching at the back side of the junction of chip 1 110 and chip 2 120, and groove B160 is formed on the front side. The groove structure formed by groove A1140, groove A2150 and groove B160 replaces the role of the dicing road, avoids separate hidden cutting operations, and can ensure the normal progress of subsequent wafer expansion operations.

[0068] At the same time, the sum of the depth of the groove A1140 or the groove A2150 and the depth of the groove B160 is less than the thickness of the wafer 100, so that the junction of the chip 110 and the chip 2 120 is not prone to breakage before wafer expansion.

[0069] A portion of the wafer 100 remains between the groove A1140 and the groove A2150 to form a protruding block 130, and the width of the protruding block 130 is greater than the width of the groove B160. Such a structure can increase the adhesion of the edges of chip 110 and chip 2 120, and prevent irregular breakage of chip 110 and chip 2 120 before expansion.

[0070] Example 3

[0071] Different from the first embodiment, the wafer 100 used in the present embodiment is a SOI wafer 200 . The SOI wafer 200 includes a bottom silicon 230 , a buried oxide layer 220 and a top silicon 210 which are stacked. The groove structure is formed at the intersection of adjacent chips along the SOI wafer 200 .

[0072] like Fig. 9As shown in or 10, the front side of chip 110 and chip 2 120 is top silicon 210, and the back side is bottom silicon 230. The top silicon 210 of chip 110 and chip 2 120 is connected to form groove A1140 and groove A2150, and the bottom silicon 230 of chip 110 and chip 2 120 is connected to form groove B160. Groove A1140 and / or A2150 penetrates the top silicon 210 to the buried oxide layer 220, and groove B160 penetrates the bottom silicon 230 to the buried oxide layer 220. This structure can effectively utilize the force difference of each layer of wafer 100, which is beneficial to wafer 100 expansion and separation, and obtain high-quality chip monomers.

[0073] At the same time, the slot structure formed by slot A1140, slot A2150 and slot B160 replaces the role of the dicing road, avoiding hidden cutting operations while ensuring the normal progress of subsequent wafer expansion operations.

[0074] At the same time, part of the wafer 100 remains between the groove A1140 and the groove A2150 to form a protruding block 130, and the width of the protruding block 130 is greater than the width of the groove B160. Such a structure can increase the adhesion of the edges of chip 110 and chip 2 120, thereby preventing irregular breakage of chip 110 and chip 2 120 before expansion.

[0075] Example 4

[0076] like Fig.11 As shown in or 12, the difference from Example 3 is that the front side of chip 110 and chip 2 120 is bottom silicon 230, and the back side is top silicon 210. The bottom silicon 230 of chip 110 and chip 2 120 intersects to form groove A1140 and groove A2150, and the top silicon 210 of chip 110 and chip 2 120 intersects to form groove B160. Grooves A1140 and / or A2150 penetrate through the bottom silicon 230 to the buried oxide layer 220, and groove B160 penetrates through the top silicon 210 to the buried oxide layer 220. This structure can effectively utilize the force difference of each layer of the wafer 100, which is beneficial to the wafer 100 expansion and separation, and obtains high-quality chip monomers.

[0077] At the same time, the slot structure formed by slot A1140, slot A2150 and slot B160 replaces the role of the dicing road, avoiding hidden cutting operations while ensuring the normal progress of subsequent wafer expansion operations.

[0078] At the same time, part of the wafer 100 remains between the groove A1140 and the groove A2150 to form a protruding block 130, and the width of the protruding block 130 is greater than the width of the groove B160. Such a structure can increase the adhesion of the edges of chip 110 and chip 2 120, thereby preventing irregular breakage of chip 110 and chip 2 120 before expansion.

[0079] Example 5

[0080] This embodiment is a slotting method for embodiments 1 to 4. Fig.13 As shown, the following steps are included:

[0081] S11, coating a photoresist on the surface of the wafer 100;

[0082] S12, performing a photolithography operation on the photoresist to expose the portion of the wafer 100 that needs to be etched;

[0083] S13, etching the exposed part of the wafer 100, forming a groove A1140 and a groove A2150 at the intersection of adjacent chips on the surface of the wafer 100, forming a protrusion 130 between the groove A1140 and the groove A2150, and removing excess photoresist;

[0084] S14, coating photoresist on the other surface of the wafer 100;

[0085] S15, performing a photolithography operation on the photoresist to expose the portion of the wafer 100 that needs to be etched;

[0086] S16, etching the exposed portion of the wafer 100 to form a groove B160 at a position corresponding to the protruding block 130, and removing excess photoresist.

[0087] By using the wafer 100 dicing method, the cross-section of a single chip formed can be a square, a rhombus, a regular hexagon or a regular dodecagon, so that the grooves on the single chip are staggered and not connected in a straight line, further increasing the stability of the single chip before expansion.

[0088] Furthermore, the width of the protrusion 130 is greater than the width of the groove B160, which increases the adhesion of the edges at the boundaries of adjacent chips; the width of the protrusion 130 is greater than the width of the groove B160, which is beneficial to maintaining the stability of the connection between adjacent chips before expansion, preventing irregular breakage of the wafer 100 before expansion, and improving the yield rate.

[0089] Further: groove A1140 and groove A2150 are opened on the front side of the wafer 100, and groove B160 is opened on the back side of the wafer 100 corresponding to the protruding block 130; the sum of the depth of groove A1140 or groove A2150 and the depth of groove B160 is less than the thickness of the wafer 100; or, groove A1140 and groove A2150 are opened on the back side of the wafer 100, and groove B160 is opened on the front side of the wafer 100 corresponding to the protruding block 130; the sum of the depth of groove A1140 or groove A2150 and the depth of groove B160 is less than the thickness of the wafer 100.

[0090] Through a variety of etching and grooving methods, various dicing and grooving schemes are formed, which can be flexibly selected according to the specifications of the wafer 100, which is beneficial to improving the dicing quality of the wafer 100.

[0091] Further, the wafer 100 is an SOI wafer 200, and the SOI wafer 200 includes a stacked bottom silicon 230, a buried oxide layer 220, and a top silicon 210. The grooves A1140 and A2150 penetrate the top silicon 210 to the buried oxide layer 220, and the groove B160 penetrates the bottom silicon 230 to the buried oxide layer 220; or, the groove B160 penetrates the top silicon 210 to the buried oxide layer 220, and the grooves A1140 and A2150 penetrate the bottom silicon 230 to the buried oxide layer 220.

[0092] By etching the SOI wafer 200 to form a groove penetrating to the buried oxide layer 220, it is beneficial to expand and separate the wafer 100 to obtain high-quality chip monomers.

[0093] Example 6

[0094] This embodiment is a slotting process for embodiment 5, and the process includes the following steps:

[0095] S21, coating a photoresist on the surface of the wafer 100;

[0096] S22, performing a photolithography operation on the photoresist to expose the portion of the wafer 100 that needs to be etched;

[0097] S23, etching the exposed part of the wafer 100, forming a groove A1140 and a groove A2150 at the intersection of adjacent chips on the surface of the wafer 100, forming a protrusion 130 between the groove A1140 and the groove A2150, and removing excess photoresist;

[0098] S24, coating photoresist on the other surface of the wafer 100;

[0099] S25, performing a photolithography operation on the photoresist to expose the portion of the wafer 100 that needs to be etched;

[0100] S26, etching the exposed portion of the wafer 100 to form a groove B160 at a position corresponding to the protruding block 130, and removing excess photoresist;

[0101] The width of the protruding block 130 is greater than the width of the groove B160, thereby increasing the adhesion of the edges at the boundaries of adjacent chips.

[0102] By adopting the above-mentioned slotting process, the present invention can form the slots through the etching process of the chip itself, without adding a separate hidden cutting process, thus simplifying the process flow.

[0103] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A slotting structure for wafer dicing, It is characterized in that The groove structure is formed on a wafer (100) having a front side and a back side opposite to each other, and the groove structure includes, along a dicing boundary: A groove A1 (140) and a groove A2 (150) are formed on one side of the wafer (100), and a protrusion (130) is formed between the groove A1 (140) and the groove A2 (150); A groove B (160) is formed on the other side of the wafer (100) at a position corresponding to the protruding block (130); The width of the protruding block (130) is greater than the width of the groove B (160), thereby increasing the adhesion of the edges at the boundaries of adjacent chips.

2. The slotting structure for wafer dicing according to claim 1, Features: The wafer (100) has a groove A formed on the front side. 1 (140) and slot A 2 (150), a groove B (160) is formed on the back side of the wafer (100) at a position corresponding to the protruding block (130); Slot A 1 (140) or slot A 2 The sum of the depth of (150) and the depth of groove B (160) is less than the thickness of the wafer (100).

3. The slotting structure for wafer dicing according to claim 1, Features: A groove A1 (140) and a groove A2 (150) are formed on the back of the wafer (100), and a groove B (160) is formed on the front of the wafer (100) at a position corresponding to the protruding block (130); Slot A1(140) or Slot A 2 The sum of the depth of (150) and the depth of groove B (160) is less than the thickness of the wafer (100).

4. The slotting structure for wafer dicing according to any one of claim 1, It is characterized in that The wafer (100) is an SOI wafer (200), and the SOI wafer (200) comprises a bottom silicon (230), a buried oxide layer (220), and a top silicon (210) which are stacked.

5. The slotting structure for wafer dicing according to claim 4, Features: The slot A 1 (140) and / or slot A 2 The groove (150) penetrates the top silicon (210) to the buried oxide layer (220), and the groove B (160) penetrates the bottom silicon (230) to the buried oxide layer (220).

6. The slotting structure for wafer dicing according to claim 4, Features: The groove B (160) penetrates the top silicon (210) to the buried oxide layer (220), and the groove A 1 (140) and / or slot A 2 (150) penetrates through the bottom silicon (230) to the buried oxide layer (220).

7. A slotting method for forming a slotting structure for wafer dicing as claimed in any one of claims 1 to 6, It is characterized in that The following steps are involved: S11, coating a photoresist on the surface of the wafer (100); S12, performing a photolithography operation on the photoresist to expose the portion of the wafer (100) that needs to be etched; S13, etching the exposed portion of the wafer (100), forming a groove A1 (140) and a groove A2 (150) at the intersection of adjacent chips on the surface of the wafer (100), forming a protrusion (130) between the groove A1 (140) and the groove A2 (150), and removing excess photoresist; S14, coating a photoresist on the other surface of the wafer (100); S15, performing a photolithography operation on the photoresist to expose the portion of the wafer (100) that needs to be etched; S16, etching the exposed portion of the wafer (100) to form a groove B (160) at a position corresponding to the protruding block (130), and removing excess photoresist; The width of the protruding block (130) is greater than the width of the groove B (160), thereby increasing the adhesion of the edges at the boundaries of adjacent chips.

8. The slotting method according to claim 7, It is characterized in that The cross section of a single chip formed by slicing the wafer (100) is a square, a rhombus, a regular hexagon or a regular dodecagon.

9. A dicing process, based on the grooving method according to claim 7 or 8, It is characterized in that The following steps are involved: S21, coating a photoresist on the surface of the wafer (100); S22, performing a photolithography operation on the photoresist to expose the portion of the wafer (100) that needs to be etched; S23, etching the exposed portion of the wafer (100), forming a groove A1 (140) and a groove A2 (150) at the intersection of adjacent chips on the surface of the wafer (100), forming a protrusion (130) between the groove A1 (140) and the groove A2 (150), and removing excess photoresist; S24, coating a photoresist on the other surface of the wafer (100); S25, performing a photolithography operation on the photoresist to expose the portion of the wafer (100) that needs to be etched; S26, etching the exposed portion of the wafer (100) to form a groove B (160) at a position corresponding to the protruding block (130), and removing excess photoresist; The width of the protruding block (130) is greater than the width of the groove B (160), thereby increasing the adhesion of the edges at the boundaries of adjacent chips.

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