GaN monolithic integrated device and preparation method thereof

Abstract

The invention provides a GaN monolithic integrated device and a preparation method thereof, and belongs to the technical field of semiconductor devices. According to the invention, the GaN monolithic integrated device is obtained by integrating the high-density capacitor with the deep groove structure and the GaN HEMT device. According to the GaN monolithic integrated device, the parasitic effect can be greatly reduced or eliminated, and the circuit reliability is improved; moreover, compared with a planar MIM capacitor, the high-density capacitor with the deep groove structure has the advantage that the capacitance density is improved by more than 100 times; in addition, the structure is equivalent to thinning the substrate, and the heat dissipation capability of the integrated device can also be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a GaN monolithic integrated device and a preparation method thereof. Background Art

[0002] In GaN push-pull drive circuits or half-bridge circuits, in order to ensure the continuous normal operation of the upper tube circuit, it is often necessary to introduce a bootstrap circuit to raise the power supply voltage in the circuit. The bootstrap circuit consists of a capacitor and a diode. The capacitor stores charge and the diode prevents current backflow. Since the voltage across the capacitor cannot change suddenly, when the frequency is high, the voltage of the bootstrap circuit is the voltage of the circuit input plus the voltage on the capacitor.

[0003] The existing process can basically realize the integration of GaN gate driver devices and power chips. However, for the capacitor part, since the capacitance value is positively correlated with the area, and the required capacitance value is usually large (generally, the bootstrap capacitance value in the gate driver is tens of pF, the bootstrap capacitance value in the half-bridge circuit is tens of nF, and the bypass capacitance value is more than μF), the planar MIM (Metal-Insulator-Metal) capacitance density prepared based on the existing process is usually small, usually <2fF / μm 2 Therefore, if we want to use the existing planar MIM capacitor process (Cs = 0.32fF / μm 2 ) to obtain a 32pF capacitor (bootstrap capacitor in the gate drive circuit), a 0.1mm 2 area, which occupies about 20% of the overall chip area; if you want to obtain a 3.2nF capacitor (bootstrap capacitor in a half-bridge circuit), you need 10mm 2 This will occupy more than 50% of the overall chip area. It can be seen that the capacitor integrated based on the existing process will significantly increase the area of ​​the GaN monolithic integrated device and increase the integration cost.

[0004] For the above reasons, the capacitors in the circuit are often connected externally. However, due to routing problems, external capacitors will introduce parasitic inductance and parasitic resistance, causing switching delays in the drive circuit and peak voltage fluctuations at both ends of the capacitor. Among them, the increase in switching delay will affect the high-frequency characteristics of the circuit, and the large peak-to-peak fluctuations at both ends of the capacitor will easily damage the capacitor; especially when the switching frequency is high (greater than kHz), the large peak-to-peak value at both ends of the capacitor will easily lead to increased harmonic losses, causing the capacitor to overheat and burn. Summary of the invention

[0005] Based on the above technical problems, the present invention provides a GaN monolithic integrated device and a preparation method thereof. By integrating the GaN HEMT device with a high-density capacitor with a deep trench structure, the parasitic effect of the circuit is weakened, and the high-frequency performance of the circuit and the reliability of the circuit as a whole are improved.

[0006] Specifically, the present invention adopts the following technical solutions to achieve the above objectives:

[0007] A method for preparing a GaN monolithic integrated device comprises the following steps:

[0008] S1. Provide a substrate, the substrate comprising a silicon-based substrate and an epitaxial layer, an AlGAN layer, a first dielectric layer and a second dielectric layer sequentially stacked on the silicon-based substrate; one side of the substrate is a GaN HEMT device region, and the other side is a capacitor region; the GaN HEMT device region is provided with a GaN HEMT device; the source and the drain of the GaN HEMT device are electrically connected to a first interconnecting metal layer located between the first dielectric layer and the second dielectric layer through a first metal plug respectively; a plurality of second metal plugs penetrate the second dielectric layer and are respectively connected to the first interconnecting metal layer;

[0009] S2, etching a plurality of first deep trenches in the capacitor region;

[0010] S3, depositing a first isolation layer, a first electrode, and a second isolation layer in sequence on the surface of the structure obtained in step S2;

[0011] S4, etching away the first isolation layer, the first electrode and the second isolation layer on the surface of the second dielectric layer in the GaN HEMT device region;

[0012] S5, etching the second isolation layer closest to the GaN HEMT device region A to expose the first electrode;

[0013] S6, depositing a metal layer on the surface of the device structure obtained in step S5; etching the metal layer to obtain a second interconnect metal layer, a second electrode and a third electrode; the second interconnect metal layer located in the GaN HEMT device region is electrically connected to the first metal interconnect layer through the second metal plug;

[0014] S7, depositing a third dielectric layer on the surface of the device structure obtained in step S6, opening a plurality of first through holes in the third dielectric layer, and filling each of the first through holes with metal to form a plurality of third metal plugs;

[0015] S8, depositing a metal layer on the surface of the device structure obtained in step S7, and etching the metal layer to form a plurality of third interconnected metal layers; the second interconnected metal layer, the second electrode and the third electrode are all electrically connected to the third interconnected metal layer through the third metal plug;

[0016] S9, depositing a passivation layer on the surface of the device structure obtained in step S8, and etching the passivation layer to expose the surface of the third interconnect metal layer away from the third dielectric layer.

[0017] Alternatively, the method for preparing the GaN monolithic integrated device comprises the following steps:

[0018] P1. Provide a substrate, the substrate comprising a silicon-based substrate and an epitaxial layer, an AlGAN layer, a first dielectric layer and a second dielectric layer sequentially stacked on the silicon-based substrate; one side of the substrate is a GaN HEMT device region, and the other side is a capacitor region; the GaN HEMT device region is provided with a GaN HEMT device; the source and the drain of the GaN HEMT device are electrically connected to a first interconnecting metal layer located between the first dielectric layer and the second dielectric layer through a first metal plug respectively; a plurality of second metal plugs penetrate the second dielectric layer and are respectively connected to the first interconnecting metal layer;

[0019] P2, etching a plurality of first deep trenches in the capacitor region;

[0020] P3, sequentially depositing a first electrode and a second isolation layer on the surface of the structure obtained in step P2;

[0021] P4, etching away the first electrode and the second isolation layer inside the first deep trench farthest from the GaN HEMT device region and around its opening, as well as the first electrode and the second isolation layer located in the GaN HEMT device region;

[0022] P5. Depositing a metal layer on the surface of the structure obtained in step P4, and etching the metal layer to obtain a second interconnect metal layer, a second electrode, and a third electrode; the second interconnect metal layer located in the GaN HEMT device region is electrically connected to the first metal interconnect layer through the second metal plug;

[0023] P6. Depositing a third dielectric layer on the surface of the device structure obtained in step P5, and opening a plurality of first through holes in the third dielectric layer, and filling each of the first through holes with metal to form a plurality of third metal plugs;

[0024] P7, depositing a metal layer on the surface of the device structure obtained in step P6, and etching the metal layer to form a plurality of third interconnected metal layers; the second interconnected metal layer, the second electrode and the third electrode are all electrically connected to the third interconnected metal layer through the third metal plug;

[0025] P8. Depositing a passivation layer on the surface of the device structure obtained in step P7, and etching the passivation layer to expose the surface of the third interconnect metal layer away from the third dielectric layer.

[0026] Alternatively, the method for preparing the GaN monolithic integrated device comprises the following steps:

[0027] R1. Provide a substrate, the substrate comprising a silicon-based substrate and an epitaxial layer, an AlGaN layer, a first dielectric layer, a second dielectric layer and a passivation layer stacked in sequence on the silicon-based substrate; a GaN HEMT device is arranged on the substrate; a source and a drain of the GaN HEMT device are electrically connected to a first interconnected metal layer located between the first dielectric layer and the second dielectric layer through a first metal plug respectively; a plurality of fourth interconnected metal layers are arranged between the second dielectric layer and the passivation layer; a surface of the fourth interconnected metal layer away from the second dielectric layer is at least partially exposed to the outside; the first interconnected metal layer and the fourth metal interconnected layer are connected through a plurality of second metal plugs arranged in the second dielectric layer; a fourth metal plug penetrates the second dielectric layer, the first dielectric layer, the AlGaN layer and the epitaxial layer, and extends into the silicon-based substrate; the fourth metal plug is connected to the fourth interconnected metal layer;

[0028] R2, bonding the surface of the passivation layer away from the second dielectric layer to a carrier, turning the substrate over, and thinning the side of the silicon-based substrate away from the epitaxial layer;

[0029] R3, etching a plurality of first deep trenches on a side of the silicon-based substrate away from the epitaxial layer; the top of the first deep trench is located in the silicon-based substrate and is coplanar with the bottom of the fourth metal plug;

[0030] R4. Depositing a first electrode, a second isolation layer and a second electrode in sequence on the inner wall of the first deep trench and the surface of the silicon-based substrate facing away from the epitaxial layer, and peeling off the carrier; the first electrode is electrically connected to the fourth interconnect metal layer through the fourth metal plug.

[0031] In a preferred embodiment, after depositing the second isolation layer in step S3, the step also includes a step of continuing to deposit a conductive material; step S4 also includes a step of etching away the conductive material on the surface of the second isolation layer, retaining the conductive material inside the first deep groove to obtain a conductive filling layer.

[0032] In a preferred solution, after depositing the second isolation layer in step R4, a conductive filling layer is firstly filled inside the first deep trench, and then the second electrode is deposited.

[0033] In a further preferred embodiment, the conductive material is at least one of n-type polysilicon, p-type polysilicon, tungsten metal, and copper metal.

[0034] In a preferred embodiment, the silicon-based substrate is any one of a p-type silicon substrate, an n-type silicon substrate, an intrinsic silicon substrate, an SOI substrate or a pn junction silicon substrate.

[0035] In a further preferred solution, when the silicon-based substrate is an SOI substrate, the bottom of the first deep trench in step S2 is located in the top silicon layer or the middle oxide buried layer of the SOI substrate.

[0036] In a further preferred embodiment, a second deep trench is opened on the substrate in step S1, and the second deep trench opens from a surface of the AlGaN layer on a side away from the epitaxial layer and extends into the oxide buried layer of the SOI substrate.

[0037] In a further preferred embodiment, when the silicon-based substrate is an SOI substrate, the bottom of the first deep trench in step P2 is located in the top silicon layer or the middle oxide buried layer of the SOI substrate.

[0038] In a further preferred embodiment, a second deep trench is opened on the substrate in step P1, and the second deep trench opens from a surface of the AlGaN layer on a side away from the epitaxial layer and extends into the oxide buried layer of the SOI substrate.

[0039] In a preferred embodiment, the material of the epitaxial layer is a GaN-based material or / and an AlN-based material.

[0040] In a further preferred embodiment, the material of the epitaxial layer includes at least one of AlN, AlGaN and GaN.

[0041] In a preferred solution, along the direction from the second dielectric layer to the silicon-based substrate, the thickness of the epitaxial layer is 1-20 μm.

[0042] In a preferred solution, the silicon-based substrate is etched to a depth of 1 to 200 μm along the direction from the second dielectric layer to the silicon-based substrate or along the direction from the silicon-based substrate to the second dielectric layer.

[0043] In a preferred embodiment, the material of the first isolation layer is SiO 2 、Si 3 N 4 、Al 2 O 3 , at least one of AlN, AlON, and SiON.

[0044] In a preferred embodiment, the material of the second isolation layer is SiO2 、Si 3 N 4 、Al 2 O 3 , HfO 2 、TiO 2 , Y 2 O 3 、ZrO 3 At least one of them.

[0045] In a preferred embodiment, the thickness of the first isolation layer is 10-1000 nm.

[0046] In a preferred embodiment, the thickness of the second isolation layer is 5 to 500 nm.

[0047] In a preferred embodiment, the material of the first dielectric layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , and at least one of polyimide.

[0048] In a preferred embodiment, the material of the second dielectric layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , and at least one of polyimide.

[0049] In a preferred embodiment, the material of the third dielectric layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , and at least one of polyimide.

[0050] In a preferred embodiment, the material of the passivation layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , and at least one of polyimide.

[0051] In a preferred embodiment, the material of the first electrode is at least one of Ti, TiN, Au, Al, Ni, and Pt.

[0052] In a preferred solution, the material of the second interconnect metal layer is a Ti / TiN / Al / Ti / TiN stack or a Ti / Au / Ti stack.

[0053] The present invention also provides a GaN monolithic integrated device prepared according to the preparation method described in any of the above schemes.

[0054] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) The present invention integrates high-density capacitors (including coplanar integration and vertical integration) into GaN HEMT-related circuits to reduce the parasitic effects of the circuits and improve the high-frequency performance of the circuits and the reliability of the circuits as a whole. (2) The MIM capacitor with a deep trench structure prepared in the present invention can greatly increase the density of the capacitors and reduce the capacitor area; compared with the planar MIM capacitor, the capacitor density is increased by more than 100 times, the integrated chip area is reduced, and the chip integration cost is reduced. (3) In the process of preparing the high-density capacitor in the present invention, the substrate is deep-grooved, which is equivalent to reducing the thickness of the integrated chip substrate, which can improve the heat dissipation capacity of the integrated chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of the structure of the device in step S1 or P1 in a specific embodiment of the present invention;

[0056] Figure 2 It is a schematic diagram of the structure of the device in step S2 or P2 in a specific embodiment of the present invention;

[0057] Figure 3 It is a schematic diagram of the structure of the device in step S3 in a specific embodiment of the present invention;

[0058] Figure 4 It is a schematic diagram of the structure of the device in step S4 in a specific embodiment of the present invention;

[0059] Figure 5 It is a schematic diagram of the structure of the device in step S5 in a specific embodiment of the present invention;

[0060] Figure 6 It is a schematic diagram of the structure of the device in step S6 in a specific embodiment of the present invention;

[0061] Figure 7 It is a schematic diagram of the structure of the device in step S7 in a specific embodiment of the present invention;

[0062] Figure 8 It is a schematic diagram of the structure of the device in step S8 in a specific embodiment of the present invention;

[0063] Fig. 9 It is a schematic diagram of the structure of the device in step S9 in a specific embodiment of the present invention;

[0064] Fig.10 A schematic structural diagram of a GaN monolithic integrated device provided by the present invention;

[0065] Fig.11A schematic structural diagram of another GaN monolithic integrated device provided by the present invention;

[0066] Fig.12 It is a schematic diagram of the structure of the device in step P3 in a specific embodiment of the present invention;

[0067] Fig.13 It is a schematic diagram of the structure of the device in step P4 in a specific embodiment of the present invention;

[0068] Fig.14 It is a schematic diagram of the structure of the device in step P5 in a specific embodiment of the present invention;

[0069] Fig.15 A schematic diagram of the structure of another GaN monolithic integrated device provided by the present invention, which is also a schematic diagram of the structure of the device obtained in step P8;

[0070] Fig.16 A schematic diagram of another GaN monolithic integrated device provided by the present invention having a second deep trench opened on the structure;

[0071] Fig.17 A schematic structural diagram of another GaN monolithic integrated device provided by the present invention;

[0072] Fig.18 A schematic structural diagram of another GaN monolithic integrated device provided by the present invention;

[0073] Fig.19 A schematic structural diagram of another GaN monolithic integrated device provided by the present invention;

[0074] Fig. 20 It is a schematic diagram of the structure of the device in step R1 in a specific embodiment of the present invention;

[0075] Fig.21 It is a schematic diagram of the structure of the device in step R3 in a specific embodiment of the present invention;

[0076] Fig. 22 It is a schematic diagram of the structure of the device in step R4 in a specific embodiment of the present invention;

[0077] Fig.23 This is a schematic structural diagram of a device obtained by filling a conductive layer in step R4 in a specific embodiment of the present invention;

[0078] Fig.24 A schematic structural diagram of another GaN monolithic integrated device provided by the present invention;

[0079] Fig.25 It is a schematic diagram of a projection graph of the capacitor of the GaN monolithic integrated device of the present invention on a plane parallel to the silicon-based substrate;

[0080] Fig.26 It is a structural schematic diagram of a MIM planar capacitor in the prior art;

[0081] Fig. 27 It is a schematic diagram of the structure of a planar capacitor with a p-type GaN gate in the prior art.

[0082] In the figure: 1, silicon substrate; 11, bottom silicon; 12, oxide buried layer; 13, top silicon; 21, epitaxial layer; 22, AlGaN layer; 3a, first dielectric layer; 3a1, surface passivation layer; 3a2, field plate dielectric layer; 3a3, interlayer dielectric layer; 3b, second dielectric layer; 3c, third dielectric layer; 4, passivation layer; 5, source; 6, p-type GaN layer; 7, drain; 8, gate; 9a, first interconnect metal layer; 9b, The second interconnect metal layer; 9c, the third interconnect metal layer; 9d, the fourth interconnect metal layer; 10a, the first metal plug; 10b, the second metal plug; 10c, the third metal plug; 10d, the fourth metal plug; 11a, the first isolation layer; 11b, the second isolation layer; 12a, the first electrode; 12b, the second electrode; 12c, the third electrode; 13, the first deep trench; 14, the conductive filling layer; 15, the second deep trench; 16, the source field plate. DETAILED DESCRIPTION

[0083] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0084] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", "bottom", "top", etc., indicate the orientation or positional relationship based on the orientation or positional relationship in the drawings of the specification, or the orientation or positional relationship in which the product of this application is usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above" and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below" and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0085] Reference Figures 1 to 9 The present invention provides a method for preparing a GaN monolithic integrated device, comprising the following steps:

[0086] S1. Provide a substrate, which includes a silicon-based substrate 1 and an epitaxial layer 21, an AlGaN layer 22, a first dielectric layer 3a and a second dielectric layer 3b stacked in sequence on the silicon-based substrate 1. One side of the substrate is a GaN HEMT device area A, and the other side is a capacitor area B. The GaN HEMT device area A is provided with a GaN HEMT device having the following structure: a source 5, a p-type GaN layer 6 and a drain 7 are provided on the surface of the AlGaN layer 22 away from the epitaxial layer 21, and a gate 8 is provided on the p-type GaN layer 6. The source 5 and the drain 7 are electrically connected to the first interconnecting metal layer 9a located between the first dielectric layer 3a and the second dielectric layer 3b through the first metal plug 10a respectively. A plurality of second metal plugs 10b penetrate the second dielectric layer 3b and are respectively connected to the first interconnecting metal layer 9a.

[0087] S2. A plurality of first deep trenches 13 are etched by photolithography in the capacitor region B. In the direction from the second dielectric layer 3b to the silicon substrate 1, the depth of the first deep trenches 13 extends from the surface of the second dielectric layer 3b to the inside of the silicon substrate 1.

[0088] S3. Depositing a first isolation layer 11a, a first electrode 12a, and a second isolation layer 11b in sequence on the surface of the structure obtained in step S2.

[0089] S4. The first isolation layer 11a, the first electrode 12a, and the second isolation layer 11b located on the surface of the second dielectric layer 3b in the GaN HEMT device region A are etched away by photolithography.

[0090] S5. Etch the second isolation layer 11b closest to the GaN HEMT device region A through a photolithography process to expose the first electrode 12a.

[0091] S6, depositing a metal layer on the surface of the device structure obtained in step S5; etching the metal layer by photolithography to obtain a second interconnect metal layer 9b, a second electrode 12b and a third electrode 12c. The second interconnect metal layer 9b located in the GaN HEMT device region A is electrically connected to the first metal interconnect layer 9a through the second metal plug 10b.

[0092] S7, depositing a third dielectric layer 3c on the surface of the device structure obtained in step S6, forming a plurality of first through holes in the third dielectric layer 3c by photolithography, and filling each first through hole with metal to form a plurality of third metal plugs 10c. The third dielectric layer 3c is filled inside each first deep trench 13.

[0093] S8, depositing a metal layer on the surface of the device structure obtained in step S7, and etching the metal layer to form a plurality of third interconnected metal layers 9c. The second interconnected metal layer 9b, the second electrode 12b and the third electrode 12c are all electrically connected to the third interconnected metal layer 9c through the third metal plug 10c. The drain 7 and the second electrode 12b (such as Fig.15 as shown) or the third electrode 12c (as shown Fig.11 As shown) an electrical connection is formed through the third interconnect metal layer 9c according to the role of capacitance in the circuit.

[0094] S9, depositing a passivation layer 4 on the surface of the device structure obtained in step S8, and etching the passivation layer 4 to expose the surface of the third interconnect metal layer 9c away from the third dielectric layer 3c.

[0095] Further, refer to Fig.19 In step S3, after depositing the second isolation layer 11b, the step further includes depositing a conductive material. In step S4, the step further includes etching away the conductive material on the surface of the second isolation layer 11b, and retaining the conductive material inside the first deep trench to obtain a conductive filling layer 14.

[0096] Or, refer to Figure 1 , 2 , Figures 12 to 15The present invention provides a method for preparing a GaN monolithic integrated device, comprising the following steps:

[0097] P1. Provide a substrate, which includes a silicon-based substrate 1 and an epitaxial layer 21, an AlGaN layer 22, a first dielectric layer 3a, and a second dielectric layer 3b stacked in sequence on the silicon-based substrate 1. One side of the substrate is a GaN HEMT device region A, and the other side is a capacitor region B. The GaN HEMT device region A is provided with a GaN HEMT device having the following structure: a source 5, a p-type GaN layer 6, and a drain 7 are provided on the surface of the AlGaN layer 22 away from the epitaxial layer 21, and a gate 8 is provided on the p-type GaN layer 6. The source 5 and the drain 7 are electrically connected to a first interconnect metal layer 9a located between the first dielectric layer 3a and the second dielectric layer 3b through a first metal plug 10a, respectively. A plurality of second metal plugs 10b penetrate the second dielectric layer 3b and are each connected to the first interconnect metal layer 9a.

[0098] P2. A plurality of first deep trenches 13 are etched by photolithography in the capacitor region B. In the direction from the second dielectric layer 3b to the silicon substrate 1, the depth of the first deep trenches 13 extends from the surface of the second dielectric layer 3b to the inside of the silicon substrate 1.

[0099] P3. Depositing the first electrode 12a and the second isolation layer 11b in sequence on the surface of the structure obtained in step P2 (eg, ALD deposition).

[0100] P4. The first electrode 12a and the second isolation layer 11b inside and around the opening of the first deep trench 13 farthest from the GaN HEMT device region A and the first electrode 12a and the second isolation layer 11b located in the device region A are etched away.

[0101] P5. Deposit a metal layer on the surface of the structure obtained in step P4, and etch the metal layer by photolithography to obtain a second interconnect metal layer 9b, a second electrode 12b, and a third electrode 12c. The second interconnect metal layer 9b located in the GaN HEMT device region A is electrically connected to the first metal interconnect layer 9a through the second metal plug 10b. The first electrode 12a and the third electrode 12c are electrically connected through the conductive silicon-based substrate 1.

[0102] P6. Deposit a third dielectric layer 3c on the surface of the device structure obtained in step P5, form a plurality of first through holes in the third dielectric layer 3c by photolithography, and fill each first through hole with metal to form a plurality of third metal plugs 10c. The third dielectric layer 3c is filled inside each first deep trench 13.

[0103] P7. Deposit a metal layer on the surface of the device structure obtained in step P6, and etch the metal layer to form a plurality of third interconnect metal layers 9c. The second interconnect metal layer 9b, the second electrode 12b and the third electrode 12c are all electrically connected to the third interconnect metal layer 9c through the third metal plug 10c.

[0104] P8. Deposit a passivation layer 4 on the surface of the device structure obtained in step P7, and etch the passivation layer 4 to expose the surface of the third interconnect metal layer 9c away from the third dielectric layer 3c.

[0105] Or, refer to Figures 20-22 A specific embodiment of the present invention provides a method for preparing a GaN monolithic integrated device, comprising the following steps:

[0106] R1. Provide a substrate, which includes a silicon-based substrate 1 and an epitaxial layer 21, an AlGaN layer 22, a first dielectric layer 3a, a second dielectric layer 3b and a passivation layer 4 stacked in sequence on the silicon-based substrate 1. A source 5, a p-type GaN layer 6 and a drain 7 are arranged on the surface of the AlGaN layer 22 away from the epitaxial layer 21, and a gate 8 is arranged on the p-type GaN layer 6. The source 5 and the drain 7 are electrically connected to the first interconnected metal layer 9a located between the first dielectric layer 3a and the second dielectric layer 3b through the first metal plug 10a respectively. A plurality of fourth interconnected metal layers 9d are arranged between the second dielectric layer 3b and the passivation layer 4. The surface of the fourth interconnected metal layer 9d away from the second dielectric layer 3b is at least partially exposed to the outside and is not covered by the passivation layer 4. A plurality of second metal plugs 10b are arranged in the second dielectric layer 3b, and the first interconnected metal layer 9a and the fourth metal interconnected layer 9d are connected through the second metal plug 10b. The fourth metal plug 10d penetrates the second dielectric layer 3b, the first dielectric layer 3a, the AlGaN layer 22 and the epitaxial layer 21 and extends into the silicon-based substrate 1, and the fourth metal plug 10d is connected to the fourth interconnect metal layer 9d.

[0107] R2. Bond the surface of the passivation layer 4 away from the second dielectric layer 3 b to a carrier, turn the substrate over, and thin the side of the silicon-based substrate 1 away from the epitaxial layer 21 .

[0108] R3. Etch a plurality of first deep trenches 13 on the side of the silicon substrate 1 away from the epitaxial layer 21. The opening of the first deep trench 13 is located on the surface of the silicon substrate 1 away from the epitaxial layer 21, and the top is located inside the silicon substrate 1 and coplanar with the bottom of the fourth metal plug 10d.

[0109] R4, a first electrode 12a, a second isolation layer 11b and a second electrode 12b are sequentially deposited on the inner wall of the first deep trench 13 and the surface of the silicon substrate 1 away from the epitaxial layer 21. The first electrode 12a is electrically connected to the fourth interconnect metal layer 9d through the fourth metal plug 10d, so that the drain 7 of the GaN HEMT device is electrically connected to the first electrode 12a of the capacitor. The carrier is peeled off (for example, by releasing the bonding by ultraviolet light), and a GaN monolithic integrated device is obtained.

[0110] Further, in step R2, the thickness of the silicon-based substrate 1 after thinning is 50-500 μm. For example, the thickness of the silicon-based substrate 1 after thinning is 50 μm, 51 μm, 52 μm, 55 μm, 60 μm, ... 100 μm, 101 μm, 102 μm, 110 μm, 115 μm, 120 μm, 130 μm, ... 200 μm, 205 μm, 210 μm, ... 500 μm; typically 200 μm.

[0111] Further, refer to Fig.23 and Fig.24 , after depositing the second isolation layer 11b in step R4, a conductive material is deposited inside the first deep trench and on the surface of the second isolation layer 11b away from the first electrode 12a, and the conductive material on the surface of the second isolation layer 11b away from the first electrode 12a is etched away, and the conductive material inside the first deep trench is retained to obtain a conductive filling layer 14; then a metal layer is deposited on the surface of the second isolation layer 11b away from the first electrode 12a to obtain the second electrode 12b. Alternatively, after depositing the second isolation layer 11b in step R4, a conductive material is directly evaporated inside the first deep trench to obtain a conductive filling layer 14, and then a metal layer is deposited on the surface of the second isolation layer 11b away from the first electrode 12a to obtain the second electrode 12b.

[0112] As an example, the preparation method of the fourth metal plug 10d is as follows: a second through hole penetrating the second dielectric layer 3b, the first dielectric layer 3a, the AlGaN layer 22 and the epitaxial layer 21 is etched through the TGV process (GaN through-hole process), and the second through hole extends into the silicon-based substrate 1, and metal is filled in the second through hole to form the fourth metal plug 10d.

[0113] As an example, the silicon-based substrate 1 in step S1 or P1 or R1 is a p-type silicon substrate (eg Fig. 9 As shown), n-type silicon substrate (as Fig. 9 As shown), intrinsic silicon substrate, SOI (silicon on insulator) substrate (as shown Fig.10 As shown), the silicon-based substrate 1 includes a bottom silicon 11, an oxide buried layer 12, a top silicon 13), any one of a pn junction silicon substrate (such as Fig.11 shown).

[0114] As an example, when the capacitor in capacitor region B is a bootstrap capacitor, the upper and lower electrodes of the bootstrap capacitor need to be connected to other components in the circuit, and the upper and lower electrode potentials need to be isolated from other components. An SOI substrate with an isolation function can be selected. At this time, the bottom of the first deep trench 13 in step S2 or P2 is located in the insulating layer (or oxide buried layer, such as SiO2) in the top silicon or in the middle. 2 buried layer) (such as Fig.17 and Fig.18 Further, as Fig.16 As shown, in Fig.17 and Fig.18 In the structure, a second deep trench 15 is further etched between the GaN HEMT device region A and the capacitor region B. The first dielectric layer 3a is a multi-layer structure. In the process of preparing the substrate, the multi-layer structure is sequentially deposited on the upper surface of the AlGaN layer 22. Therefore, the second deep trench 15 opens from the upper surface of any layer of the first dielectric layer 3a (except the layer farthest from the AlGaN layer 22) and extends to the insulating layer (or oxide buried layer, such as SiO 2 The second deep trench 15 is in the buried layer, that is, the bottom of the second deep trench 15 is located in the insulating layer of the SOI substrate; the dielectric material is continued to be deposited on the surface of the structural layer with the opening of the second deep trench 15 to complete the production of the first dielectric layer 3a. At this time, the inside of the second deep trench 15 is filled with the first dielectric layer 3a.

[0115] As an example, along the direction from the second dielectric layer to the silicon-based substrate (or along the direction from the silicon-based substrate to the second dielectric layer), the total thickness of the first dielectric layer and the second dielectric layer is 3 to 10 μm, for example, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm; typically 5 μm.

[0116] As an example, along the direction from the second dielectric layer to the silicon-based substrate (or along the direction from the silicon-based substrate to the second dielectric layer), the thickness of the epitaxial layer is 1 to 20 μm. For example, the thickness of the epitaxial layer is 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, ... 10 μm, 11 μm, 12 μm, 13 μm, ... 20 μm, typically 5 μm.

[0117] As an example, along the direction from the second dielectric layer to the silicon-based substrate (or along the direction from the silicon-based substrate to the second dielectric layer), the silicon-based substrate is etched to a depth of 1 to 200 μm. For example, the silicon-based substrate is etched to a depth of 1 μm, 2 μm, 3 μm, 4 μm, ... 100 μm, 101 μm, 102 μm, 110 μm, 115 μm, ... 200 μm.

[0118] As an example, along the direction from the GaN HEMT device region A to the capacitor region B (or along the direction from the capacitor region B to the GaN HEMT device region A), the width of the first deep trench is ˜100 μm, for example, the width is 10 μm; the distance between two adjacent first deep trenches is 0.5˜500 μm, for example, the width is 10 μm.

[0119] As an example, the projection pattern of the capacitor on the plane parallel to the silicon substrate can be any common pattern such as a rectangle, square, hexagon, triangle, circle, etc. (such as Fig.25 shown).

[0120] As an example, the epitaxial layer is a multi-layer structure, including a nucleation layer, a buffer layer, a voltage-resistant layer and a channel layer stacked in sequence.

[0121] Further, as an example, the material of the nucleation layer is AlN.

[0122] Further, as an example, the material of the buffer layer is AlGaN.

[0123] Further, as an example, the material of the voltage-resistant layer is GaN doped with C or Fe.

[0124] Further, as an example, the material of the channel layer is GaN.

[0125] As an example, the material of the first dielectric layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , any one or a combination of polyimide.

[0126] As an example, the material of the second dielectric layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , any one or a combination of polyimide.

[0127] As an example, the material of the third dielectric layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , any one or a combination of polyimide.

[0128] As an example, the main material of each of the first metal plug, the second metal plug and the third metal plug is any one or a combination of tungsten, aluminum and copper, and the surface of the main material is coated with metal Ti and metal TiN.

[0129] As an example, the material of the first isolation layer is SiO 2 、Si 3 N 4 、Al 2 O 3 , at least one of AlN, AlON, and SiON.

[0130] As an example, the thickness of the first isolation layer is 10 to 1000 nm; for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 50 nm, 55 nm, 60 nm...500 nm, 501 nm, 510 nm, 540 nm, 560 nm, 580 nm...1000 nm.

[0131] As an example, the material of the first electrode is any one of Ti, TiN, Au, Al, Ni, Pt, and W, or a combination of several of them.

[0132] As an example, the thickness of the first electrode is 10 to 500 nm, for example, 10 nm, 11 nm, 12 nm, 15 nm, 110 nm...220 nm, 250 nm, 280 nm, 300 nm...500 nm.

[0133] As an example, the material of the second isolation layer is SiO 2 、Si 3 N 4 、Al 2 O 3 , HfO 2 、TiO 2 , Y 2 O 3 、ZrO 3 At least one of them.

[0134] As an example, the thickness of the second isolation layer is 5 to 500 nm, for example, 5 nm, 6 nm, 7 nm, 10 nm, 20 nm, 30 nm, 50 nm, 100 nm, ... 500 nm, preferably 20 nm.

[0135] As an example, the material of the first interconnect metal layer is a Ti / TiN / Al / Ti / TiN stack, or a Ti / Au / Ti stack.

[0136] As an example, the material of the second interconnect metal layer is a Ti / TiN / Al / Ti / TiN stack, or a Ti / Au / Ti stack. Therefore, the materials of the second electrode and the third electrode in step S6 or step P5 are both Ti / TiN / Al / Ti / TiN stack, or a Ti / Au / Ti stack.

[0137] As an example, the material of the third interconnect metal layer is a Ti / TiN / Al / Ti / TiN stack, or a Ti / Au / Ti stack.

[0138] As an example, the material of the conductive filling layer is at least one of n-type polysilicon, p-type polysilicon, tungsten metal, and copper metal.

[0139] As an example, the material of the passivation layer is SiO 2 、Si 3 N 4 、SiON、Al 2 O 3 , and at least one of polyimide.

[0140] As an example, the material of the second electrode in step R4 is any one or a combination of Ti, TiN, Au, Al, Ni, Pt, and W. For example, when the material of the second electrode is a combination material, it can be a Ti / TiN / Al / Ti / TiN stack or a Ti / Au / Ti stack.

[0141] For capacitors with different structures, the structural parameters and performance comparisons are shown in Table 1.

[0142] Table 1 Structural parameters and performance comparison results of capacitors with different structures

[0143]

[0144]

[0145] The structure of capacitor C1 in Table 1 is as follows Fig.26 As shown, Fig.26 The structure layer composed of the surface passivation layer 3a1, the field plate dielectric layer 3a2, and the interlayer dielectric layer 3a3 is equivalent to Fig. 9 The gate 8 is located between the surface passivation layer 3a1 and the field plate dielectric layer 3a2, and the source field plate 16 is located between the field plate dielectric layer 3a2 and the interlayer dielectric layer 3a3. The structure of the capacitor C2 is as follows: Fig. 27 As shown, the structure of capacitor C3 is Fig. 9 The structure shown in FIG. C1, C2, and C3 capacitors have the same structure and the same material as the structural components. Fig.26 and Fig. 27 The dotted line in the figure represents the two-dimensional electron gas (2DEG). It can be seen from Table 1 that the density of the capacitor is significantly improved by adopting the integrated device structure of the present invention.

[0146] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A method for preparing a GaN monolithic integrated device, characterized in that: The following steps are involved: S1. Provide a substrate, the substrate comprising a silicon-based substrate and an epitaxial layer, an AlGaN layer, a first dielectric layer and a second dielectric layer sequentially stacked on the silicon-based substrate; one side of the substrate is a GaN HEMT device region, and the other side is a capacitor region; the GaN HEMT device region is provided with a GaN HEMT device; the source and the drain of the GaN HEMT device are electrically connected to a first interconnecting metal layer located between the first dielectric layer and the second dielectric layer through a first metal plug respectively; a plurality of second metal plugs penetrate the second dielectric layer and are respectively connected to the first interconnecting metal layer; S2, etching a plurality of first deep trenches in the capacitor region; S3, depositing a first isolation layer, a first electrode, and a second isolation layer in sequence on the surface of the structure obtained in step S2; S4, etching away the first isolation layer, the first electrode and the second isolation layer on the surface of the second dielectric layer in the GaN HEMT device region; S5, etching the second isolation layer closest to the GaN HEMT device region A to expose the first electrode; S6, depositing a metal layer on the surface of the device structure obtained in step S5; etching the metal layer to obtain a second interconnect metal layer, a second electrode and a third electrode; the second interconnect metal layer located in the GaN HEMT device region is electrically connected to the first metal interconnect layer through the second metal plug; S7, depositing a third dielectric layer on the surface of the device structure obtained in step S6, opening a plurality of first through holes in the third dielectric layer, and filling each of the first through holes with metal to form a plurality of third metal plugs; S8, depositing a metal layer on the surface of the device structure obtained in step S7, and etching the metal layer to form a plurality of third interconnected metal layers; the second interconnected metal layer, the second electrode and the third electrode are all electrically connected to the third interconnected metal layer through the third metal plug; S9, depositing a passivation layer on the surface of the device structure obtained in step S8, and etching the passivation layer so that the surface of the third interconnect metal layer away from the third dielectric layer is exposed to the outside; Alternatively, the method for preparing the GaN monolithic integrated device comprises the following steps: P1. Provide a substrate, the substrate comprising a silicon-based substrate and an epitaxial layer, an AlGaN layer, a first dielectric layer and a second dielectric layer sequentially stacked on the silicon-based substrate; one side of the substrate is a GaN HEMT device region, and the other side is a capacitor region; the GaN HEMT device region is provided with a GaN HEMT device; the source and drain of the GaN HEMT device are electrically connected to a first interconnecting metal layer located between the first dielectric layer and the second dielectric layer through a first metal plug respectively; a plurality of second metal plugs penetrate the second dielectric layer and are respectively connected to the first interconnecting metal layer; P2, etching a plurality of first deep trenches in the capacitor region; P3, sequentially depositing a first electrode and a second isolation layer on the surface of the structure obtained in step P2; P4, etching away the first electrode and the second isolation layer inside the first deep trench farthest from the GaN HEMT device region and around its opening, as well as the first electrode and the second isolation layer located in the GaN HEMT device region; P5. Depositing a metal layer on the surface of the structure obtained in step P4, and etching the metal layer to obtain a second interconnect metal layer, a second electrode, and a third electrode; the second interconnect metal layer located in the GaN HEMT device region is electrically connected to the first metal interconnect layer through the second metal plug; P6. Depositing a third dielectric layer on the surface of the device structure obtained in step P5, and opening a plurality of first through holes in the third dielectric layer, and filling each of the first through holes with metal to form a plurality of third metal plugs; P7, depositing a metal layer on the surface of the device structure obtained in step P6, and etching the metal layer to form a plurality of third interconnected metal layers; the second interconnected metal layer, the second electrode and the third electrode are all electrically connected to the third interconnected metal layer through the third metal plug; P8, depositing a passivation layer on the surface of the device structure obtained in step P7, and etching the passivation layer so that the surface of the third interconnect metal layer away from the third dielectric layer is exposed; Alternatively, the method for preparing the GaN monolithic integrated device comprises the following steps: R1. Provide a substrate, the substrate comprising a silicon-based substrate and an epitaxial layer, an AlGaN layer, a first dielectric layer, a second dielectric layer and a passivation layer stacked in sequence on the silicon-based substrate; a GaN HEMT device is arranged on the substrate; the source and the drain of the GaN HEMT device are electrically connected to a first interconnected metal layer located between the first dielectric layer and the second dielectric layer through a first metal plug respectively; a plurality of fourth interconnected metal layers are arranged between the second dielectric layer and the passivation layer; the surface of the fourth interconnected metal layer away from the second dielectric layer is at least partially exposed to the outside; the first interconnected metal layer and the fourth metal interconnected layer are connected through a plurality of second metal plugs arranged in the second dielectric layer; the fourth metal plug penetrates the second dielectric layer, the first dielectric layer, the AlGaN layer and the epitaxial layer, and extends into the silicon-based substrate; the fourth metal plug is connected to the fourth interconnected metal layer; R2, bonding the surface of the passivation layer away from the second dielectric layer to a carrier, turning the substrate over, and thinning the side of the silicon-based substrate away from the epitaxial layer; R3, etching a plurality of first deep trenches on a side of the silicon-based substrate away from the epitaxial layer; the top of the first deep trench is located in the silicon-based substrate and is coplanar with the bottom of the fourth metal plug; R4. Depositing a first electrode, a second isolation layer and a second electrode in sequence on the inner wall of the first deep trench and the surface of the silicon-based substrate facing away from the epitaxial layer, and peeling off the carrier; the first electrode is electrically connected to the fourth interconnect metal layer through the fourth metal plug.

2. The preparation method according to claim 1, characterized in that: After depositing the second isolation layer in step S3, the step also includes a step of continuing to deposit a conductive material; step S4 also includes a step of etching away the conductive material on the surface of the second isolation layer, retaining the conductive material inside the first deep trench to obtain a conductive filling layer.

3. The preparation method according to claim 1, characterized in that: In step R4, after depositing the second isolation layer, a conductive filling layer is firstly filled inside the first deep trench, and then the second electrode is deposited.

4. The preparation method according to claim 1, characterized in that: The silicon-based substrate is any one of a p-type silicon substrate, an n-type silicon substrate, an intrinsic silicon substrate, an SOI substrate or a pn junction silicon substrate; or / and the material of the epitaxial layer is a GaN-based material or / and an AlN-based material.

5. The preparation method according to claim 1, characterized in that: The thickness of the epitaxial layer along the direction from the second dielectric layer to the silicon-based substrate or from the silicon-based substrate to the second dielectric layer is 1-20 μm; or / and the silicon-based substrate is etched to a depth of 1-200 μm.

6. The preparation method according to claim 1, characterized in that: The material of the first isolation layer is at least one of SiO2, Si3N4, Al2O3, AlN, AlON, and SiON; or / and the material of the second isolation layer is at least one of SiO2, Si3N4, Al2O3, HfO2, TiO2, Y2O3, and ZrO3.

7. The preparation method according to claim 1, characterized in that: The thickness of the first isolation layer is 10-1000 nm; or / and the thickness of the second isolation layer is 5-500 nm.

8. The preparation method according to claim 1, characterized in that: The material of the first dielectric layer is at least one of SiO2, Si3N4, SiON, Al2O3, and polyimide; or / and the material of the second dielectric layer is at least one of SiO2, Si3N4, SiON, Al2O3, and polyimide.

9. The preparation method according to claim 1, characterized in that: The material of the third dielectric layer is at least one of SiO2, Si3N4, SiON, Al2O3, and polyimide; or / and the material of the passivation layer is at least one of SiO2, Si3N4, SiON, Al2O3, and polyimide.

10. A GaN monolithic integrated device prepared by the preparation method according to any one of claims 1 to 9.

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