Display device

Abstract

A display device is disclosed. The display device includes: a display panel in which a plurality of first pixel regions and a plurality of second pixel regions each including a plurality of sub-pixels are defined; a pixel circuit disposed in each of the plurality of sub-pixels and including a driving transistor; and a solder transistor selectively connecting pixel circuits of first and second pixel regions adjacent to each other among the plurality of first pixel regions and the plurality of second pixel regions. Therefore, the welding transistor is used for further supplying the driving current of the pixel circuit to the light emitting diode of the adjacent sub-pixel so as to improve brightness.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example, but not limited to, to a display device using a light emitting diode (LED). Background Art

[0002] As display devices for monitors of computers, televisions or cellular phones, there are organic light emitting display devices (OLED) which are self-luminous devices, plasma display devices (PDP), field emission display devices (FED), micro LED (micro light emitting diode) display devices, and liquid crystal display devices (LCD) which require a separate light source, etc.

[0003] The application range of the display device is diversified to personal digital assistants as well as monitors of computers and televisions and display devices having a large display area and reduced volume and weight are being studied.

[0004] In addition, recently, a display device including a light emitting diode (LED) has attracted attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, it has excellent reliability, making its life longer than that of a liquid crystal display device or an organic light emitting display device. In addition, LED has a fast lighting speed, excellent luminous efficiency, and strong impact resistance, making it excellent in stability and able to display images with high brightness.

[0005] The description provided in the description of the background technology section should not be assumed to be prior art simply because it is mentioned in the description of the background technology section or is associated with the description of the background technology section. The description of the background technology section may include information describing one or more aspects of the subject technology, and the description in this part does not limit the present invention. Summary of the invention

[0006] The inventors have recognized the requirements and limitations in the resolution of display devices. Therefore, one object to be achieved by the present disclosure is to provide a display device that can be driven in both a high-resolution mode and a low-resolution mode.

[0007] Another object to be achieved by the present disclosure is to provide a display device that can be driven in both a high grayscale mode and a low grayscale mode in a low-resolution model display device.

[0008] Still another object to be achieved by the present disclosure is to provide a display device that is implemented from a display device designed with a high resolution to a low resolution model.

[0009] Another object to be achieved by the present disclosure is to provide a display device capable of adjusting the resolution according to the specifications of the spliced ​​display device.

[0010] Still another object to be achieved by the present disclosure is to provide a display device in which a display device dedicated to a high-resolution mode and a display device dedicated to a low-resolution mode are unified to reduce manufacturing costs and process time.

[0011] Still another object to be achieved by the present disclosure is to provide a display device which selectively transfers light emitting diodes to only some of a plurality of sub-pixels to be driven at a low resolution.

[0012] Still another object to be achieved by the present disclosure is to provide a display device capable of supplying a high current to a light emitting diode by connecting a pixel circuit of a sub-pixel to which the light emitting diode is not transferred to a light emitting diode of another sub-pixel in a low-resolution model.

[0013] Still another object to be achieved by the present disclosure is to provide a display device which easily displays a high grayscale image by supplying a high current to a light emitting diode in a low resolution model.

[0014] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0015] According to one aspect of the present disclosure, a display device includes: a display panel, in which a plurality of first pixel regions and a plurality of second pixel regions are defined, each of the plurality of first pixel regions and the plurality of second pixel regions including a plurality of sub-pixels; a pixel circuit, the pixel circuit being arranged in each of the plurality of sub-pixels and including a driving transistor; and a welding transistor, the welding transistor selectively connecting the pixel circuits of the first pixel region and the second pixel region adjacent to each other among the plurality of first pixel regions and the plurality of second pixel regions. Therefore, the welding transistor is used to further supply the driving current of the pixel circuit to the light-emitting diode of the adjacent sub-pixel to increase the brightness.

[0016] According to another aspect of the present disclosure, a display device includes: a substrate in which a plurality of first pixel regions and a plurality of second pixel regions are defined, each of the plurality of first pixel regions and the plurality of second pixel regions including a plurality of sub-pixels; a plurality of pixel circuits disposed in each of the plurality of sub-pixels on the substrate and including a driving transistor; a plurality of reflecting plates disposed in each of the plurality of sub-pixels on the plurality of pixel circuits and electrically connected to the driving transistor of each of the plurality of pixel circuits; and a plurality of welding transistors disposed between the plurality of first pixel regions and the plurality of second pixel regions and selectively connecting the plurality of reflecting plates of the plurality of first pixel regions and the plurality of reflecting plates of the plurality of second pixel regions. Therefore, the reflecting plates connected to the driving transistors are used to easily electrically connect the driving transistors of adjacent pixel circuits.

[0017] Additional details of example embodiments are included in the Detailed Description and the Drawings.

[0018] According to the present disclosure, the display device can be driven in any one of a high-resolution mode and a low-resolution mode.

[0019] According to the present disclosure, the display device may be driven in any one of a high grayscale mode and a low grayscale mode in a low-resolution model display device.

[0020] According to the present disclosure, the resolution of the display device is easily adjusted according to the specifications of the spliced ​​display device.

[0021] According to the present disclosure, during driving in a low-resolution mode, pixel circuits of sub-pixels that do not emit light are selectively connected to light-emitting diodes to display a high-brightness image.

[0022] According to the present disclosure, designs of a low-resolution model display device and a high-resolution model display device are unified to optimize the process and reduce the process time and manufacturing cost.

[0023] According to the present disclosure, light emitting diodes are selectively transferred to only some sub-pixels to easily form a low-resolution model display device.

[0024] According to the present disclosure, pixel circuits in a region where a light emitting diode is not transferred are selectively connected to the light emitting diode to easily display a high grayscale image.

[0025] The effects according to the present disclosure are not limited to the contents exemplified above, and more various effects are included in the present disclosure.

[0026] Other systems, methods, features, and advantages will or will become apparent to those skilled in the art upon reviewing the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included in this description, to be within the scope of the present disclosure, and to be protected by the following claims. Nothing in this section shall be construed as limiting these claims. Further aspects and advantages are discussed below in conjunction with embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 3 is an enlarged plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 4 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 5A is along Figure 3 A cross-sectional view taken along the line Va-Va';

[0034] Figure 5B is along Figure 3 A cross-sectional view taken at Vb-Vb';

[0035] Figure 6 and Figure 7 is an exemplary circuit diagram of a pixel circuit of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0036] Figure 8 is a driving timing diagram of a display device according to an exemplary embodiment of the present disclosure;

[0037] Fig. 9 is an enlarged plan view of a display panel of a display device according to another exemplary embodiment of the present disclosure;

[0038] Fig.10 and Fig.11is an exemplary circuit diagram of a pixel circuit of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure; and

[0039] Fig.12 is a driving timing diagram of a display device according to another exemplary embodiment of the present disclosure.

[0040] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0041] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, when it is determined that a detailed description of well-known functions or configurations associated with this document unnecessarily obscures the main points of the inventive concept, its detailed description will be omitted. The described progression of processing steps and / or operations is an example; however, the order of steps and / or operations is not limited to the order described herein and may be changed as known in the art, except for steps and / or operations that must occur in a specific order. Similar reference numerals always represent similar elements. The names of the various elements used in the following description may be selected solely for the convenience of writing the specification and may therefore differ from the names used in the actual product.

[0042] By referring to the following and attached Figure 1 The advantages and features of the present disclosure and the methods for achieving the advantages and features will be clear from the exemplary embodiments described in detail. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0043] The shapes, sizes, areas, ratios, angles, quantities, etc. shown in the drawings used to describe the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, a detailed explanation of known related technologies may be omitted or may be briefly provided to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed of", "composed of" are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0044] Any implementation described herein as "exemplary" is not necessarily to be construed as optimal or advantageous over other implementations.

[0045] When the terms “including,” “having,” and “comprising” may be used in the present disclosure, another component may be added unless a more restrictive term such as “only” is used. Terms in the singular form may include plural forms unless otherwise specified.

[0046] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0047] When terms such as "on," "over," "above," "under," "beside," "under," "near," "near," "adjacent," "on the side of," and "close" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the terms "immediately" or "directly."

[0048] Spatially relative terms, such as "below," "below," "under," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if the elements in the figures are inverted, elements described as "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary term "below" may include both below and above orientations. Similarly, the exemplary terms "above" or "above" may include both "above" and "below" orientations.

[0049] When describing a temporal relationship, terms such as "after", "subsequently", "next", "following", "before", etc. may include any situation where two events are not consecutive, unless terms such as "immediately", "directly" or "directly" are explicitly used.

[0050] When an element or layer is disposed “on” another element or layer, the further layer or element may be interposed directly on the other element or layer or between the element or layer and the other element or layer.

[0051] Although the terms "first", "second", "A", "B", "a", and "b" etc. are used to describe various components, the components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0052] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to limit the nature, order or sequence of the corresponding components, but is only used to distinguish the corresponding components from other components. In the case of describing that a certain structural element or layer is "connected", "coupled", "bonded" or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer can be directly or indirectly "connected", "coupled", "bonded" or "joined" to the structural element or layer.

[0053] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0054] The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light emitting diodes (LEDs), etc. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as complete electronic devices (or devices) or complete sets of devices (or devices) including LEDs, etc. as complete products or final products, for example, mobile electronic devices such as smart phones or electronic tablets, but embodiments of the present disclosure are not limited thereto.

[0055] Like reference numbers generally refer to like elements throughout the specification.

[0056] For convenience of description, the size and thickness of each component shown in the drawings are shown, and the present disclosure is not limited to the size and thickness of the components shown.

[0057] The features of the various embodiments of the present disclosure may be partially or completely attached or combined with each other, and may be interlocked and operated in various ways technically, and the embodiments may be performed independently or in association with each other.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0059] In aspects of the present disclosure, for ease of description, source electrodes and drain electrodes are distinguished from each other. However, source electrodes and drain electrodes may be used interchangeably. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. In addition, a source electrode in any aspect of the present disclosure may be a drain electrode in another aspect of the present disclosure, and a drain electrode in any aspect of the present disclosure may be a source electrode in another aspect of the present disclosure.

[0060] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For the convenience of description, the proportion of each element shown in the accompanying drawings is different from the actual proportion, and therefore is not limited to the proportion shown in the accompanying drawings.

[0061] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure. Figure 1 In the embodiment, for the convenience of description, among the various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD and the timing controller TC are illustrated, but the components of the display device 100 of the present disclosure are not limited thereto. In addition, all components of each display device according to all embodiments of the present disclosure are operably connected and configured.

[0062] Reference Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD supplying various signals to the display panel PN; and a timing controller TC controlling the gate driver GD and the data driver DD.

[0063] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 In the embodiment, one gate driver GD is provided to be spaced apart from one side of the display panel PN, but the number and arrangement of the gate drivers GD are not limited thereto. For example, two gate drivers GD may be provided on both sides of the display panel PN, respectively, and spaced apart from the display panel PN. However, the embodiments of the present disclosure are not limited thereto.

[0064] The data driver DD converts the image data input from the timing controller TC into data voltages using a reference gamma voltage according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL. The data driver DD may be implemented in the form of an integrated circuit (IC), and the gate driver GD may be implemented in a display panel in a gate-in-panel (GIP) type.

[0065] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals (such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. Here, the horizontal synchronization signal is a signal indicating the time taken for one horizontal line of the display screen, and the vertical synchronization signal is a signal indicating the time taken for one frame of the display screen. The data enable signal may correspond to a signal indicating a period of supplying a data voltage to the pixel PX. In addition, the timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0066] The display panel PN is a configuration for displaying an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, even though not shown in the figure, each of the plurality of sub-pixels SP may be connected to a high potential power line, a low potential power line, and a reference line.

[0067] In the display panel PN, a display area AA and a non-display area NA disposed near, surrounding, or around the display area AA may be defined.

[0068] The display area AA is an area where an image is displayed in the display device 100. In the display area AA, a plurality of pixel areas may be arranged in a matrix form along a plurality of row lines and column lines. The plurality of pixel areas may include pixel areas that display different colors (e.g., red (R), green (G) and blue (B) or red (R), green (G), blue (B) and white). At this time, mutually adjacent red (R), green (G) and blue (B) pixel areas or mutually adjacent red (R), green (G), blue (B) and white pixel areas may be used as unit pixels for displaying color images. In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units constituting the display area AA, and n sub-pixels SP form one pixel PX. Each of the plurality of sub-pixels SP may emit light having different wavelengths from each other. The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel and a third sub-pixel that emit light of different colors from each other. For example, the plurality of sub-pixels SP may include a red sub-pixel SPR as a first sub-pixel, a green sub-pixel SPG as a second sub-pixel, and a blue sub-pixel SPB as a third sub-pixel. In addition, the plurality of sub-pixels SP may further include a white sub-pixel.

[0069] For example, a plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeated manner. Alternatively, a plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, wherein the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeated manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be arranged sequentially along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be arranged sequentially along the row direction. However, in the example embodiments of the present disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited, and may be configured in various forms according to the luminous characteristics, device life, and device specifications.

[0070] In addition, the sub-pixels may have different light-emitting areas according to the light-emitting characteristics. For example, a sub-pixel emitting light of a color different from the color of the blue sub-pixel may have a light-emitting area different from the light-emitting area of ​​the blue sub-pixel. For example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel, or a red sub-pixel, a blue sub-pixel, a white sub-pixel, and a green sub-pixel may each have a different light-emitting area.

[0071] In each of the plurality of sub-pixels SP, a light emitting diode and a thin film transistor for driving the light emitting diode may be provided. Depending on the type of the display panel PN, the plurality of light emitting diodes may be defined in different ways. For example, when the display panel PN is an inorganic light emitting display panel PN, the light emitting diode may be a light emitting diode (LED) or a micro light emitting diode (micro LED), and when the display panel PN is an organic light emitting display panel, the light emitting element may be an organic light emitting diode (OLED), and the embodiments of the present disclosure are not limited thereto.

[0072] In the display area AA, a plurality of wirings for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of wirings may include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP and a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the display area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the display area AA to be connected to the plurality of sub-pixels SP. In addition, in the display area AA, a low potential power line and a high potential power line may also be provided, but are not limited thereto.

[0073] One sub-pixel SP constituting the unit pixel may include a switching thin film transistor SW, a driving thin film transistor DR, a storage capacitor Cst, a compensation circuit CC, and a light emitting diode (LED).

[0074] The switching thin film transistor SW may perform a switching operation in response to a scan signal supplied through the first gate line to store a data signal supplied through the first data line as a data voltage in the storage capacitor Cst. The driving thin film transistor DR may operate according to the data voltage stored in the storage capacitor Cst to flow a driving current between a first power line (e.g., a high potential voltage line) and a second power line (e.g., a low potential voltage line). The light emitting diode (LED) may operate according to the driving current formed by the driving thin film transistor DR to emit light.

[0075] The compensation circuit CC is a circuit added in the sub-pixel for compensating the threshold voltage of the driving thin film transistor DR. The compensation circuit CC may include one or more thin film transistors. The compensation circuit CC may have various configurations according to the compensation method, so an example thereof will be described below.

[0076] The non-display area NA is an area where no image is displayed, so that the non-display area NA may be defined as an area extending from the display area AA. In the non-display area NA, a link line, a pad electrode, or a driver IC such as a gate driver IC or a data driver IC that transmits a signal to the sub-pixel SP of the display area AA may be disposed.

[0077] However, the non-display area NA may be located on the rear surface of the display panel PN, ie, on a surface where the sub-pixels SP are not disposed, or may be omitted, and is not limited to what is illustrated in the drawings.

[0078] In addition, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-display area NA in a gate-in-panel (GIP) manner, or may be installed between a plurality of sub-pixels SP in the display area AA in a gate-in-display area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards. The data driver DD and the timing controller TC are electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to the pad electrodes formed in the non-display area NA of the display panel PN. However, embodiments of the present disclosure are not limited thereto.

[0079] If the gate driver GD is installed in a GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode of the non-display area NA, the area of ​​the non-display area NA for disposing the gate driver GD and the pad electrode must be larger than a predetermined level. Therefore, the bezel may increase.

[0080] In contrast, the gate driver GD is installed in the display area AA in a GIA manner, and a side line SRL is formed to connect the signal line on the front surface of the display panel PN to the pad electrode on the rear surface of the display panel PN to bond the flexible film and the printed circuit board to the rear surface of the display panel PN. At this time, on the front surface of the display panel PN, the non-display area NA can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero border substantially without a border can be realized or implemented.

[0081] Specifically, refer to Figure 2A and Figure 2B In the non-display area NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to the plurality of sub-pixels SP are provided. For example, in the non-display area NA on the front surface of the display panel PN, a first pad electrode PAD1 for transmitting signals to the plurality of sub-pixels SP is provided. In the non-display area NA on the rear surface of the display panel PN, a second pad electrode PAD2 electrically connected to a driving component such as a flexible film and a printed circuit board is provided. That is, on the front surface of the display panel PN displaying an image, only the pad area of ​​the non-display area NA in which the first pad electrode PAD1 is provided may be formed to a minimum.

[0082] In this case, even though not shown in the drawings, various signal lines (eg, scan lines SL or data lines DL) connected to the plurality of sub-pixels SP extend from the display area AA to the non-display area NA to be electrically connected to the first pad electrode PAD1.

[0083] In addition, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, a signal transmission path is formed from the front surface of the display panel PN to the side surface and the rear surface to minimize the area of ​​the non-display region NA on the front surface of the display panel PN.

[0084] Reference Figure 2B, a spliced ​​display device TD with a large screen size can be realized by connecting a plurality of display devices 100. Figure 2A As shown, when the spliced ​​display device TD is implemented using the display device 100 having a minimized frame, a seam area in which an image between the display devices 100 is not displayed is minimized, so that the display quality can be improved.

[0085] For example, a plurality of sub-pixels SP form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Therefore, a constant distance D1 between pixels PX between display devices 100 is configured to minimize a seam area.

[0086] However, Figure 2A and Figure 2B It is illustrative so that the display device 100 according to the exemplary embodiment of the present disclosure may be a general display device having a bezel, but is not limited thereto.

[0087] Figure 3 is an enlarged plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure. Figure 4 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 5A is along Figure 3 A cross-sectional view taken along line Va-Va'. Figure 5B is along Figure 3 Specifically, Figure 5A and Figure 5B is a cross-sectional view of a welding transistor WT according to an exemplary embodiment of the present disclosure. Figure 3 In the embodiment, only a plurality of reflecting plates RF, a plurality of light emitting diodes LED and a plurality of welding transistors WT are illustrated, and in Figure 4 , only the driving transistor in the configuration of the pixel circuit PC is illustrated.

[0088] First, the display device 100 according to the exemplary embodiment of the present disclosure can be driven in any one of a high-resolution mode and a low-resolution mode. In the high-resolution mode, all of the plurality of pixels PX are driven to display a high-resolution image, and in the low-resolution mode, only some of the plurality of pixels PX are driven to display a low-resolution image. The resolution varies according to the number of pixels PX used to display one image. Therefore, the resolution of the image to be displayed can be adjusted by selectively driving the plurality of pixels PX. For example, as the number of driven pixels PX increases, the resolution of the image to be displayed increases.

[0089] Reference Figure 3 , a plurality of pixel areas UPA are formed in the display panel PN. The plurality of pixel areas UPA are areas where a plurality of pixels PX are disposed. The plurality of pixel areas UPA may be disposed by forming a plurality of rows and a plurality of columns. Each of the plurality of pixels PX disposed in the plurality of pixel areas UPA includes a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light emitting diode LED and a pixel circuit PC to emit light independently.

[0090] The plurality of pixel areas UPA include a plurality of first pixel areas UPA1 and a plurality of second pixel areas UPA2. When the display device 100 is driven, the plurality of first pixel areas UPA1 are always driven. That is, the plurality of first pixel areas UPA1 are areas that always display images in both high-resolution mode and low-resolution mode. When the display device 100 is driven, the plurality of second pixel areas UPA2 are selectively driven, and the plurality of second pixel areas UPA2 are driven in high-resolution mode but not in low-resolution mode. For example, in high-resolution mode, both the plurality of first pixel areas UPA1 and the plurality of second pixel areas UPA2 are driven, and in low-resolution mode, only the plurality of first pixel areas UPA1 are driven, while the plurality of second pixel areas UPA2 are not driven. However, the present disclosure is not limited thereto, and only the plurality of second pixel areas UPA2 may be driven.

[0091] The arrangement of the plurality of first pixel areas UPA1 and the plurality of second pixel areas UPA2 may be designed in various forms according to the resolution. For example, the plurality of first pixel areas UPA1 and the plurality of second pixel areas UPA2 may be arranged alternately in the row direction and the column direction, or in any one of the row direction and the column direction. Figure 3 , it is illustrated that the first pixel area UPA1 and the second pixel area UPA2 are disposed in different rows, but this is illustrative and the present disclosure is not limited thereto, for example, the first pixel area UPA1 and the second pixel area UPA2 may be disposed in different columns.

[0092] A plurality of sub-pixels SP forming one pixel PX are disposed in each of the plurality of pixel areas UPA. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4 that emit light of different colors. For example, the first sub-pixel SP1 and the second sub-pixel SP2 are red sub-pixels, the third sub-pixel SP3 is a green sub-pixel, and the fourth sub-pixel SP4 is a blue sub-pixel, but is not limited thereto.

[0093] Hereinafter, description is made by assuming that one pixel PX includes one first subpixel SP1, one second subpixel SP2, one third subpixel SP3, and one fourth subpixel SP4, ie, two red subpixels, one green subpixel, and one blue subpixel. However, the configuration of the pixel PX is not limited thereto.

[0094] Also refer to Figure 3 and Figure 4 In each of the multiple sub-pixels SP of the display panel PN of the display device 100 according to the exemplary embodiment of the present disclosure, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a third interlayer insulating layer 115, a first planarization layer 116, an adhesive layer 117, a second planarization layer 118, a third planarization layer 119, a driving transistor DT, a light emitting diode LED, a plurality of reflective plates RF, a first connection electrode CE1, a second connection electrode CE2, a light shielding layer LS and an auxiliary electrode LE are provided.

[0095] First, the substrate 110 is a component for supporting various components included in the display device 100, and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be configured to include a polymer or plastic or may be formed of a flexible material. For example, the substrate 110 may be made of a flexible polymer film, and the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyether sulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA) and polystyrene (PS), and the present disclosure is not limited thereto.

[0096] A light shielding layer LS is disposed in each of the plurality of sub-pixels SP on the substrate 110. The light shielding layer LS blocks light incident on a driving active layer ACT of a driving transistor DT to be described below under the substrate 110. Light incident on the driving active layer ACT of the driving transistor DT is blocked by the light shielding layer LS to minimize leakage current.

[0097] The buffer layer 111 is disposed on the substrate 110 and the light shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the buffer layer 111 may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, but is not limited thereto.

[0098] A pixel circuit PC including a driving transistor DT is disposed on a substrate 110. The pixel circuit PC is a circuit including a driving transistor DT, some other transistors, and a capacitor for driving a light emitting diode LED. For example, the pixel circuit PC may further include a driving transistor DT, a switching transistor, a sensing transistor, and a light emitting control transistor to supply a driving current to the light emitting diode LED. Transistors and capacitors other than the driving transistor DT among the plurality of transistors included in the pixel circuit PC may be configured in various forms according to design, and the present disclosure is not limited thereto.

[0099] The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes a driving active layer ACT, a driving gate electrode GE, a driving source electrode SE, and a driving drain electrode DE.

[0100] The driving active layer ACT is disposed on the buffer layer 111. The driving active layer ACT may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0101] Oxide semiconductor materials can have excellent effects of preventing leakage current and relatively cheap manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and combinations of their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but are not limited thereto.

[0102] The polycrystalline semiconductor material has a fast moving speed of carriers such as electrons and holes, and thus has high mobility, and has low power consumption and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si), but is not limited thereto.

[0103] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0104] In addition, even if not shown in the drawings, other transistors other than the driving transistor DT, such as a switching transistor, a sensing transistor, and a light emission control transistor, may be further provided on the buffer layer 111. The active layer of the transistor is also formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. In addition, the active layers of transistors such as the driving transistor DT, the switching transistor, the sensing transistor, and the light emission control transistor included in the pixel circuit PC may be formed of the same material, or may be formed of different materials.

[0105] Next, a gate insulating layer 112 is disposed on the driving active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the driving active layer ACT from the driving gate electrode GE, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the gate insulating layer 112 may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0106] The driving gate electrode GE is disposed on the gate insulating layer 112. The driving gate electrode GE may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto. As an example, the driving gate electrode GE may be made of an alloy of two or more thereof, or a multilayer thereof, but is not limited thereto.

[0107] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the driving gate electrode GE. In the first interlayer insulating layer 113 and the second interlayer insulating layer 114, contact holes through which the driving source electrode SE and the driving drain electrode DE are connected to the driving active layer ACT are formed. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting components under the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto. For example, each of the first interlayer insulating layer 113 and the second interlayer insulating layer 114 can be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited to this.

[0108] A driving source electrode SE and a driving drain electrode DE electrically connected to the driving active layer ACT are disposed on the second interlayer insulating layer 114. The driving source electrode SE and the driving drain electrode DE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0109] In addition, in the present disclosure, the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are described, that is, multiple insulating layers are provided between the driving gate electrode GE and the driving source electrode SE and the driving drain electrode DE. However, the present disclosure is not limited thereto, and only one insulating layer may be provided between the driving gate electrode GE and the driving source electrode SE and the driving drain electrode DE.

[0110] Further, as shown in the figure, when a plurality of insulating layers such as the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are provided between the driving gate electrode GE and the driving source electrode SE and the driving drain electrode DE, an electrode may be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode may form a capacitor together with other structures provided under the first interlayer insulating layer 113 or over the second interlayer insulating layer 114.

[0111] The auxiliary electrode LE is disposed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light shielding layer LS under the buffer layer 111 to any one of the driving source electrode SE and the driving drain electrode DE on the second interlayer insulating layer 114. For example, the light shielding layer LS is electrically connected to any one of the driving source electrode SE or the driving drain electrode DE through the auxiliary electrode LE so as not to operate as a floating gate. Therefore, the fluctuation of the threshold voltage of the driving transistor DT caused by the floating light shielding layer LS can be minimized. Although in the figure, the light shielding layer LS is connected to the driving source electrode SE, the light shielding layer LS may also be connected to the driving drain electrode DE, but is not limited thereto.

[0112] The third interlayer insulating layer 115 is disposed on the driving transistor DT. The third interlayer insulating layer 115 is disposed to cover the pixel circuit PC including the driving transistor DT to protect the pixel circuit PC. The third interlayer insulating layer 115 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the third interlayer insulating layer 115 may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0113] The first planarization layer 116 is disposed on the third interlayer insulating layer 115. The first planarization layer 116 may planarize the upper portion of the substrate 110 on which the driving transistor DT is disposed. The first planarization layer 116 may be composed of a single layer or a double layer and may be formed of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0114] Refer to Figure 3 and Figure 4 , a plurality of reflective plates RF are disposed on the first planarization layer 116. The reflective plate RF is a configuration that reflects light emitted from a plurality of light emitting diodes LED above the substrate 110, and may be formed to have a shape corresponding to each of a plurality of sub-pixels SP. A reflective plate RF may be provided to cover most of the area of ​​a sub-pixel SP. The reflective plate RF reflects light emitted from the light emitting diode LED, and may also be used as an electrode that electrically connects the light emitting diode LED and the pixel circuit PC. Therefore, in consideration of light reflection efficiency and resistance, the reflective plate RF may include various conductive layers. For example, the reflective plate RF may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, and a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the structure of the reflective plate RF is not limited thereto.

[0115] The reflection plate RF includes a first reflection plate RF1 corresponding to the first sub-pixel SP1, a second reflection plate RF2 corresponding to the second sub-pixel SP2, a third reflection plate RF3 corresponding to the third sub-pixel SP3, and a fourth reflection plate RF4 corresponding to the fourth sub-pixel SP4.

[0116] The first reflector RF1 overlaps the first sub-pixel SP1. The first reflector RF1 can reflect light emitted from the red light emitting diode 120 of the first sub-pixel SP1 to above the red light emitting diode 120. Further, the first reflector RF1 is electrically connected to the driving transistor DT through a contact hole formed in the first planarization layer 116 and the third interlayer insulating layer 115 to transmit the driving current from the driving transistor DT to the red light emitting diode 120.

[0117] The second reflector RF2 overlaps the second sub-pixel SP2. The second reflector RF2 can reflect light emitted from the red light emitting diode 120 of the second sub-pixel SP2 to above the red light emitting diode 120. Further, the second reflector RF2 is electrically connected to the driving transistor DT through a contact hole formed in the first planarization layer 116 and the third interlayer insulating layer 115 to transmit the driving current from the driving transistor DT to the red light emitting diode 120.

[0118] The third reflector RF3 overlaps the third sub-pixel SP3. The third reflector RF3 can reflect light emitted from the green light emitting diode 130 of the third sub-pixel SP3 to above the green light emitting diode 130. The third reflector RF3 is electrically connected to the driving transistor DT through a contact hole formed in the first planarization layer 116 and the third interlayer insulating layer 115 to transmit the driving current from the driving transistor DT to the green light emitting diode 130.

[0119] The fourth reflector RF4 overlaps the fourth sub-pixel SP4. The fourth reflector RF4 may reflect light emitted from the blue light emitting diode 140 of the fourth sub-pixel SP4 to above the blue light emitting diode 140. The fourth reflector RF4 is electrically connected to the driving transistor DT through a contact hole formed in the first planarization layer 116 and the third interlayer insulating layer 115 to transmit a driving current from the driving transistor DT to the blue light emitting diode 140.

[0120] The adhesive layer 117 is provided on the plurality of reflective plates RF. The adhesive layer 117 is formed on the front surface of the substrate 110 to fix the light emitting diode LED provided on the adhesive layer 117. The adhesive layer 117 may be formed of a light-curable adhesive material by light curing. For example, the adhesive layer 117 may be selected from any one of an adhesive polymer, an epoxy resin resist, a UV resin, a polyimide, an acrylate, a polyurethane, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0121] In addition, even if not shown in the figure, a first passivation layer may be further provided between the adhesive layer 117 and the plurality of reflective plates RF. The first passivation layer is an insulating layer for protecting the components below the first passivation layer and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the first passivation layer may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0122] In addition, a second passivation layer may be provided on the plurality of reflective plates RF, the second passivation layer being an insulating layer for protecting components below the second passivation layer, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the second passivation layer may be formed by a single layer or multiple layers of an inorganic film, for example, a single layer of the inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and a multilayer of the inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0123] A plurality of light emitting diodes LED are disposed in each of the plurality of sub-pixels SP on the adhesive layer 117. The light emitting diode LED is an element that emits light by current. The light emitting diode LED includes a red light emitting diode 120 that emits red light, a green light emitting diode 130 that emits green light, and a blue light emitting diode 140 that emits blue light, and realizes light having various colors including white through a combination thereof. For example, the light emitting diode LED may be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0124] A red light emitting diode 120 is arranged in each of the first sub-pixel SP1 and the second sub-pixel SP2, a pair of green light emitting diodes 130 is arranged in the third sub-pixel SP3, and a pair of blue light emitting diodes 140 is arranged in the fourth sub-pixel SP4. That is, two red light emitting diodes 120, two green light emitting diodes 130 and two blue light emitting diodes 140 can be arranged in one pixel PX. At this time, each red light emitting diode 120 is respectively connected to the driving transistor DT of each of the first sub-pixel SP1 and the second sub-pixel SP2 to be driven individually. In contrast, a pair of green light emitting diodes 130 of the third sub-pixel SP3 and a pair of blue light emitting diodes 140 of the fourth sub-pixel SP4 are respectively connected in parallel to a driving transistor DT to be driven. For example, a pair of green light emitting diodes 130 of the third sub-pixel SP3 is connected in parallel to a driving transistor DT to be driven, and a pair of blue light emitting diodes 140 of the fourth sub-pixel SP4 is connected in parallel to a driving transistor DT to be driven.

[0125] Hereinafter, the red light emitting diode 120 disposed in the first sub-pixel SP1 is described as an example, and the green light emitting diode 130 and the blue light emitting diode 140 are also formed by substantially the same structure as the red light emitting diode.

[0126] Among the plurality of light emitting diodes LED, the red light emitting diode 120 includes a first semiconductor layer 121 , a light emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 and a second electrode 125 .

[0127] The first semiconductor layer 121 is disposed on the adhesive layer 117, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers in which n-type impurities and p-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurity may be silicon (Si), germanium (Ge), and tin (Sn), but is not limited thereto.

[0128] The light emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. Holes and electrons are supplied from the first semiconductor layer 121 and the second semiconductor layer 123 to the light emitting layer 122 to emit light. The light emitting layer 122 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0129] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode electrically connecting the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be composed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0130] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode electrically connecting any one of the high potential power line VDD or the low potential power line VSS and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be composed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0131] Next, an encapsulation layer 126 is provided to surround the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation layer 126 is formed of an insulating material to protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. In the encapsulation layer 126, contact holes exposing the first electrode 124 and the second electrode 125 are formed to electrically connect the first connection electrode CE1 and the second connection electrode CE2 to the first electrode 124 and the second electrode 125.

[0132] In addition, part of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation layer 126. The light emitting diode LED manufactured on the wafer is separated from the wafer so as to be transferred to the display panel PN. However, in the process of separating the light emitting diode LED from the wafer, a part of the encapsulation layer 126 may be torn. For example, in the process of separating the light emitting diode LED from the wafer, a part of the encapsulation layer 126 adjacent to the lower edge of the first semiconductor layer 121 of the light emitting diode LED is torn. Therefore, a part of the lower side surface of the first semiconductor layer 121 may be exposed to the outside. Even if the lower part of the light emitting diode LED is exposed from the encapsulation layer 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after forming the second planarization layer 118 and the third planarization layer 119 covering the side surface of the first semiconductor layer 121. Therefore, short circuit defects can be reduced.

[0133] Next, the second planarization layer 118 and the third planarization layer 119 are disposed on the adhesive layer 117 and the light emitting diode LED.

[0134] The second planarization layer 118 overlaps a portion of the side surface of the plurality of light emitting diodes LED to fix and protect the plurality of light emitting diodes LED. The torn portion of the encapsulation layer 126 protecting the side surface of the first semiconductor layer 121 of the light emitting diode LED is covered by the second planarization layer 118. By doing so, contact and short circuit defects of the connection electrode and the first semiconductor layer 121 can be suppressed thereafter.

[0135] The third planarization layer 119 is formed to cover the second planarization layer 118 and the upper portion of the light emitting diode LED. A contact hole exposing the first electrode 124 and the second electrode 125 of the light emitting diode LED may be formed in the third planarization layer 119. The first electrode 124 and the second electrode 125 of the light emitting diode LED are exposed from the third planarization layer 119, and the third planarization layer 119 is partially disposed in a region between the first electrode 124 and the second electrode 125 to reduce a short circuit defect. The second planarization layer 118 and the third planarization layer 119 may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0136] The first connection electrode CE1 and the second connection electrode CE2 are disposed on the third planarization layer 119. The second connection electrode CE2 is an electrode that electrically connects the second electrode 125 of the light emitting diode LED and the electric power line. The second connection electrode CE2 is electrically connected to the second electrode 125 of the light emitting diode LED through a contact hole formed in the third planarization layer 119. However, embodiments of the present disclosure are not limited thereto.

[0137] The first connection electrode CE1 is an electrode electrically connecting the first electrode 124 of the light emitting diode LED and the driving transistor DT. The first connection electrode CE1 may be connected to the first reflection plate RF1, the second reflection plate RF2, the third reflection plate RF3, and the fourth reflection plate RF4 of each of the plurality of sub-pixels SP through a contact hole. The contact hole is formed in the third planarization layer 119, the second planarization layer 118, and the adhesive layer 117. At this time, the first reflection plate RF1, the second reflection plate RF2, the third reflection plate RF3, and the fourth reflection plate RF4 are also connected to the driving source electrode SE of the driving transistor DT, so that the driving source electrode SE of the driving transistor DT and the first electrode 124 of the light emitting diode LED may be electrically connected to each other. However, the embodiments of the present disclosure are not limited thereto.

[0138] In addition, in the figure, the driving source electrode SE of the driving transistor DT and the first electrode 124 of the light emitting diode LED are electrically connected through the reflector RF. However, the driving drain electrode DE of the driving transistor DT and the second electrode 125 of the light emitting diode LED can be electrically connected through the reflector RF according to the type of the driving transistor DT and the design of the pixel circuit PC, but is not limited thereto.

[0139] Next, even though not shown in the figure, a bank may be provided on the first connection electrode CE1 and the second connection electrode CE2. The bank may be provided to be spaced apart from the light emitting diode LED at a predetermined interval and at least partially overlap the reflective plate RF. For example, the bank may cover a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact holes of the third planarization layer 119 and the second planarization layer 118. The bank may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and may be formed of, for example, a black resin, but is not limited thereto.

[0140] In addition, in order to configure the image to be displayed to have different resolutions, it is necessary to configure the display device 100 to have different designs according to the resolution, so that the manufacturing process of the display device 100 is not unified, which may increase the manufacturing cost. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the display device 100 that displays a high-resolution image is used as it is, and a low-resolution display device 100 can be realized by driving only some pixels PX. For example, in the high-resolution mode, all pixels set in the plurality of first pixel areas UPA1 and the plurality of second pixel areas UPA2 are driven. In addition, in the low-resolution mode, the pixels of the plurality of first pixel areas UPA1 are driven, but the pixels of the plurality of second pixel areas UPA2 are not driven to display a low-resolution image. Therefore, the display device 100 designed to display a high-resolution image is used as it is to display a low-resolution image, so that the design of the existing display device 100 for displaying high resolution is used as it is and all manufacturing processes are unified to reduce manufacturing costs.

[0141] In addition, when the display device 100 is driven in a low-resolution mode, the number of driven pixels PX is reduced, so that the brightness of the display device 100 can be reduced. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, in the low-resolution mode, the driving current of the pixel circuit PC of the pixel PX of the second pixel area UPA2 that is not driven is supplied to the pixel PX of the first pixel area UPA1. By doing so, the brightness of the light emitted from each pixel PX is improved. A plurality of welding transistors WT connecting the first pixel area UPA1 and the second pixel area UPA2 are arranged to supply the driving current generated in the pixel PX of the second pixel area UPA2 to the light emitting diode LED of the first pixel area UPA1.

[0142] Reference Figures 3 to 5B , a plurality of welding transistors WT are disposed between the first pixel area UPA1 and the second pixel area UPA2. The welding transistor WT may connect each of the plurality of sub-pixels SP of the second pixel area UPA2 to each of the plurality of sub-pixels SP of the first pixel area UPA1. The driving current generated by the welding transistor WT in each of the plurality of sub-pixels SP of the second pixel area UPA2 may be transmitted to each of the plurality of sub-pixels SP of the first pixel area UPA1.

[0143] The welding transistor WT may connect each of the plurality of sub-pixels SP of the first pixel area UPA1 to each of the plurality of sub-pixels SP of the second pixel area UPA2. The welding transistor WT may connect the reflection plate RF of the sub-pixels SP emitting the same color light. For example, one welding transistor WT may connect the first sub-pixel SP1 of the first pixel area UPA1 and the second pixel area UPA2, and another welding transistor WT may connect the second sub-pixel SP2 of the first pixel area UPA1 and the second pixel area UPA2.

[0144] As described above, the reflector RF is connected between the driving transistor DT and the light emitting diode LED so that the driving current from the driving transistor DT can flow to the light emitting diode LED through the reflector RF. Therefore, the welding transistor WT is connected to the reflector RF through which the driving current flows from the driving transistor DT to transfer the driving current of one sub-pixel SP to another sub-pixel SP. For example, the welding source electrode WSE and the welding drain electrode WDE of each of the plurality of welding transistors WT may be connected to the first reflector RF1 of the first pixel area UPA1 and the first reflector RF1 of the second pixel area UPA2, the second reflector RF2 of the first pixel area UPA1 and the second reflector RF2 of the second pixel area UPA2. In addition, the welding source electrode WSE and the welding drain electrode WDE of each of the plurality of welding transistors WT may be connected to the third reflector RF3 of the first pixel area UPA1 and the third reflector RF3 of the second pixel area UPA2, and the fourth reflector RF4 of the first pixel area UPA1 and the fourth reflector RF4 of the second pixel area UPA2. For example, the welding source electrode WSE of one welding transistor WT among the plurality of welding transistors WT may be connected to the first reflection plate RF1 of the second pixel area UPA2, and the welding drain electrode WDE of the one welding transistor WT may be connected to the first reflection plate RF1 of the first pixel area UPA1. For example, the welding source electrode WSE of one welding transistor WT among the plurality of welding transistors WT may be connected to the second reflection plate RF2 of the second pixel area UPA2, and the welding drain electrode WDE of the one welding transistor WT may be connected to the second reflection plate RF2 of the first pixel area UPA1. For example, the welding source electrode WSE of one welding transistor WT among the plurality of welding transistors WT may be connected to the third reflection plate RF3 of the second pixel area UPA2, and the welding drain electrode WDE of the one welding transistor WT may be connected to the third reflection plate RF3 of the first pixel area UPA1. For example, the welding source electrode WSE of one welding transistor WT among the plurality of welding transistors WT may be connected to the fourth reflection plate RF4 of the second pixel area UPA2, and the welding drain electrode WDE of the one welding transistor WT may be connected to the fourth reflection plate RF4 of the first pixel area UPA1, but the present disclosure is not limited thereto.

[0145] The welding transistor WT includes a welding active layer WACT, a first welding gate electrode WGE1, a second welding gate electrode WGE2, a welding source electrode WSE, and a welding drain electrode WDE.

[0146] First, the first welding gate electrode WGE1 is disposed on the substrate 110 in the area between the first pixel area UPA1 and the second pixel area UPA2. The first welding gate electrode WGE1 may be disposed along the boundary between the first pixel area UPA1 and the second pixel area UPA2. An end of the first welding gate electrode WGE1 extends toward the welding control line WCL to be electrically connected to the welding control line WCL. The first welding gate electrodes WGE1 of the plurality of welding transistors WT are connected to each other. Therefore, the first welding gate electrode WGE1 serves as a gate electrode of each of the plurality of welding transistors WT, and may also serve as a wiring connecting each of the plurality of welding transistors WT and the welding control line WCL.

[0147] The buffer layer 111 is disposed on the first welding gate electrode WGE1, and the welding active layer WACT is disposed on the buffer layer 111. The welding active layer WACT may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0148] Oxide semiconductor materials may have excellent effects of preventing or reducing leakage current and relatively cheap manufacturing costs. Oxide semiconductors may be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and their oxides. Specifically, oxide semiconductors may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but are not limited thereto.

[0149] The polycrystalline semiconductor material has a fast moving speed of carriers such as electrons and holes, and thus has high mobility, and has low power consumption and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si), but is not limited thereto.

[0150] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0151] The gate insulating layer 112 is disposed on the welding active layer WACT, and the second welding gate electrode WGE2 is disposed on the gate insulating layer 112. The second welding gate electrode WGE2 may be electrically connected to the first welding gate electrode WGE1 through a contact hole formed in the gate insulating layer 112 and the buffer layer 111. Therefore, the welding transistor WT may be a transistor having a dual gate structure in which the first welding gate electrode WGE1 and the second welding gate electrode WGE2 are disposed above and below the welding active layer WACT. However, the welding transistor WT may include only any one of the first welding gate electrode WGE1 and the second welding gate electrode WGE2, but is not limited thereto.

[0152] Next, the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the second welding gate electrode WGE2, and the welding source electrode WSE and the welding drain electrode WDE are disposed on the second interlayer insulating layer 114. According to the type of the welding transistor WT, one of the welding source electrode WSE and the welding drain electrode WDE is connected to the multiple reflection plates RF of the first pixel area UPA1, and the other can be connected to the multiple reflection plates RF of the second pixel area UPA2. For example, when the welding transistor WT is a P-type transistor, the welding source electrode WSE is connected to the reflection plate RF of the second pixel area UPA2, and the welding drain electrode WDE is connected to the reflection plate RF of the first pixel area UPA1. Therefore, the driving current of the second pixel area UPA2 can be transmitted to the first pixel area UPA1. On the contrary, when the welding transistor WT is an N-type transistor, the welding source electrode WSE is connected to the reflection plate RF of the first pixel area UPA1, and the welding drain electrode WDE is connected to the reflection plate RF of the second pixel area UPA2. Therefore, the driving current of the second pixel area UPA2 can be transmitted to the first pixel area UPA1.

[0153] The welding control line WCL is disposed between the plurality of pixel areas UPA. For example, the welding control line WCL may extend in the column direction between the plurality of pixel areas UPA. The welding control line WCL is a wiring for applying a control signal to the plurality of welding transistors WT. The welding control line WCL applies a control signal to the first welding gate electrode WGE1 and the second welding gate electrode WGE2 of the welding transistor WT to turn on or off the welding transistor WT.

[0154] In addition, an auxiliary line WCLA may be provided to connect the plurality of welding transistors WT and the welding control line WCL. For example, one end of the auxiliary line WCLA is electrically connected to the welding control line WCL, and the other end may be connected to the first welding gate electrode WGE1 of the welding transistor WT. However, the first welding gate electrode WGE1 of the welding transistor WT may be directly connected to the welding control line WCL without using the auxiliary line WCLA, but is not limited thereto.

[0155] The auxiliary line WCLA may be formed in various shapes. For example, the auxiliary line WCLA may be formed in a rectangular shape having a closed loop structure. However, the auxiliary line WCLA may be configured in various shapes, but is not limited thereto.

[0156] In the following, reference will be made to Figures 6 to 8 A method for increasing brightness using a soldering transistor WT in a low resolution mode is described.

[0157] Figure 6 and Figure 7 is an exemplary circuit diagram of a pixel circuit of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 8 is a driving timing diagram of a display device according to an exemplary embodiment of the present disclosure.

[0158] Reference Figure 6 and Figure 7 , various pixel circuits PC including a driving transistor DT may be formed in the plurality of sub-pixels SP. For example, in the plurality of sub-pixels SP, the following may be provided: Figure 6 The pixel circuit PC with a 3T1C structure as shown or Figure 7 The pixel circuit PC with a 7T3C structure shown. However, the present disclosure is not limited thereto, and in the pixel circuit of the present disclosure, various configurations of the internal compensation circuit are possible. For example, the number of transistors TFT in the pixel circuit of the present disclosure may be three or more, and the number of capacitors may be 1 or more. For example, the pixel circuit of the present disclosure may be a 3T2C pixel circuit including three TFTs and two capacitors, a 5T1C pixel circuit including five TFTs and one capacitor, a 5T2C pixel circuit including five TFTs and two capacitors, or a 7T2C pixel circuit including seven TFTs and two capacitors, etc. Further, a plurality of light emitting diodes LED may be configured with any one of a common cathode structure in which the cathode is commonly connected to a low potential power line VSS or a common anode structure in which the anode is commonly connected to a high potential power line VDD.

[0159] For example, refer to Figure 6 , the pixel circuit PC may have a 3T1C structure, and the light emitting diode LED may be connected to the pixel circuit PC in a common cathode manner. In addition, the pixel circuit PC provided in each of the plurality of sub-pixels SP of the first pixel area UPA1 and the second pixel area UPA2 may include a driving transistor DT as an N-type transistor, a first transistor T1 and a second transistor T2, and a first capacitor C1.

[0160] The first transistor T1 includes a first gate electrode, a first source electrode, and a first drain electrode. The first drain electrode is connected to the data line DL, the first source electrode is connected to the driving gate electrode GE, and the first gate electrode is connected to the scan line SL. The first transistor T1 of the first pixel area UPA1 is turned on by the first scan signal S1 from the scan line SL, and the first transistor T1 of the second pixel area UPA2 is turned on by the second scan signal S2 from the scan line SL. The turned-on first transistor T1 transmits the data voltage from the data line DL to the driving gate electrode GE of the driving transistor DT. Therefore, the first transistor T1 can be called a switching transistor.

[0161] The second transistor T2 includes a second gate electrode, a second source electrode, and a second drain electrode. The second drain electrode is connected to the reference line, the second source electrode is connected to the driving source electrode SE, and the second gate electrode is connected to the sensing line. The second transistor T2 is turned on by the sensing signal Sense of the sensing line and transmits the reference voltage Vref from the reference line to the driving source electrode SE of the driving transistor DT.

[0162] The driving transistor DT includes a driving gate electrode GE, a driving source electrode SE, and a driving drain electrode DE. The driving drain electrode DE is connected to the high potential power line VDD, the driving source electrode SE is connected to the drain electrode of the first enabling transistor ET1 or the second enabling transistor ET2, and the driving gate electrode GE is connected to the first transistor T1. The driving transistor DT can control the driving current supplied to the light emitting diode LED.

[0163] The first capacitor C1 includes a plurality of capacitor electrodes. Some of the plurality of capacitor electrodes are connected to the driving gate electrode GE, and the other capacitor electrodes may be connected to the driving source electrode SE. The first capacitor C1 constantly maintains the voltage of the driving gate electrode GE to supply a constant driving current to the light emitting diode LED.

[0164] The light emitting diode LED includes an anode and a cathode. For example, the first electrode 124 of the light emitting diode LED connected to the first semiconductor layer 121 doped with n-type impurities is a cathode, and the second electrode 125 connected to the second semiconductor layer 123 doped with p-type impurities may be an anode. The anode is connected to the source electrode of the first enabling transistor ET1 or the second enabling transistor ET2, and the cathode may be connected to the low potential power line VSS. The light emitting diode LED of the first pixel area UPA1 is disposed between the first enabling transistor ET1 and the low potential power line VSS, and the light emitting diode LED of the second pixel area UPA2 may be disposed between the second enabling transistor ET2 and the low potential power line VSS.

[0165] The anode may be formed into a multilayer structure including an opaque conductive layer and a transparent conductive layer having high reflection efficiency. The transparent conductive layer is formed of a material having a large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive layer is formed of a single layer or multilayer structure containing Al, Ag, Cu, Pb, Mo or Ti or an alloy thereof. For example, the anode may be formed into a structure in which a transparent conductive layer, an opaque conductive layer and a transparent conductive layer are stacked in sequence, or a structure in which a transparent conductive layer and an opaque conductive layer are stacked in sequence. However, the embodiments of the present disclosure are not limited thereto.

[0166] For example, refer to Figure 7 , the pixel circuit PC may have a 7T3C structure, and the light emitting diode LED is connected to the pixel circuit PC in a common anode manner. Further, the pixel circuit PC provided in each of the plurality of sub-pixels SP in the first pixel area UPA1 and the second pixel area UPA2 may include a driving transistor DT as a P-type transistor, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. In addition, the pixel circuit PC provided in each of the plurality of sub-pixels SP in the first pixel area UPA1 and the second pixel area UPA2 may include a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0167] The first transistor T1 includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the scan line SL in the nth row, and the first source electrode and the first drain electrode may be connected to the driving gate electrode GE and the driving drain electrode DE of the driving transistor DT, respectively. When the threshold voltage of the driving transistor DT is compensated, the first transistor T1 may connect the driving transistor DT in a diode shape.

[0168] The second transistor T2 includes a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the scan line SL in the n-th row, the second source electrode is connected to the data line DL, and the second drain electrode is connected to the first capacitor C1. The second transistor T2 of the first pixel area UPA1 is turned on by the n-th first scan signal S1(n), and the second transistor T2 of the second pixel area UPA2 is turned on by the n-th second scan signal S2(n) to transfer the data voltage from the data line DL to the first capacitor C1. Therefore, the second transistor T2 can be called a switching transistor.

[0169] The third transistor T3 includes a third gate electrode, a third source electrode and a third drain electrode. The third gate electrode is connected to the light emitting control signal EM line, and the third source electrode and the third drain electrode are respectively connected to the reference line and the first capacitor C1. The third transistor T3 is turned on by the light emitting control signal EM to transmit the reference voltage Vref to the first capacitor C1.

[0170] The fourth transistor T4 includes a fourth gate electrode, a fourth source electrode and a fourth drain electrode. The fourth gate electrode is connected to the light emitting control signal EM line, and the fourth source electrode and the fourth drain electrode are respectively connected to the driving drain electrode DE and the low potential power line VSS. The fourth transistor T4 is turned on by the light emitting control signal EM to connect the driving transistor DT and the low potential power line VSS.

[0171] The fifth transistor T5 includes a fifth gate electrode, a fifth source electrode, and a fifth drain electrode. The fifth gate electrode is connected to the scan line SL in the n-1th row, and the fifth source electrode and the fifth drain electrode are connected to the reference line and the driving drain electrode DE, respectively. The fifth transistor T5 of the first pixel area UPA1 is turned on by the (n-1)th first scan signal S1(n-1), and the fifth transistor T5 of the second pixel area UPA2 is turned on by the (n-1)th second scan signal S2(n-1) to transmit the reference voltage Vref to the driving drain electrode DE.

[0172] The sixth transistor T6 includes a sixth gate electrode, a sixth source electrode, and a sixth drain electrode. The sixth gate electrode is connected to the scan line SL in the nth row, the sixth source electrode is connected to the high potential power line VDD, and the sixth drain electrode is connected to the driving source electrode SE and the cathode of the light emitting diode LED. The sixth transistor T6 of the first pixel area UPA1 is turned on by the nth first scan signal S1(n) and the sixth transistor T6 of the second pixel area UPA2 is turned on by the nth second scan signal S2(n), and the turned-on sixth transistor T6 can transmit the high potential power supply voltage to the driving source electrode SE and the cathode.

[0173] The driving transistor DT includes a driving gate electrode GE connected to a node between the first capacitor C1 and the third capacitor C3, a driving source electrode SE connected to a cathode of the light emitting diode LED, and a driving drain electrode DE connected to a fourth source electrode of the fourth transistor T4.

[0174] The first capacitor C1 includes a plurality of capacitor electrodes. Some of the plurality of capacitor electrodes are connected to the driving gate electrode GE, and the other capacitor electrodes may be connected to the second transistor T2. The first capacitor C1 constantly maintains the voltage of the driving gate electrode GE to supply a constant driving current to the light emitting diode LED.

[0175] The second capacitor C2 is a capacitor formed between the high potential power line VDD and the third capacitor C3. The second capacitor C2 includes a capacitor electrode connected to the high potential power line VDD and a capacitor electrode connected to the third capacitor C3. The second capacitor C2 increases the intrinsic capacitance in the light emitting diode LED to emit light with higher brightness from the light emitting diode LED.

[0176] The third capacitor C3 is a capacitor formed between the first capacitor C1 and the second capacitor C2 and between the driving gate electrode GE and the driving source electrode SE. The third capacitor C3 includes a capacitor electrode connected to the first capacitor C1 and a capacitor electrode connected to the second capacitor C2. The third capacitor C3 connected in series with the first capacitor C1 is coupled to the first capacitor C1, and a portion of the data voltage from the second drain electrode is transmitted to the driving gate electrode GE according to the capacitance ratio of the first capacitor C1 and the third capacitor C3. Therefore, the use of the third capacitor C3 reduces the transmission rate of the data voltage transmitted to the driving gate electrode GE. In addition, when the light emitting diode LED is configured as a micro LED having a large IV curve slope, the use of the third capacitor C3 reduces the transmission rate of the data voltage to display a more subtle gray scale.

[0177] The light emitting diode LED includes an anode and a cathode. The anode is connected to the source electrode of the first enabling transistor ET1 or the second enabling transistor ET2, and the cathode is connected to the driving transistor DT. The light emitting diode LED of the first pixel area UPA1 is arranged between the first enabling transistor ET1 and the driving transistor DT, and the light emitting diode LED of the second pixel area UPA2 can be arranged between the second enabling transistor ET2 and the driving transistor DT.

[0178] Next, a plurality of enabling transistors ET1 and ET2 for selectively supplying a driving current to the light emitting diode LED according to the high-resolution mode and the low-resolution mode may be provided in each of the plurality of sub-pixels SP. For example, the first enabling transistor ET1 is connected between the pixel circuit PC and the light emitting diode LED in the sub-pixel SP of the first pixel area UPA1, and the second enabling transistor ET2 may be connected between the pixel circuit PC and the light emitting diode LED in the sub-pixel SP of the second pixel area UPA2. The first enabling transistor ET1 is turned on or off to selectively supply a driving current to the light emitting diode LED of the first pixel area UPA1. In addition, the second enabling transistor ET2 is turned on or off to selectively supply a driving current to the light emitting diode LED of the second pixel area UPA2.

[0179] The first enabling transistor ET1 is used to control whether to drive the sub-pixel SP of the first pixel area UPA1. The first enabling transistor ET1 disposed in the sub-pixel SP of the first pixel area UPA1 includes a first enabling gate electrode, a first enabling source electrode, and a first enabling drain electrode.

[0180] For example, in Figure 6 In the common cathode structure shown, the first enabling source electrode and the first enabling drain electrode of the first enabling transistor ET1 are connected between the light emitting diode LED and the pixel circuit PC, and the first enabling gate electrode can be connected to the first enabling line EN1. Therefore, the turned-on first enabling transistor ET1 connects the anode of the light emitting diode LED in the first pixel area UPA1 and the pixel circuit PC, so that the driving current flows to the light emitting diode LED.

[0181] For example, in Figure 7 In the common anode structure shown, the first enabling source electrode and the first enabling drain electrode of the first enabling transistor ET1 can be connected between the high potential power line VDD and the light emitting diode LED. The turned-on first enabling transistor ET1 connects the light emitting diode LED in the first pixel area UPA1 and the high potential power line VDD to allow the driving current to flow to the light emitting diode LED.

[0182] The second enabling transistor ET2 is used to control whether to drive the sub-pixel SP of the second pixel area UPA2. The second enabling transistor ET2 disposed in the sub-pixel SP of the second pixel area UPA2 includes a second enabling gate electrode, a second enabling source electrode, and a second enabling drain electrode.

[0183] For example, in Figure 6 In the common cathode structure shown, the second enabling source electrode and the second enabling drain electrode of the second enabling transistor ET2 are connected between the light emitting diode LED and the pixel circuit PC, and the second enabling gate electrode can be connected to the second enabling line EN2. Therefore, the turned-on second enabling transistor ET2 connects the anode of the light emitting diode LED in the second pixel area UPA2 and the pixel circuit PC, so that the driving current flows to the light emitting diode LED.

[0184] For example, in Figure 7 In the common anode structure shown, the second enabling source electrode and the second enabling drain electrode of the second enabling transistor ET2 can be connected between the high potential power line VDD and the light emitting diode LED. The turned-on second enabling transistor ET2 connects the light emitting diode LED in the second pixel area UPA2 and the high potential power line VDD to allow the driving current to flow to the light emitting diode LED.

[0185] Furthermore, in the drawing, the first enabling transistor ET1 is illustrated as being connected to the light emitting diode LED of the first pixel area UPA1 , but the first enabling transistor ET1 may be omitted in the first pixel area UPA1 which is always driven in both the high resolution mode and the low resolution mode.

[0186] Finally, a welding transistor WT connecting the sub-pixel SP of the first pixel area UPA1 and the sub-pixel SP of the second pixel area UPA2 is provided. The welding transistor WT may connect a node between the light emitting diode LED of the first pixel area UPA1 and the second pixel area UPA2 and the driving transistor DT.

[0187] Specifically, the welding transistor WT includes a welding gate electrode, a welding source electrode WSE, and a welding drain electrode WDE.

[0188] For example, in a common cathode structure using N-type transistors, such as Figure 6 As shown, the welding gate electrode is connected to the welding control line WCL. Further, the welding source electrode WSE is connected to the first enable drain electrode of the first enable transistor ET1 which is the driving source electrode SE of the first pixel area UPA1. The welding drain electrode WDE may be connected to the second enable drain electrode and the driving source electrode SE of the second pixel area UPA2. When the welding transistor WT is turned on, the driving current of the second pixel area UPA2 may be transmitted to the node between the first enable transistor ET1 and the driving source electrode SE of the first pixel area UPA1, and a high current may be supplied to the light emitting diode LED.

[0189] For example, in a common anode structure using a P-type transistor, such as Figure 7 As shown, the welding gate electrode is connected to the welding control line WCL. The welding source electrode WSE is connected to the node between the cathode of the light emitting diode LED of the second pixel area UPA2 and the driving transistor DT. The welding drain electrode WDE can be connected to the node between the driving transistor DT and the cathode of the light emitting diode LED of the first pixel area UPA1. When the welding transistor WT is turned on, the driving current path of the second pixel area UPA2 is connected to the light emitting diode LED of the first pixel area UPA1, so that a high current flows to the light emitting diode LED of the first pixel area UPA1.

[0190] Reference Figure 8 , the display device 100 is driven in any one of the high-resolution mode and the low-resolution mode using the plurality of enable transistors ET1 and ET2 connected to each pixel circuit PC and the bonding transistor.

[0191] In the high-resolution mode, the sub-pixels of the plurality of first pixel areas UPA1 and the plurality of second pixel areas UPA2 may be driven. In addition, in the low-resolution mode, only the sub-pixels SP of the plurality of first pixel areas UPA1 among the sub-pixels of the plurality of first pixel areas UPA1 and the plurality of second pixel areas UPA2 may be driven, but the sub-pixels SP of the plurality of second pixel areas UPA2 among the sub-pixels of the plurality of first pixel areas UPA1 and the plurality of second pixel areas UPA2 may not be driven. In addition, in the low-resolution mode, the driving current generated in the pixel circuit PC of the sub-pixels SP of the plurality of second pixel areas UPA2 is supplied to the light-emitting diodes LED of the plurality of first pixel areas UPA1 to increase the brightness.

[0192] As an example, in Figure 6 In the pixel circuit PC of the first pixel area UPA1, in the high-resolution mode, the cut-off level voltage is applied to the welding control line WCL. The welding transistor WT is cut off by the cut-off level voltage from the welding control line WCL, and the pixel circuit PC of the first pixel area UPA1 and the second pixel area UPA2 can be separated. The welding transistor WT is cut off to cut off the current path between the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2. Therefore, the driving current generated in the pixel circuit PC of the first pixel area UPA1 is supplied only to the light emitting diode LED of the first pixel area UPA1, and the driving current generated in the pixel circuit PC of the second pixel area UPA2 can be supplied only to the light emitting diode LED of the second pixel area UPA2.

[0193] In addition, in the high-resolution mode, an on-level voltage may be applied to both the first enable line EN1 and the second enable line EN2. The first enable transistor ET1 of the first pixel area UPA1 is turned on by the on-level voltage from the first enable line EN1, so a drive current path between the pixel circuit PC in the first pixel area UPA1 and the light emitting diode LED may be formed. The second enable transistor ET2 of the second pixel area UPA2 is turned on by the on-level voltage from the second enable line EN2, so a drive current path between the pixel circuit PC in the second pixel area UPA2 and the light emitting diode LED may be formed.

[0194] Therefore, in the high-resolution mode, the welding transistor WT is turned off and the first and second enabling transistors ET1 and ET2 are turned on to drive both the sub-pixels SP of the first and second pixel areas UPA1 and UPA2 .

[0195] In contrast, in the low-resolution mode, an on-level voltage may be applied to the welding control line WCL. The welding transistor WT is turned on by the on-level voltage from the welding control line WCL, and the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2 may be connected to each other. The welding transistor WT is turned on to form a current path between the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2. Therefore, the driving current generated in the second pixel area UPA2 configured not to emit light in the low-resolution mode is not supplied to the light-emitting diode LED of the second pixel area UPA2, and may be supplied to the light-emitting diode LED of the first pixel area UPA1.

[0196] In addition, in the low-resolution mode, an on-level voltage is applied to the first enable line EN1, but an off-level voltage may be applied to the second enable line EN2. The first enable transistor ET1 of the first pixel area UPA1 is turned on by the on-level voltage from the first enable line EN1, so that a drive current path between the pixel circuit PC in the first pixel area UPA1 and the light emitting diode LED can be formed. The second enable transistor ET2 of the second pixel area UPA2 can be turned off by the off-level voltage from the second enable line EN2, so that the drive current path between the pixel circuit PC in the second pixel area UPA2 and the light emitting diode LED can be cut off. That is, even if a drive current is generated in the pixel circuit PC of the second pixel area UPA2, the drive current may not be supplied to the light emitting diode LED of the second pixel area UPA2.

[0197] Therefore, in the low resolution mode, the welding transistor WT and the first enabling transistor ET1 are turned on and the second enabling transistor ET2 is turned off to operate so that the subpixels SP of the second pixel area UPA2 do not display images, but only the subpixels SP of the first pixel area UPA1 display images.

[0198] exist Figure 8 In the embodiment, it is assumed that the welding transistor WT, the first enabling transistor ET1 and the second enabling transistor ET2 are as follows Figure 6 The N-type transistor shown in FIG. 1 is used to show a high level voltage as a conduction level voltage and a low level voltage as a cut-off level voltage. However, when the welding transistor WT, the first enabling transistor ET1 and the second enabling transistor ET2 are as shown in FIG. Figure 7 When the P-type transistor is shown, a high level voltage is used as an off level voltage, and a low level voltage is used as an on level voltage to select a high resolution mode and a low resolution mode.

[0199] In addition, a plurality of display devices 100 according to an exemplary embodiment of the present disclosure are connected to form a spliced ​​display device TD. Therefore, a plurality of display devices 100 having a specific inch and resolution can be connected according to specifications such as size and resolution of the spliced ​​display device TD. However, when the size and resolution of the spliced ​​display device TD change, the display devices 100 constituting the spliced ​​display device TD also need to be designed to have different specifications. However, in the display device 100 according to the exemplary embodiment of the present disclosure, some sub-pixels SP are selectively driven to easily adjust the resolution of the display device 100. For example, a plurality of display devices 100 that drive all sub-pixels SP of a plurality of first pixel areas UPA1 and a plurality of second pixel areas UPA2 to operate in a high-resolution mode are connected to form a spliced ​​display device TD having a specific resolution. In addition, in order to form a spliced ​​display device TD having a resolution lower than a specific resolution, a plurality of display devices 100 that operate in a low-resolution mode in which only sub-pixels SP in a plurality of first pixel areas UPA1 are driven and sub-pixels SP in a plurality of second pixel areas UPA2 are not driven can be connected. Therefore, a spliced ​​display device TD having various specifications can be formed using the display device 100 whose resolution is adjusted by selectively driving a plurality of sub-pixels SP. In addition, the display device 100 does not need to be redesigned for each spliced ​​display device TD of various models, and the design and process of the display device 100 can be unified to reduce manufacturing cost and process time and optimize the process.

[0200] In the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of first pixel areas UPA1 and a plurality of second pixel areas UPA2 are selectively driven to display an image in either a high-resolution mode or a low-resolution mode. The resolution may vary according to the density of the pixels PX, and the greater the number of pixels PX in the same area, the higher the resolution of the image to be displayed. Therefore, in the high-resolution mode, all pixels PX included in the display device 100 (for example, both the pixels PX of the first pixel area UPA1 and the pixels PX of the second pixel area UPA2) are driven to display a high-resolution image. In contrast, in the low-resolution mode, only some of the pixels PX (for example, the pixels in the first pixel area UPA1) of the plurality of pixels PX included in the display device 100 are driven to display an image, but not limited thereto, for example, only the pixels in the first pixel area UPA1 are driven to display an image. Therefore, the display device 100 having a specification capable of displaying a high-resolution image may be used as is to display a low-resolution image. Therefore, there is no need to design and manufacture a new display device 100 having specifications for displaying only a low-resolution image, but the existing high-resolution display device 100 can be used, so that the manufacturing cost and process time can be reduced.

[0201] In the display device 100 according to the exemplary embodiment of the present disclosure, the brightness of the display device 100 can be improved in the low-resolution mode. In the low-resolution mode, only the pixel PX of the first pixel area UPA1 emits light to display an image, while the pixel PX of the second pixel area UPA2 does not emit light. At this time, various signals are applied to the second pixel area UPA2 in the same manner to generate a driving current in the pixel circuit PC of the second pixel area UPA2. The generated driving current flows to the light-emitting diode LED of the first pixel area UPA1 to supply a high current to the light-emitting diode LED of the first pixel area UPA1. Specifically, a welding transistor WT connecting the pixel circuit PC of the first pixel area UPA1 and the second pixel area UPA2 is formed to transmit the driving current generated in the pixel circuit PC of the second pixel area UPA2 to the first pixel area UPA1. In addition, the second enabling transistor ET2 is connected to the light-emitting diode LED of the second pixel area UPA2 so that the light-emitting diode LED of the second pixel area UPA2 may not emit light. In this case, a high current can be supplied to the light-emitting diode LED while keeping the range of various voltages applied to the display device the same as the related art. Therefore, in the low-resolution mode, both the driving current from the pixel circuit PC of the first pixel area UPA1 and the driving current from the pixel circuit PC of the second pixel area UPA2 are supplied to the light-emitting diode LED of the first pixel area UPA1. Therefore, a high current is supplied to the light-emitting diode LED of the first pixel area UPA1, and the brightness of the display device 100 can be improved.

[0202] Fig. 9 is an enlarged plan view of a display panel of a display device according to another exemplary embodiment of the present disclosure. Fig.10 and Fig.11 is an exemplary circuit diagram of a pixel circuit of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure. Fig.12 is a driving timing diagram of a display device according to another exemplary embodiment of the present disclosure. Except that the light emitting diode LED is not transferred to the second pixel area UPA2 and the first enabling transistor ET1 and the second enabling transistor ET2 are not provided, Figures 9 to 12 The display device 900 and Figures 1 to 8 Therefore, redundant description will be omitted.

[0203] Reference Fig. 9In a display device 900 in which a plurality of pixel areas UPA are designed based on high resolution, the light emitting diodes LED are transferred only to some of the pixel areas UPA in the pixel areas UPA to form a display device 900 dedicated to a low-resolution mode. For example, after the pixel circuits PC, the plurality of reflective plates RF, and the adhesive layer 117 are completely formed in the plurality of pixel areas UPA, the plurality of light emitting diodes LED are transferred onto the adhesive layer 117. At this time, the light emitting diodes LED are transferred to the plurality of first pixel areas UPA1, and the light emitting diodes LED are not transferred to the plurality of second pixel areas UPA2. Therefore, the pixel circuits PC are formed in the plurality of second pixel areas UPA2, but the light emitting diodes LED are not transferred, so that no light is emitted. For example, the pixel circuits PC and the light emitting diodes LED are provided in the plurality of first pixel areas UPA1, the pixel circuits PC are provided in the plurality of second pixel areas UPA2, but the light emitting diodes LED are not provided in the plurality of second pixel areas UPA2, but the present disclosure is not limited thereto.

[0204] In addition, the display device 900 according to another exemplary embodiment of the present disclosure can be driven in either a low grayscale mode or a high grayscale mode. In the low grayscale mode, only the pixel circuit PC of the first pixel area UPA1 is used to drive the light emitting diode LED, and in the high grayscale mode, both the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2 are used to drive the light emitting diode LED of the first pixel area UPA1. Grayscale represents the concentration difference of color in level, and at a low grayscale level, a relatively dark image is displayed, while at a high grayscale level, a relatively bright image can be displayed. Therefore, when the image to be displayed is a low grayscale image, only the driving current from the pixel circuit PC of the first pixel area UPA1 is supplied to the light emitting diode LED to drive the display device 900 in the low grayscale mode. In addition, when the image to be displayed is a high grayscale image, all the driving currents from the pixel circuit PC of the first pixel area UPA1 and the second pixel area UPA2 are supplied to the light emitting diode LED, so that the light emitting diode LED is supplied with a high current to emit light of high brightness. Therefore, the display device 900 can be driven in a high grayscale mode.

[0205] For example, refer to Fig.10 , the pixel circuit PC has a 3T1C structure, and the light emitting diode LED is connected to the pixel circuit PC in a common cathode manner. At this time, the pixel circuit PC and the light emitting diode LED power line connected between the pixel circuit PC and the low potential power line VSS are arranged in the sub-pixel SP of the first pixel area UPA1. Further, in the sub-pixel SP of the second pixel area UPA2, the pixel circuit PC having a 3T1C structure is arranged, but the light emitting diode LED is not arranged.

[0206] Further, a welding transistor WT is provided to connect the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2. The welding source electrode WSE and the welding drain electrode WDE of the welding transistor WT may be connected to the same node of the pixel circuit PC of the first pixel area UPA1 and the second pixel area UPA2. The welding source electrode WSE and the welding drain electrode WDE may be connected to a node between the driving transistor DT and the light emitting diode LED. For example, the welding source electrode WSE is connected to a node of the driving source electrode SE of the driving transistor DT of the first pixel area UPA1, and the welding drain electrode WDE is connected to a node of the driving source electrode SE of the driving transistor DT of the second pixel area UPA2. That is, the welding source electrode WSE and the welding drain electrode WDE may be connected to a path through which the driving current flows between the pixel circuit PC and the light emitting diode LED.

[0207] As another example, refer to Fig.11 , the pixel circuit PC has a 7T3C structure, and the light emitting diode LED is connected to the pixel circuit PC in a common anode manner. At this time, the power line between the pixel circuit PC and the light emitting diode LED connected between the pixel circuit PC and the low potential power line VSS is set in the sub-pixel SP of the first pixel area UPA1. Further, in the sub-pixel SP of the second pixel area UPA2, the pixel circuit PC with a 7T3C structure is set, but the light emitting diode LED is not set.

[0208] Further, a welding transistor WT is provided to connect the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2. The welding source electrode WSE and the welding drain electrode WDE of the welding transistor WT may be connected to the same node of the pixel circuit PC of the first pixel area UPA1 and the second pixel area UPA2. The welding source electrode WSE and the welding drain electrode WDE may be connected to the node between the driving transistor DT and the light emitting diode LED. For example, the welding drain electrode WDE is connected to the node of the driving source electrode SE of the driving transistor DT of the first pixel area UPA1, and the welding source electrode WSE may be connected to the node of the driving source electrode SE of the driving transistor DT of the second pixel area UPA2. That is, the welding source electrode WSE and the welding drain electrode WDE may be connected to the path through which the driving current flows between the pixel circuit PC and the light emitting diode LED. Therefore, the welding transistor WT is turned on to transmit the driving current of the pixel circuit PC of the second pixel area UPA2 to the light emitting diode LED of the first pixel area UPA1.

[0209] Will describe Fig.10In the low grayscale mode, the welding transistor WT is turned off to separate the pixel circuit PC of the second pixel area UPA2 from the light emitting diode LED of the first pixel area UPA1. Fig.10 and Fig.12 In the low grayscale mode, the off-level voltage is applied to the welding control line WCL to turn off the welding transistor WT. Therefore, only the driving current from the pixel circuit PC of the first pixel area UPA1 is supplied to the light emitting diode LED of the first pixel area UPA1, and the driving current from the pixel circuit PC of the second pixel area UPA2 is not supplied to the light emitting diode LED of the first pixel area UPA1 to emit light.

[0210] Further, in the high grayscale mode, the welding transistor WT is turned on to connect the pixel circuit PC of the second pixel area UPA2 and the light emitting diode LED of the first pixel area UPA1. Fig.10 and Fig.12 , in the high grayscale mode, the on-level voltage is applied to the welding control line WCL to turn on the welding transistor WT. Therefore, the light emitting diode LED of the first pixel area UPA1 is supplied with both the driving current from the pixel circuit PC of the first pixel area UPA1 and the driving current from the pixel circuit PC of the second pixel area UPA2 to emit light. That is, the light emitting diode LED of the first pixel area UPA1 is supplied with high current from the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2 to emit light with high brightness. Therefore, the display device 900 can easily display a relatively bright high grayscale image.

[0211] In addition, Fig.12 In FIG. 1 , it is assumed that the welding transistor WT is an N-type transistor to represent the high level voltage as the on-level voltage and the low level voltage as the off-level voltage. However, when the welding transistor is Fig.11 When the P-type transistor is shown, the high level voltage is used as the off level voltage, and the low level voltage is used as the on level voltage to select the high gray scale mode and the low gray scale mode.

[0212] In a display device 900 according to another exemplary embodiment of the present disclosure, a display device 900 designed based on high resolution is used to implement a low-resolution display device 900. Specifically, when the light-emitting diode LED is transferred in the display device 100 in which a plurality of pixel areas UPA are designed based on high resolution, the light-emitting diode LED is transferred only to some of the pixel areas UPA to form a display device 900 dedicated to the low-resolution mode. Therefore, the formation process of the display device 900 dedicated to the high-resolution mode and the display device 900 dedicated to the low-resolution mode are performed in one process line, so that the process is unified. In addition, there is no need to design the display device 900 dedicated to the low-resolution mode, so that the manufacturing cost and process time are reduced.

[0213] In a display device 900 according to another exemplary embodiment of the present disclosure, the pixel circuit PC of the pixel area UPA where the light emitting diode LED is not transferred is additionally connected to the light emitting diode LED to supply a high current to the light emitting diode LED. The range of the driving current generated in one pixel circuit PC is limited, making it difficult to achieve a predetermined level or higher of the brightness of the light that can be emitted from the light emitting diode connected to one pixel circuit. Low grayscale images can be easily displayed, but in order to display a relatively bright high grayscale image, it is necessary to supply a high current to the light emitting diode LED. Therefore, in the high grayscale mode, the welding transistor WT is used to connect the pixel circuit PC of the second pixel area UPA2 in which the light emitting diode LED is not transferred to the light emitting diode LED of the first pixel area UPA1. The light emitting diode LED is connected to both the pixel circuit PC of the first pixel area UPA1 and the pixel circuit PC of the second pixel area UPA2 to be supplied with a high current and emit light with high brightness. Therefore, the pixel circuit PC of the pixel area UPA where the light emitting diode LED is not transferred is temporarily connected to the light emitting diode LED in the high grayscale mode to supply a high current to the light emitting diode LED, thereby easily displaying a high grayscale image.

[0214] Exemplary embodiments of the present disclosure may also be described as follows:

[0215] According to an exemplary embodiment of the present disclosure, a display device includes: a display panel, in which a plurality of first pixel regions and a plurality of second pixel regions are defined, each of the plurality of first pixel regions and the plurality of second pixel regions including a plurality of sub-pixels; a pixel circuit, the pixel circuit being arranged in each of the plurality of sub-pixels and including a driving transistor; and a welding transistor, the welding transistor selectively connecting the pixel circuits of the first pixel regions and the second pixel regions that are adjacent to each other among the plurality of first pixel regions and the plurality of second pixel regions.

[0216] The welding transistor according to the exemplary embodiment of the present disclosure may be disposed between the pixel circuit of the first pixel area and the pixel circuit of the second pixel area, and may selectively control connection or disconnection between the pixel circuit of the first pixel area and the pixel circuit of the second pixel area.

[0217] The welding transistor according to the exemplary embodiment of the present disclosure may be provided between the pixel circuit of the first pixel area and the pixel circuit of the second pixel area and selectively control the display panel to operate in a high resolution mode or a low resolution mode.

[0218] The display device according to the exemplary embodiment of the present disclosure may further include a reflection plate provided in each of the plurality of sub-pixels and electrically connected to the driving transistor of the pixel circuit.

[0219] The welding transistor according to the exemplary embodiment of the present disclosure may be disposed between the reflection plate of the first pixel area and the reflection plate of the second pixel area, and may selectively control connection or disconnection between the reflection plate of the first pixel area and the reflection plate of the second pixel area.

[0220] The display device according to the exemplary embodiment of the present disclosure may further include a light emitting diode disposed in at least some of the plurality of sub-pixels to be connected to a driving transistor of the pixel circuit. A welding source electrode or a welding drain electrode of the welding transistor may be connected to a node between the driving transistor and the light emitting diode.

[0221] According to an exemplary embodiment of the present disclosure, in a high-resolution mode in which the display panel displays a high-resolution image, the light-emitting diodes of the plurality of first pixel areas and the light-emitting diodes of the plurality of second pixel areas may emit light, and in a low-resolution mode in which the display panel displays a low-resolution image, the light-emitting diodes of the plurality of first pixel areas may emit light, and the light-emitting diodes of the plurality of second pixel areas may not emit light.

[0222] The display device according to the exemplary embodiment of the present disclosure may further include: a first enabling transistor, which is disposed in each of the plurality of sub-pixels of the plurality of first pixel regions and connected between the driving transistor and the light emitting diode; and a second enabling transistor, which is disposed in each of the plurality of sub-pixels of the plurality of second pixel regions and connected between the driving transistor and the light emitting diode. The welding transistor may selectively connect a node between the first enabling transistor and the driving transistor and a node between the second enabling transistor and the driving transistor.

[0223] According to an exemplary embodiment of the present disclosure, the source electrode of the first enabling transistor can be connected to the driving drain electrode of the driving transistor, and the drain electrode of the first enabling transistor can be connected to the anode of the light-emitting diode, and the source electrode of the second enabling transistor can be connected to the driving drain electrode of the driving transistor, and the drain electrode of the second enabling transistor can be connected to the anode of the light-emitting diode.

[0224] The display device according to the exemplary embodiment of the present disclosure may further include: a first enabling transistor, which is arranged in each of the plurality of sub-pixels in the plurality of first pixel regions and connected between the light emitting diode and the high potential power line; and a second enabling transistor, which is arranged in each of the plurality of sub-pixels in the plurality of second pixel regions and connected between the light emitting diode and the high potential power line. The welding transistor may selectively connect a node between the light emitting diode of each of the plurality of sub-pixels in the plurality of first pixel regions and the driving transistor and a node between the light emitting diode of each of the plurality of sub-pixels in the plurality of second pixel regions and the driving transistor.

[0225] According to an exemplary embodiment of the present disclosure, in the low-resolution mode, driving currents from pixel circuits of the plurality of second pixel regions may be supplied to light emitting diodes of the plurality of first pixel regions.

[0226] According to an exemplary embodiment of the present disclosure, in the high resolution mode, the first and second enabling transistors may be turned on and the welding transistor may be turned off, and in the low resolution mode, the first enabling transistor and the welding transistor may be turned on and the second enabling transistor may be turned off.

[0227] According to an exemplary embodiment of the present disclosure, the light emitting diodes may be transferred to the plurality of sub-pixels of the plurality of first pixel regions, but may not be transferred to the plurality of sub-pixels of the plurality of second pixel regions.

[0228] In a high grayscale mode in which the display panel displays a high grayscale image, the light-emitting diodes of the multiple first pixel areas can be supplied with driving currents from the pixel circuits of the multiple first pixel areas and the pixel circuits of the multiple second pixel areas, and in a low grayscale mode in which the display panel displays a low grayscale image, the light-emitting diodes of the multiple first pixel areas can be supplied with driving currents from the pixel circuits of the multiple first pixel areas.

[0229] In the low grayscale mode, the light emitting diodes of the plurality of first pixel regions are not supplied with driving currents from the pixel circuits of the plurality of second pixel regions.

[0230] In the high grayscale mode, the welding transistor can be turned on and can electrically connect the anodes of the light-emitting diodes of multiple first pixel areas with the driving transistors of the pixel circuits of multiple second pixel areas, and in the low grayscale mode, the welding transistor can be turned off and can separate the anodes of the light-emitting diodes of multiple first pixel areas from the driving transistors of the pixel circuits of multiple second pixel areas.

[0231] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate, in which a plurality of first pixel regions and a plurality of second pixel regions, each of which includes a plurality of sub-pixels, are defined; a plurality of pixel circuits, which are arranged in each of the plurality of sub-pixels, and each of the plurality of pixel circuits includes a driving transistor; a plurality of reflecting plates, which are arranged in each of the plurality of sub-pixels on the plurality of pixel circuits and are electrically connected to the driving transistor of each of the plurality of pixel circuits; and a plurality of welding transistors, which are arranged between the plurality of first pixel regions and the plurality of second pixel regions and the plurality of welding transistors selectively connect the plurality of reflecting plates of the plurality of first pixel regions and the plurality of reflecting plates of the plurality of second pixel regions.

[0232] The display device may further include a plurality of light emitting diodes disposed on a plurality of reflective plates in at least some of the plurality of sub-pixels. Each of the plurality of light emitting diodes may be electrically connected to the driving transistor through each of the plurality of reflective plates.

[0233] The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The plurality of reflectors may include a first reflector disposed in the first sub-pixel, a second reflector disposed in the second sub-pixel, a third reflector disposed in the third sub-pixel, and a fourth reflector disposed in the fourth sub-pixel. Each of the plurality of welding transistors may be respectively connected to the first reflector of the plurality of first pixel regions and the first reflector of the plurality of second pixel regions, the second reflector of the plurality of first pixel regions and the second reflector of the plurality of second pixel regions, the third reflector of the plurality of first pixel regions and the third reflector of the plurality of second pixel regions, and the fourth reflector of the plurality of first pixel regions and the fourth reflector of the plurality of second pixel regions.

[0234] In the high-resolution mode, the welding transistor can be turned off and can electrically separate each of the multiple reflective plates of the multiple first pixel areas from each of the multiple reflective plates of the multiple second pixel areas, and in the low-resolution mode, the welding transistor can be turned on and can electrically connect each of the multiple reflective plates of the multiple first pixel areas with each of the multiple reflective plates of the multiple second pixel areas.

[0235] The display device may also include a plurality of first enabling transistors connected to the plurality of light emitting diodes of the plurality of first pixel regions and a plurality of second enabling transistors connected to the plurality of light emitting diodes of the plurality of second pixel regions. In a high-resolution mode, the plurality of first enabling transistors and the plurality of second enabling transistors may be turned on to connect a path for supplying a driving current to the plurality of light emitting diodes, and in a low-resolution mode, the enabling transistors provided in the plurality of second pixel regions may be turned off to separate a path for supplying a driving current to the plurality of light emitting diodes of the plurality of second pixel regions.

[0236] Among the multiple first pixel areas and the multiple second pixel areas, the multiple light emitting diodes can be arranged only in the multiple first pixel areas, and in the low grayscale mode, the welding transistor can be turned off to electrically separate each of the multiple reflection plates of the multiple first pixel areas from each of the multiple reflection plates of the multiple second pixel areas, and in the high grayscale mode, the welding transistor can be turned on to electrically connect each of the multiple reflection plates of the multiple first pixel areas with each of the multiple reflection plates of the multiple second pixel areas.

[0237] Among the plurality of first pixel regions and the plurality of second pixel regions, the plurality of light emitting diodes are not disposed in the plurality of second pixel regions.

[0238] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be understood to fall within the scope of the present disclosure.

[0239] CROSS-REFERENCE TO RELATED APPLICATIONS

[0240] This application claims priority from Korean Patent Application No. 10-2023-0077472 filed on June 16, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein for all purposes by reference.

Claims

1. A display device, comprising: A display panel, wherein a plurality of first pixel regions and a plurality of second pixel regions are defined in the display panel, each of which includes a plurality of sub-pixels; a pixel circuit, the pixel circuit being disposed in each of the plurality of sub-pixels, the pixel circuit comprising a driving transistor; as well as A welding transistor selectively connects the pixel circuits of the plurality of first pixel regions and the plurality of second pixel regions that are adjacent to each other among the plurality of first pixel regions and the plurality of second pixel regions.

2. The display device according to claim 1, wherein: The welding transistor is provided between the pixel circuit of the first pixel area and the pixel circuit of the second pixel area, and selectively controls connection or disconnection between the pixel circuit of the first pixel area and the pixel circuit of the second pixel area.

3. The display device according to claim 1, wherein: The welding transistor is disposed between a pixel circuit of the first pixel area and a pixel circuit of the second pixel area, and selectively controls the display panel to operate in a high-resolution mode or a low-resolution mode. 4 . The display device according to claim 1 , further comprising a reflection plate provided in each of the plurality of sub-pixels and electrically connected to the driving transistor of the pixel circuit.

5. The display device according to claim 4, wherein: The welding transistor is disposed between the reflection plate of the first pixel area and the reflection plate of the second pixel area, and selectively controls connection or disconnection between the reflection plate of the first pixel area and the reflection plate of the second pixel area.

6. The display device according to claim 1, further comprising: a light emitting diode disposed in at least some of the plurality of sub-pixels to be connected to the driving transistor of the pixel circuit, The welding source electrode or the welding drain electrode of the welding transistor is connected to a node between the driving transistor and the light emitting diode.

7. The display device according to claim 6, wherein: In a high-resolution mode in which the display panel displays a high-resolution image, the light-emitting diodes of the plurality of first pixel regions and the light-emitting diodes of the plurality of second pixel regions emit light, and In a low-resolution mode in which the display panel displays a low-resolution image, the light-emitting diodes of the plurality of first pixel regions emit light, and the light-emitting diodes of the plurality of second pixel regions do not emit light.

8. The display device according to claim 7, further comprising: a first enabling transistor, the first enabling transistor being disposed in each of the plurality of sub-pixels of the plurality of first pixel regions and connected between the driving transistor and the light emitting diode; as well as a second enabling transistor, which is disposed in each of the plurality of sub-pixels in the plurality of second pixel regions and is connected between the driving transistor and the light emitting diode, The welding transistor selectively connects a node between the first enabling transistor and the driving transistor and a node between the second enabling transistor and the driving transistor.

9. The display device according to claim 8, in, The source electrode of the first enabling transistor is connected to the driving drain electrode of the driving transistor, and the drain electrode of the first enabling transistor is connected to the anode of the light emitting diode, and The source electrode of the second enabling transistor is connected to the driving drain electrode of the driving transistor, and the drain electrode of the second enabling transistor is connected to the anode of the light emitting diode.

10. The display device according to claim 7, further comprising: a first enabling transistor, the first enabling transistor being provided in each of the plurality of sub-pixels of the plurality of first pixel regions and being connected between the light emitting diode and a high potential power line; as well as a second enabling transistor, which is provided in each of the plurality of sub-pixels in the plurality of second pixel regions and connected between the light emitting diode and the high potential power line, The welding transistor selectively connects a node between the light-emitting diode of each of the sub-pixels in the first pixel regions and the driving transistor and a node between the light-emitting diode of each of the sub-pixels in the second pixel regions and the driving transistor.

11. The display device according to claim 10, wherein: In the low-resolution mode, driving currents from pixel circuits of the plurality of second pixel regions are supplied to the light emitting diodes of the plurality of first pixel regions.

12. The display device according to claim 10, wherein: In the high resolution mode, the first enabling transistor and the second enabling transistor are turned on and the welding transistor is turned off, and In the low-resolution mode, the first enabling transistor and the welding transistor are turned on and the second enabling transistor is turned off.

13. The display device according to claim 6, wherein: The light emitting diodes are disposed in the plurality of sub-pixels in the plurality of first pixel regions, but are not disposed in the plurality of sub-pixels in the plurality of second pixel regions.

14. The display device according to claim 13, wherein: In a high grayscale mode in which the display panel displays a high grayscale image, the light emitting diodes of the plurality of first pixel regions are supplied with driving currents from the pixel circuits of the plurality of first pixel regions and the pixel circuits of the plurality of second pixel regions, and In a low grayscale mode in which the display panel displays a low grayscale image, the light emitting diodes of the plurality of first pixel regions are supplied with driving currents from the pixel circuits of the plurality of first pixel regions.

15. The display device according to claim 14, wherein: In the low grayscale mode, the light emitting diodes of the plurality of first pixel regions are not supplied with driving currents from the pixel circuits of the plurality of second pixel regions.

16. The display device according to claim 14, wherein: In the high grayscale mode, the welding transistor is turned on to electrically connect the anodes of the light emitting diodes of the plurality of first pixel regions to the driving transistors of the pixel circuits of the plurality of second pixel regions, and In the low grayscale mode, the welding transistor is turned off to disconnect the anodes of the light emitting diodes of the plurality of first pixel regions from the driving transistors of the pixel circuits of the plurality of second pixel regions.

17. A display device, comprising: a substrate in which a plurality of first pixel regions and a plurality of second pixel regions, each of which includes a plurality of sub-pixels, are defined; a plurality of pixel circuits disposed in each of the plurality of sub-pixels on the substrate and including a driving transistor; a plurality of reflection plates, the reflection plates being disposed in each of the plurality of sub-pixels on the plurality of pixel circuits and being electrically connected to the driving transistor of each of the plurality of pixel circuits; as well as A plurality of welding transistors are disposed between the plurality of first pixel regions and the plurality of second pixel regions and selectively connect the plurality of reflection plates of the plurality of first pixel regions and the plurality of reflection plates of the plurality of second pixel regions.

18. The display device according to claim 17, further comprising: a plurality of light emitting diodes, wherein the plurality of light emitting diodes are arranged on the plurality of reflective plates in at least some of the plurality of sub-pixels; Each of the plurality of light emitting diodes is electrically connected to the driving transistor through each of the plurality of reflection plates.

19. The display device according to claim 18, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, The plurality of reflection plates include a first reflection plate disposed in the first sub-pixel, a second reflection plate disposed in the second sub-pixel, a third reflection plate disposed in the third sub-pixel, and a fourth reflection plate disposed in the fourth sub-pixel, and Each of the multiple welding transistors is respectively connected to the first reflecting plate of the multiple first pixel areas and the first reflecting plate of the multiple second pixel areas, the second reflecting plate of the multiple first pixel areas and the second reflecting plate of the multiple second pixel areas, the third reflecting plate of the multiple first pixel areas and the third reflecting plate of the multiple second pixel areas, and the fourth reflecting plate of the multiple first pixel areas and the fourth reflecting plate of the multiple second pixel areas.

20. The display device according to claim 19, wherein: In a high-resolution mode, the welding transistor is turned off and electrically separates each of the plurality of reflection plates of the plurality of first pixel regions from each of the plurality of reflection plates of the plurality of second pixel regions, and In a low resolution mode, the welding transistor is turned on and electrically connects each of the plurality of reflection plates of the plurality of first pixel regions with each of the plurality of reflection plates of the plurality of second pixel regions.

21. The display device according to claim 20, further comprising: a plurality of first enabling transistors connected to the plurality of light emitting diodes of the plurality of first pixel regions; as well as a plurality of second enabling transistors, the plurality of second enabling transistors being connected to the plurality of light emitting diodes of the plurality of second pixel regions, wherein, in the high-resolution mode, the plurality of first enabling transistors and the plurality of second enabling transistors are turned on and connect a path for supplying a driving current to the plurality of light emitting diodes, and In the low-resolution mode, the enable transistors provided in the plurality of second pixel regions are turned off and disconnect a path for supplying the driving current to the plurality of light emitting diodes in the plurality of second pixel regions.

22. The display device according to claim 19, wherein: Among the plurality of first pixel regions and the plurality of second pixel regions, the plurality of light emitting diodes are arranged in the plurality of first pixel regions, In a low grayscale mode, the welding transistor is turned off and electrically separates each of the plurality of reflection plates of the plurality of first pixel regions from each of the plurality of reflection plates of the plurality of second pixel regions, and In a high grayscale mode, the welding transistor is turned on and electrically connects each of the plurality of reflection plates of the plurality of first pixel regions with each of the plurality of reflection plates of the plurality of second pixel regions.

23. The display device according to claim 22, wherein: Among the plurality of first pixel regions and the plurality of second pixel regions, the plurality of light emitting diodes are not disposed in the plurality of second pixel regions.

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