Semiconductor device, preparation method thereof and electronic equipment

Abstract

According to the semiconductor device, the preparation method thereof and the electronic equipment provided by the invention, the resistance above the P + collector region is increased by adding the low-doped N-type high-resistance region above the P + collector region, and the current path above the P + collector region is prolonged by arranging the P-type floating region with the partition region between the N-type high-resistance region and the N-type buffer layer, so that the current path above the P + collector region is prolonged. And the P + collector region is arranged at the bottom of the first groove of the N-type high-resistance region, so that the longitudinal distance of the N-type high-resistance region in the collector structure is increased, the distance from the N + collector region to the middle position of the P + collector region is farther, and the parasitic resistance of the device from the middle position of the P + collector region to the N + collector region is relatively higher; a PN junction formed by the P + collector region / the N-type high-resistance region is easier to open, the snapback phenomenon existing when a conventional reverse conducting device is conducted in the forward direction can be more effectively restrained, and meanwhile the forward conducting characteristic and the reverse conducting characteristic of the device can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof and an electronic device. Background Art

[0002] Bipolar devices such as IGBT (insulated gate bipolar transistor) and GTO (gate turn-off thyristor) participate in conduction when they are turned on. The number of minority carriers in the drift region is much higher than the background doping concentration. Therefore, a conductivity modulation effect occurs in the drift region, greatly reducing the on-resistance of the drift region. They are widely used in applications that require high voltage and high current.

[0003] Conventional bipolar devices such as IGBT and GTO have PN junctions in the collector, so the device cannot achieve reverse conduction. In applications, an anti-parallel freewheeling diode is often required for freewheeling. Integrating the freewheeling diode inside the bipolar device can not only reduce the parasitic inductance and parasitic resistance of the connecting leads, but also save the terminal area, thereby increasing the device power density, improving device performance, and reducing the system volume. In order to integrate the freewheeling diode inside the bipolar device, reverse-conducting IGBT, reverse-conducting GTO, etc. have been proposed. Conventional reverse-conducting IGBT introduces an N+ collector region that is short-circuited with the P+ collector region in the collector region of the device, thereby forming a PiN diode structure in the device to achieve the freewheeling function.

[0004] However, in the initial forward conduction stage of conventional reverse-conducting devices, when the device switches from unipolar conduction mode to bipolar conduction mode, there will be a process in which the on-state voltage drop of the device decreases sharply due to a sharp drop in on-resistance, which is called the voltage snapback phenomenon. The existence of the snapback phenomenon may cause the internal cells of the device to be unable to switch from unipolar conduction mode to bipolar conduction mode at the same time due to differences in structural material parameters or temperature distribution, resulting in uneven distribution of current inside the device, which can easily lead to local overcurrent and failure of the device. Summary of the invention

[0005] In view of this, the embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device, which are used to eliminate the snapback effect during the forward conduction process of the device and improve the device performance.

[0006] The present disclosure provides a semiconductor device and a method for manufacturing the same, and an electronic device, the specific scheme of which is as follows: In one aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: an N-type drift region, a collector structure disposed on a first surface of the N-type drift region, and a gate structure and an emitter structure disposed on a second surface of the N-type drift region; the first surface and the second surface are disposed opposite to each other; The collector structure includes a collector metal layer, an N+ collector region, a P+ collector region, an N-type high resistance region, a P-type floating region and an N-type buffer layer; wherein, The N-type buffer layer contacts the first surface of the N-type drift region, the P-type floating region contacts the surface of the N-type buffer layer away from the N-type drift region, and the P-type floating region has a partition region; the N-type high resistance region contacts the surface of the P-type floating region away from the N-type drift region and fills the partition region, the N+ collector region contacts the surface of the N-type high resistance region away from the N-type drift region, and the N+ collector region has a through hole, and the orthographic projection of the partition region on the N-type buffer layer overlaps with the orthographic projection of the through hole on the N-type buffer layer; the P+ collector region includes a first sub-P+ collector region embedded in the surface of the N-type high resistance region away from the N-type drift region, and the first sub-P+ collector region corresponds to the position of the through hole; the collector metal layer contacts the surface of the N+ collector region away from the N-type drift region and fills the through hole until it contacts the first sub-P+ collector region.

[0007] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, a surface of the first sub-P+ collector region facing away from the N-type drift region is flush with a surface of the N+ collector region facing the N-type drift region.

[0008] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the N-type high resistance region has an opening arranged corresponding to the through hole and penetrating a portion of the thickness of the N-type high resistance region, the through hole and the opening are interconnected, and the first sub-P+ collector region is embedded in the surface of the N-type high resistance region corresponding to the position of the opening, away from the N-type drift region.

[0009] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the cross-sectional shape of the through hole along the thickness direction of the N-type high resistance region is a rectangle.

[0010] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the P+ collector region also includes a second sub-P+ collector region embedded in the side surface of the N-type high resistance region corresponding to the opening position, the first sub-P+ collector region and the second sub-P+ collector region are an integrated structure, and the surface of the N+ collector region facing the N-type drift region is in contact with the surface of the N-type high resistance region away from the N-type drift region and the surface of the second sub-P+ collector region away from the N-type drift region.

[0011] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the cross-sectional shape of the overall structure of the through hole and the opening along the thickness direction of the N-type high resistance region is a regular trapezoid.

[0012] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, an orthographic projection area of ​​the partition region on the N-type buffer layer is smaller than an orthographic projection area of ​​the through hole on the N-type buffer layer.

[0013] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the center of the orthographic projection of the partition region on the N-type buffer layer coincides with the center of the orthographic projection of the through hole on the N-type buffer layer.

[0014] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, a surface of the collector metal layer facing away from the N-type drift region is a flat surface.

[0015] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, the gate structure includes: a gate dielectric layer located on the second surface of the N-type drift region, a gate electrode located on a side of the gate dielectric layer away from the N-type drift region, and an isolation dielectric layer located on a side of the gate electrode away from the N-type drift region; the isolation dielectric layer covers the gate electrode and contacts the gate dielectric layer; The emitter structure includes a P-type well region, an N-type emitter region, a P-type emitter region and an emitter metal layer. The P-type well region, the N-type emitter region and the P-type emitter region are embedded in the second surface of the N-type drift region. The cross-section of the P-type well region along the thickness direction of the N-type drift region is concave. The P-type emitter region is located in the middle area of ​​the concave shape. The N-type emitter region is located between the P-type emitter region and the side wall of the concave shape. The surface of the gate dielectric layer facing the N-type buffer layer is in contact with the N-type emitter region, the P-type well region and the N-type drift region. The emitter metal layer wraps the gate structure and is in contact with the N-type emitter region and the P-type emitter region.

[0016] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, a surface of the emitter metal layer facing away from the N-type drift region is a flat surface.

[0017] On the other hand, the present disclosure also provides a method for preparing the semiconductor device, which is used to prepare the semiconductor device provided by the present disclosure. The method comprises: Providing an N+ substrate, and forming an N-type high resistance region on one side of the N+ substrate; Forming the P-type floating region having a partition region on the surface of the N-type high resistance region away from the N+ substrate; Forming an N-type buffer layer and an N-type drift region on a surface of the P-type floating region away from the N+ substrate; forming a part of the emitter structure on a surface of the N-type drift region away from the N-type buffer layer; Patterning the N+ substrate to form a through hole that completely penetrates the N+ substrate to form the N+ collector region; Forming the first sub-P+ collector region on a surface of the N-type high resistance region corresponding to the position of the through hole away from the N-type drift region; forming a gate structure on a side of the N-type drift region and a portion of the emitter structure away from the N-type buffer layer; forming another part of the emitter structure on a side of the gate structure away from the N-type buffer layer; The collector metal layer is formed on a side of the N+ collector region and the first sub-P+ collector region away from the gate structure.

[0018] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, when the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region is not patterned.

[0019] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, when the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region is simultaneously patterned to form an opening that penetrates a portion of the thickness of the N-type high resistance region, and the through hole and the opening are interconnected.

[0020] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned semiconductor device provided by an embodiment of the present disclosure.

[0021] The beneficial effects of the present disclosure are as follows: A semiconductor device, a preparation method thereof, and an electronic device provided by the embodiments of the present disclosure increase the resistance above the P+ collector region by adding a low-doped N-type high-resistance region above the P+ collector region, and extend the current path above the P+ collector region by setting a P-type floating region with a partition region between the N-type high-resistance region and the N-type buffer layer. The P+ collector region is embedded in the N-type high-resistance region, thereby increasing the longitudinal distance of the N-type high-resistance region in the collector structure, and making the distance from the N+ collector region to the middle position of the P+ collector region farther. Therefore, when the device is forward-conducted, the voltage drop generated by the unipolar current from the middle position of the P+ collector region to the N+ collector region is relatively higher, and the PN junction formed by the P+ collector region / N-type high-resistance region is easier to open, and it is easier to eliminate the snapback phenomenon when the device is forward-conducted. Compared with the method in the related art in which the reverse conducting device improves the snapback phenomenon by increasing the length ratio of the P+ collector region to the N+ collector region, thereby increasing the parasitic resistance above the P+ collector region, the structure disclosed in the present invention can improve the snapback phenomenon by increasing the longitudinal distance between the P+ collector region and the N+ collector region. In this way, the length ratio of the P+ collector region to the N+ collector region can be better controlled, and the problems of uneven distribution of the reverse conduction current of the device and excessively high conduction voltage drop can be avoided, so as to compromise and optimize the forward conduction characteristics and reverse conduction characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A structure of a reverse conducting IGBT device provided in the related art; Figure 2 for Figure 1 The corresponding equivalent circuit diagram; Figure 3 A schematic diagram of a voltage rebound phenomenon occurring in a reverse-conducting IGBT device provided in the related art; Figure 4 A schematic diagram of a structure of a semiconductor device provided by an embodiment of the present disclosure; Figure 5 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 7 for Figure 5 The schematic diagram of the current path when the semiconductor device is forward-conducting is shown; Figure 8 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present disclosure; Fig. 9A for Figure 5 A schematic diagram of a structure of a semiconductor device during the preparation process shown; Fig. 9B for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Fig. 9C for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Fig.9D for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Fig.9E for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Fig.9F for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Figure 9G for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Figure 9H for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Fig.9I for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Figure 9J for Figure 5 Another structural schematic diagram of a semiconductor device during the manufacturing process shown; Figure 9K for Figure 5 Another structural schematic diagram of a semiconductor device during the preparation process is shown. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thickness of the layers, films, panels, regions, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes do not represent the exact shapes of the illustrated areas, do not reflect the true proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0024] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] like Figure 1 and Figure 2 As shown, Figure 1 A structure of a reverse conducting IGBT device provided in the related art, Figure 2 for Figure 1 The corresponding equivalent circuit diagram shows that when the reverse-conducting IGBT device is forward-conducting, the N+ collector region 10 is turned on first, and the on-resistance is large at the initial stage of conduction. The device works in a unipolar conduction mode. Due to the parasitic resistance of the N-type buffer layer 20, as the voltage of the collector metal layer 30 increases, the current will produce a voltage drop on the parasitic resistance. When this voltage drop is greater than the built-in potential on the PN junction of the P+ collector region 40 / N-type buffer layer 20, the PN junction of the P+ collector region 40 / N-type buffer layer 20 will be turned on, and the device will enter a bipolar conduction mode with a low on-resistance. The sharp decrease in on-resistance will cause a snapback phenomenon, such as Figure 3 In order to suppress the snapback phenomenon, Figure 1 The reverse-conducting device shown increases the parasitic resistance of the N-type buffer layer 20 above the P+ collector region 40 by increasing the length ratio of the P+ collector region 40 to the N+ collector region 10, so that the potential difference between the N-type buffer layer 20 far away from the N+ collector region 10 and the N+ collector region 10 can more easily reach the turn-on voltage of the PN junction of the P+ collector region 40 / N-type buffer layer 20, so that the device can more easily enter the bipolar conduction mode, and achieve the purpose of suppressing the snapback phenomenon. However, this method often requires a very high length ratio of the P+ collector region 40 to the N+ collector region 10. Since the reverse current of the device only flows from the N+ collector region 10, an overly short N+ collector region 10 will cause uneven distribution of the reverse conduction current of the device and excessively high conduction voltage drop. An overly long N+ collector region 10 is not only prone to cause the snapback phenomenon, but also reduces the area of ​​the P+ collector region 40, reduces the forward conduction hole injection efficiency of the device, and increases the forward conduction voltage drop of the device.

[0027] In order to suppress the snapback phenomenon and avoid the problems of uneven current distribution and excessive on-state voltage drop during reverse conduction in the related art, the present disclosure provides a semiconductor device, such as Figure 4-Figure 6 As shown, it includes: an N-type drift region 1, a collector structure 2 arranged on a first surface A1 of the N-type drift region 1, and a gate structure 3 and an emitter structure 4 arranged on a second surface A2 of the N-type drift region 1; the first surface A1 and the second surface A2 are arranged opposite to each other; The collector structure 2 includes a collector metal layer 21, an N+ collector region 22, a P+ collector region 23, an N-type high resistance region 24, a P-type floating region 25 and an N-type buffer layer 26; wherein, The N-type buffer layer 26 contacts the first surface A1 of the N-type drift region 1, the P-type floating region 25 contacts the surface of the N-type buffer layer 26 away from the N-type drift region 1, and the P-type floating region 25 has a partition region 251; the N-type high resistance region 24 contacts the surface of the P-type floating region 25 away from the N-type drift region 1 and fills the partition region 251, the N+ collector region 22 contacts the surface of the N-type high resistance region 24 away from the N-type drift region 1, the N+ collector region 22 has a through hole H, and the partition region 2 The orthographic projection of 51 on the N-type buffer layer 26 overlaps with the orthographic projection of the through hole H on the N-type buffer layer 26; the P+ collector region 23 includes a first sub-P+ collector region 231 embedded in the surface of the N-type high resistance region 24 away from the N-type drift region 1, and the first sub-P+ collector region 231 corresponds to the position of the through hole H; the collector metal layer 21 contacts the surface of the N+ collector region 22 away from the N-type drift region 1 and fills the through hole H until it contacts the first sub-P+ collector region 231.

[0028] The above-mentioned semiconductor device provided by the embodiment of the present disclosure is mainly aimed at the problem that the conventional reverse-conducting device has a snapback phenomenon when the device is forward-conducted due to the parasitic resistance from the N-type buffer layer above the P+ collector region to the N+ collector region being too small. The present disclosure increases the resistance above the P+ collector region by adding a low-doped N-type high-resistance region above the P+ collector region, and extends the current path above the P+ collector region by setting a P-type floating region with a partition region between the N-type high-resistance region and the N-type buffer layer. The P+ collector region is embedded in the N-type high-resistance region, which increases the longitudinal distance of the N-type high-resistance region in the collector structure, making the distance from the N+ collector region to the middle position of the P+ collector region farther. Therefore, when the device is forward-conducted, the voltage drop generated by the unipolar current from the middle position of the P+ collector region to the N+ collector region is relatively higher, and the PN junction formed by the P+ collector region / N-type high-resistance region is easier to open, and it is easier to eliminate the snapback phenomenon when the device is forward-conducted. Compared with the method in the related art in which the reverse conducting device improves the snapback phenomenon by increasing the length ratio of the P+ collector region to the N+ collector region, thereby increasing the parasitic resistance above the P+ collector region, the structure disclosed in the present invention can improve the snapback phenomenon by increasing the longitudinal distance between the P+ collector region and the N+ collector region. In this way, the length ratio of the P+ collector region to the N+ collector region can be better controlled, and the problems of uneven distribution of the reverse conduction current of the device and excessively high conduction voltage drop can be avoided, so as to compromise and optimize the forward conduction characteristics and reverse conduction characteristics of the device.

[0029] In some embodiments, Figure 4-Figure 6 As shown, when manufacturing the collector structure 2, an N+ substrate (for forming the N+ collector region 22) can be provided first, and then an N-type high resistance region 24 is grown by epitaxial growth on the N+ substrate, and then a P-type floating region 25 is formed on the surface of the N-type high resistance region 24 by ion implantation. When forming the P+ collector region, only the N+ substrate can be etched to form a through hole, or the N+ substrate can be etched to form a through hole and a portion of the thickness of the N-type high resistance region 24 can be etched to form an opening, and then the P+ collector region 23 is formed on the surface of the N-type high resistance region 24 corresponding to the through hole position by ion implantation. Since the P+ collector region 23 is formed by ion implantation after the N+ substrate is partially grooved, no additional photomask is required, and the process is relatively simple. In addition, the present disclosure can retain a very thick N+ substrate, so that the mechanical strength of the semiconductor device is not affected. Furthermore, the present disclosure digs grooves in the N+ substrate and the N-type high resistance region 24 so that the collector metal layer 21 directly contacts the N-type high resistance region 24 and the sidewalls of the thick N+ substrate. Therefore, the retained thick N+ substrate has little effect on the on-resistance and thermal resistance of the device.

[0030] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4As shown, the surface of the first sub-P+ collector region 231 facing away from the N-type drift region 1 is flush with the surface of the N+ collector region 22 facing the N-type drift region 1, that is, only the N+ collector region 22 is etched to form a through hole H, and the surface of the N-type high resistance region 24 facing away from the N-type drift region 1 is not etched, and the first sub-P+ collector region 231 is formed on the surface of the N-type high resistance region 24 exposed by the through hole H by ion implantation, that is, the distance between the lower surface of the first sub-P+ collector region 231 and the upper surface of the N+ collector region 22 is 0. In this way, compared with the related art in which the N+ collector region 22 and the P+ collector region 23 are on the same plane, the present disclosure can increase the resistance above the P+ collector region 23 and extend the current path, so that the PN junction formed by the P+ collector region 23 / N-type high resistance region 24 is easier to open, eliminating the snapback phenomenon when the device is forward-conducted, and improving the device performance.

[0031] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 5 As shown, the N-type high resistance region 24 has an opening V which is arranged corresponding to the through hole H and penetrates part of the thickness of the N-type high resistance region 24. The through hole H and the opening V can be formed by a single etching process. The through hole H and the opening V are interconnected. The first sub-P+ collector region 231 is embedded in the surface of the N-type high resistance region 24 corresponding to the position of the opening V, which is away from the N-type drift region 1, that is, the distance between the lower surface of the first sub-P+ collector region 231 and the upper surface of the N+ collector region 22 is greater than 0, so that the collector metal layer 21 is in contact with the lower surface of the first sub-P+ collector region 231, the side wall of the opening V of the N-type high resistance region 24, and the lower surface and side wall of the N+ collector region 22 at the same time. In this way, the present invention can increase the thickness of the N-type high resistance region 24, further increase the resistance between the N+ collector region 22 and the N-type high resistance region 24, and the distance from the N+ collector region 22 to the middle position of the P+ collector region 23 is farther. Therefore, when the device is forward-conducted, the voltage drop generated by electrons from the middle position of the P+ collector region 23 to the N+ collector region 22 is relatively higher, and the PN junction formed by the P+ collector region 23 / N-type high resistance region 24 is easier to open, eliminating the snapback phenomenon when the device is forward-conducted, improving the device performance, and the device cell size can be further reduced.

[0032] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 5 As shown, the contact between the collector metal layer 21 and the side wall of the opening V of the N-type high resistance region 24 can be a Schottky contact or an Ohmic contact. Preferably, it is a Schottky contact, which will have a better effect on improving the snapback phenomenon.

[0033] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4 and Figure 5As shown, the cross-sectional shape of the through hole H along the thickness direction of the N-type high resistance region 24 can be a rectangle.

[0034] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 5 As shown, the cross-sectional shape of the opening V along the thickness direction of the N-type high resistance region 24 may be a rectangle, and the orthographic projection of the opening V on the N-type buffer layer 26 may overlap with the orthographic projection of the through hole H on the N-type buffer layer 26 .

[0035] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 6 As shown, the P+ collector region 23 also includes a second sub-P+ collector region 232 embedded in the side surface of the N-type high resistance region 24 corresponding to the position of the opening V, the first sub-P+ collector region 231 and the second sub-P+ collector region 232 are an integrated structure, and the surface of the N+ collector region 22 facing the N-type drift region 1 is in contact with the surface of the N-type high resistance region 24 away from the N-type drift region 1 and the surface of the second sub-P+ collector region 232 away from the N-type drift region 1. Figure 6 The structure shown is Figure 5 Compared to the structure shown, Figure 6 The structure shown increases the area of ​​the P+ collector region 23. The P+ collector region 23 covers the contact area between the N-type high resistance region 24 and the collector metal layer 21. The N-type high resistance region 24 does not contact the collector metal layer 21. The P+ collector region 23 covers the bottom and side walls of the opening V of the N-type high resistance region 24. This can avoid the formation of Schottky or ohmic contact between the collector metal layer 21 and the side walls of the opening V of the N-type high resistance region 24, ensuring that the current does not flow through the interface between the collector metal layer 21 and the N-type high resistance region 24. The injection efficiency is higher and the conduction characteristics are better.

[0036] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 6 As shown, the cross-sectional shape of the overall structure of the through hole H and the opening V along the thickness direction of the N-type high resistance region 24 can be a regular trapezoid. This is because the P+ collector region 23 is formed by ion implantation at the bottom and sidewall of the opening V of the N-type high resistance region 24, and the through hole H and the opening V having a regular trapezoidal overall structure are conducive to ion implantation to form the P+ collector region 23 that wraps the N-type high resistance region 24.

[0037] It should be noted that due to the limitations of process conditions or the influence of other factors such as measurement, the "normal trapezoid" may be a standard normal trapezoid, or it may have some deviations and be an approximate normal trapezoid. Therefore, as long as the "normal trapezoid" meets the error allowance, it belongs to the protection scope of the present disclosure.

[0038] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4-Figure 6As shown, the orthographic projection area of ​​the partition region 251 on the N-type buffer layer 26 is smaller than the orthographic projection area of ​​the through hole H (i.e., smaller than the first sub-P+ collector region 231) on the N-type buffer layer 26. This is beneficial to extend the current path above the P+ collector region 23 and further eliminate the snapback phenomenon.

[0039] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 6 As shown, the center of the orthographic projection of the partition area 251 on the N-type buffer layer 26 coincides with the center of the orthographic projection of the through hole H on the N-type buffer layer 26, so that the current distribution will be more uniform when the device is turned on.

[0040] It should be noted that due to the limitations of process conditions or the influence of other factors such as measurement, the "coincidence of the centers of orthographic projection" may be completely coincident or there may be some deviations. Therefore, as long as the relationship of "coincidence of the centers of orthographic projection" meets the error allowance, it falls within the scope of protection of the present disclosure.

[0041] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4-Figure 6 As shown, the surface of the collector metal layer 21 away from the N-type drift region 1 is a flat surface, which is beneficial to improving device performance.

[0042] The above-mentioned semiconductor device provided in the embodiment of the present disclosure can be a reverse conducting IGBT device, or a bipolar device such as a thyristor, a bipolar junction transistor, a MOS controlled thyristor, etc. Devices whose collector structure design is the same as the collector structure of the present disclosure are all within the protection scope of the present disclosure.

[0043] In some embodiments, the semiconductor device provided by the embodiments of the present disclosure may be a reverse conducting IGBT device, such as Figure 4-Figure 6 As shown, the gate structure 3 includes: a gate dielectric layer 31 located on the second surface A2 of the N-type drift region 1, a gate electrode 32 located on the side of the gate dielectric layer 31 away from the N-type drift region 1, and an isolation dielectric layer 33 located on the side of the gate electrode 32 away from the N-type drift region 1; the isolation dielectric layer 33 covers the gate electrode 32 and contacts the gate dielectric layer 31; specifically, the dielectric materials of the gate dielectric layer 31 and the isolation dielectric layer 33 can be SiO2, HfO2, Al2O3, Si3N4, etc.

[0044] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4-Figure 6As shown, the emitter structure 4 includes a P-type well region 41, an N-type emitter region 42, a P-type emitter region 43 and an emitter metal layer 44. The P-type well region 41, the N-type emitter region 42 and the P-type emitter region 43 are embedded in the second surface A2 of the N-type drift region 1. The cross-section of the P-type well region 41 along the thickness direction of the N-type drift region 1 is concave. The P-type emitter region 43 is located in the middle area of ​​the concave shape. The N-type emitter region 42 is located between the P-type emitter region 43 and the side wall of the concave shape. The surface of the gate dielectric layer 31 facing the N-type buffer layer 26 is in contact with the N-type emitter region 42, the P-type well region 41 and the N-type drift region 1. The emitter metal layer 44 wraps the gate structure 3 and is in contact with the N-type emitter region 42 and the P-type emitter region 43.

[0045] Specifically, Figure 4-Figure 6 As shown, the P-type well region 41 , the N-type emitter region 42 and the P-type emitter region 43 are all formed on the second surface A2 of the N-type drift region 1 by ion implantation.

[0046] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4-Figure 6 As shown, the gate structure 3 is a planar gate, and can certainly be a trench gate, which is not limited in the present disclosure.

[0047] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4-Figure 6 As shown, the surface of the emitter metal layer 44 facing away from the N-type drift region 1 is a flat surface, which is beneficial to improving device performance.

[0048] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 4-Figure 6 As shown, the gate structure 3 and the emitter structure 4 can be called the front structure of the semiconductor device, and the collector structure 2 can be called the back structure of the semiconductor device. The front structure of the device (gate structure 3 and emitter structure 4) and the collector structure 2 may not have a one-to-one correspondence. For example, one collector structure 2 may correspond to multiple repeated front structures.

[0049] In some embodiments, the semiconductor device provided by the embodiments of the present disclosure can be based on semiconductor materials such as single crystal silicon, silicon carbide or gallium nitride, and can be prepared through processes such as epitaxy and ion implantation.

[0050] It should be noted that the thickness of each region, the doped ion type, and the ion doping concentration in the semiconductor device provided in the embodiment of the present disclosure can be designed as needed.

[0051] by Figure 5Taking the semiconductor device shown as an example, its working principle is: when the emitter metal layer 44 is connected to a low potential and the collector metal layer 21 is connected to a high potential, when the gate electrode 32 voltage is changed from 0 potential or negative potential to positive potential so that the surface of the P-type well region 41 under the gate dielectric layer 31 is inverted to form an electron channel, the device first works in a forward-conducting unipolar mode, and electrons pass through the electron channel, the N-type drift region 1, the N-type buffer layer 26, the N-type high-resistance region 24 from the N-type emitter region 42 in sequence, and finally enter the N+ collector region 22. The corresponding current distribution diagram (arrow direction) is as follows Figure 7 As shown. Since the N-type high resistance region 24 is low-doped, it forms a Schottky contact or an Ohmic contact with the collector metal layer 21 with a high contact resistance. Therefore, electrons tend to flow away through the N+ collector region 22, the low contact resistance N+ collector region 22 / collector metal layer 21 interface, and the collector metal layer 21, rather than flowing away from the high resistance interface between the N-type high resistance region 24 and the collector metal layer 21. When the semiconductor device provided by the present disclosure is forward-conducting, electrons flow away from Figure 7 The distance from point A to point B1 or point B2 in the circuit becomes longer, that is, the corresponding parasitic resistance increases. The larger the parasitic resistance is under the same current, the larger the voltage drop on the parasitic resistance is. Since the N+ collector region 22 and the P+ collector region 23 are at the same potential, the larger the voltage drop on the parasitic resistance from point A to point B1 or from point A to point B2 is, the larger the voltage difference between the P+ collector region 23 and the N-type high resistance region 24 near point A is, and the easier it is to reach the turn-on voltage of the PN junction formed by the P+ collector region 23 and the N-type high resistance region 24, thereby turning on the PN junction and the device entering the bipolar conduction mode. Therefore, the structure disclosed in the present invention improves the snapback phenomenon by extending the longitudinal distance between the N+ collector region 22 and the P+ collector region 23, making it easier for the device to enter the bipolar conduction mode from the unipolar conduction mode.

[0052] It should be noted that Figure 4 and Figure 6 The structure shown works in the same way as Figure 5 The same difference is Figure 6 It can further ensure that the current flows from point B1 or point B2 to point A, and the effect of improving the snapback phenomenon is better.

[0053] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned semiconductor device. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned semiconductor device, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned semiconductor device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0054] In some embodiments, the method for preparing the semiconductor device provided in the embodiments of the present disclosure is as follows: Figure 8 As shown, it may include: S801, providing an N+ substrate, and forming an N-type high resistance region on one side of the N+ substrate; S802, forming a P-type floating region having a partition region on a surface of the N-type high resistance region away from the N+ substrate; S803, forming an N-type buffer layer and an N-type drift region on a surface of the P-type floating region away from the N+ substrate; S804, forming a part of the emitter structure on a surface of the N-type drift region away from the N-type buffer layer; S805, patterning the N+ substrate to form a through hole that completely penetrates the N+ substrate to form an N+ collector region; S806, forming a first sub-P+ collector region on a surface of the N-type high resistance region corresponding to the through hole position away from the N-type drift region; S807, forming a gate structure on a side of the N-type drift region and a portion of the emitter structure away from the N-type buffer layer; S808, forming another part of the emitter structure on a side of the gate structure away from the N-type drift region; S809 , forming a collector metal layer on a side of the N+ collector region and the first sub-P+ collector region away from the gate structure.

[0055] Specifically, a part of the emitter structure formed in step S804 may form a P-type well region, an N-type emitter region and a P-type emitter region, and another part of the emitter structure formed in step S808 may form an emitter metal layer.

[0056] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, in step S804, when the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region is not patterned, that is, Figure 4 The structure shown.

[0057] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, in step S804, when the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region can be patterned at the same time to form an opening that penetrates part of the thickness of the N-type high resistance region. The through hole and the opening are interconnected, and the corresponding through hole and opening shapes are selected, as well as the injection area is selected, so that the through hole and the opening can be formed respectively. Figure 5 or Figure 6 The structure shown.

[0058] In order to better understand the above preparation method provided in the embodiments of the present disclosure, Figure 5 Taking the semiconductor device shown in FIG. 1 as an example, the preparation process of the semiconductor device is described in detail.

[0059] In some embodiments, Figure 5The manufacturing process of the semiconductor device may specifically include the following steps: (1) If Fig. 9A As shown, an N+ substrate 22' is provided, and an N-type high resistance region 24 is formed by epitaxial growth on one side of the N+ substrate 22'; (2) If Fig. 9B As shown, a hard mask 100 is formed on the surface of the N-type high resistance region 24 away from the N+ substrate 22', and then a P-type floating region 25 is formed on the surface of the N-type high resistance region 24 not covered by the hard mask 100 by ion implantation, and the area below the hard mask 100 forms a partition region 251 of the P-type floating region 25. Subsequently, the hard mask 100 is stripped.

[0060] (3) If Fig. 9C As shown, an N-type buffer layer 26 and an N-type drift region 1 are epitaxially formed in sequence on the surface of the P-type floating region 25 away from the N+ substrate 22'; (4) If Fig.9D As shown, the process is the same as that shown in 9B, using a hard mask and ion implantation method to selectively implant a P-type well region 41, an N-type emitter region 42, and a P-type emitter region 43 in the second surface A2 of the N-type drift region 1; (5) If Fig.9E As shown, a hard mask 200 is formed on the back of the N+ substrate 22', and then a selective etching is performed, and the N+ substrate 22' is etched by dry etching until at least the N-type high resistance region 24 is exposed. In this embodiment, the N+ substrate 22' is formed to completely penetrate the N+ substrate 22' and penetrate a part of the thickness. The remaining N+ substrate 22' is the N+ collector region 22; (6) Fig.9F As shown, the hard mask 200 is maintained, and P-type impurities are implanted on the back of the N+ collector region 22, thereby forming a first sub-P+ collector region 231 on the bottom surface of the opening V. Subsequently, the hard mask 200 is stripped off. Then, an annealing process is performed to activate the implanted ions and repair lattice damage.

[0061] (7) Figure 9G As shown, a gate dielectric film 31' is sequentially formed on the N-type drift region 1, the P-type well region 41, the N-type emitter region 42 and the P-type emitter region 43, and a gate conductive layer 32' is formed on the surface of the gate dielectric film 31'; (8) Figure 9H As shown, the gate conductive layer 32' is selectively etched to form a gate electrode 32; (9) Fig.9I As shown, an isolation dielectric film 33' is grown on the gate electrode 32 by CVD method; (10) Figure 9JAs shown, the isolation dielectric film 33' and the gate dielectric film 31' are selectively dry-etched to form a source contact hole and a gate electrode contact hole (the gate electrode contact hole is not shown in the figure), so as to form a gate dielectric layer 31 and an isolation dielectric layer 33; (11) Figure 9K As shown, on the side of the gate structure 3 away from the N-type drift region 1, the conductive material is filled with the source contact hole and the gate electrode contact hole by a process such as sputtering and deposited on the isolation dielectric layer 33. The conductive material is selectively etched to form an emitter metal layer 44.

[0062] (12) Figure 5 As shown, a collector metal layer 21 is formed by filling a conductive material on the back side of the N+ collector region 22 using a sputtering method, for example.

[0063] Through the above steps (1)-(12) Figure 5 The semiconductor device shown.

[0064] Need to explain yes, Figure 4 and Figure 6 The method for preparing the semiconductor device is as follows Figure 5 The preparation methods shown are basically the same, except that: Figure 4 When etching the N+ substrate 22' in the above step (5), only the N+ substrate 22' is completely etched through without etching the N-type high resistance region 24; Figure 6 When, in the above step (5), the N+ substrate 22' is etched to form a through hole H and a portion of the thickness of the N-type high resistance region 24 is etched to form an opening V, the cross-sectional shape of the overall structure of the through hole H and the opening V along the thickness direction of the semiconductor device is a positive trapezoid. When, in step (6), P-type impurities are injected into the back side of the N+ collector region 22, a second sub-P+ collector region 232 is simultaneously formed on the side wall surface of the opening V.

[0065] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including the semiconductor device provided in the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the semiconductor device, the implementation of the electronic device provided in the embodiment of the present disclosure can refer to the implementation of the semiconductor device provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0066] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, the electronic devices provided by the present disclosure may include other structures in addition to semiconductor devices. For example, when the electronic device is a radar, it also includes: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it also includes: input ports, output ports, etc.

[0067] A semiconductor device, a preparation method thereof, and an electronic device provided by the embodiments of the present disclosure increase the resistance above the P+ collector region by adding a low-doped N-type high-resistance region above the P+ collector region, and extend the current path above the P+ collector region by setting a P-type floating region with a partition region between the N-type high-resistance region and the N-type buffer layer. The P+ collector region is embedded in the N-type high-resistance region, thereby increasing the longitudinal distance of the N-type high-resistance region in the collector structure, and making the distance from the N+ collector region to the middle position of the P+ collector region farther. Therefore, when the device is forward-conducted, the voltage drop generated by the unipolar current from the middle position of the P+ collector region to the N+ collector region is relatively higher, and the PN junction formed by the P+ collector region / N-type high-resistance region is easier to open, and it is easier to eliminate the snapback phenomenon when the device is forward-conducted. Compared with the method in the related art in which the reverse conducting device improves the snapback phenomenon by increasing the length ratio of the P+ collector region to the N+ collector region, thereby increasing the parasitic resistance above the P+ collector region, the structure disclosed in the present invention can improve the snapback phenomenon by increasing the longitudinal distance between the P+ collector region and the N+ collector region. In this way, the length ratio of the P+ collector region to the N+ collector region can be better controlled, and the problems of uneven distribution of the reverse conduction current of the device and excessively high conduction voltage drop can be avoided, so as to compromise and optimize the forward conduction characteristics and reverse conduction characteristics of the device.

[0068] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0069] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: It comprises: an N-type drift region, a collector structure arranged on a first surface of the N-type drift region, and a gate structure and an emitter structure arranged on a second surface of the N-type drift region; The first surface and the second surface are arranged opposite to each other; The collector structure includes a collector metal layer, an N+ collector region, a P+ collector region, an N-type high resistance region, a P-type floating region and an N-type buffer layer; wherein, The N-type buffer layer contacts the first surface of the N-type drift region, the P-type floating region contacts the surface of the N-type buffer layer away from the N-type drift region, and the P-type floating region has a partition region; the N-type high resistance region contacts the surface of the P-type floating region away from the N-type drift region and fills the partition region, the N+ collector region contacts the surface of the N-type high resistance region away from the N-type drift region, and the N+ collector region has a through hole, and the orthographic projection of the partition region on the N-type buffer layer overlaps with the orthographic projection of the through hole on the N-type buffer layer; the P+ collector region includes a first sub-P+ collector region embedded in the surface of the N-type high resistance region away from the N-type drift region, and the first sub-P+ collector region corresponds to the position of the through hole; the collector metal layer contacts the surface of the N+ collector region away from the N-type drift region and fills the through hole until it contacts the first sub-P+ collector region.

2. The semiconductor device according to claim 1, wherein A surface of the first sub-P+ collector region facing away from the N-type drift region is arranged flush with a surface of the N+ collector region facing the N-type drift region.

3. The semiconductor device according to claim 1, wherein The N-type high resistance region has an opening which is arranged corresponding to the through hole and penetrates part of the thickness of the N-type high resistance region. The through hole and the opening are interconnected. The first sub-P+ collector region is embedded in the surface of the N-type high resistance region corresponding to the opening position away from the N-type drift region.

4. The semiconductor device according to claim 2 or 3, characterized in that The cross-sectional shape of the through hole along the thickness direction of the N-type high resistance region is a rectangle.

5. The semiconductor device according to claim 3, wherein: The P+ collector region also includes a second sub-P+ collector region embedded in the side surface of the N-type high resistance region corresponding to the opening position, the first sub-P+ collector region and the second sub-P+ collector region are an integrated structure, and the surface of the N+ collector region facing the N-type drift region is in contact with the surface of the N-type high resistance region away from the N-type drift region and the surface of the second sub-P+ collector region away from the N-type drift region.

6. The semiconductor device according to claim 5, characterized in that The cross-sectional shape of the overall structure of the through hole and the opening along the thickness direction of the N-type high resistance region is a regular trapezoid.

7. The semiconductor device according to claim 1, wherein: An orthographic projection area of ​​the partition region on the N-type buffer layer is smaller than an orthographic projection area of ​​the through hole on the N-type buffer layer.

8. The semiconductor device according to claim 7, wherein: The orthographic projection center of the partition area on the N-type buffer layer coincides with the orthographic projection center of the through hole on the N-type buffer layer.

9. The semiconductor device according to claim 1, wherein: The surface of the collector metal layer away from the N-type drift region is a flat surface.

10. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, characterized in that: The gate structure comprises: a gate dielectric layer located on the second surface of the N-type drift region, a gate electrode located on a side of the gate dielectric layer away from the N-type drift region, and an isolation dielectric layer located on a side of the gate electrode away from the N-type drift region; the isolation dielectric layer covers the gate electrode and contacts the gate dielectric layer; The emitter structure includes a P-type well region, an N-type emitter region, a P-type emitter region and an emitter metal layer. The P-type well region, the N-type emitter region and the P-type emitter region are embedded in the second surface of the N-type drift region. The cross-section of the P-type well region along the thickness direction of the N-type drift region is concave. The P-type emitter region is located in the middle area of ​​the concave shape. The N-type emitter region is located between the P-type emitter region and the side wall of the concave shape. The surface of the gate dielectric layer facing the N-type buffer layer is in contact with the N-type emitter region, the P-type well region and the N-type drift region. The emitter metal layer wraps the gate structure and is in contact with the N-type emitter region and the P-type emitter region.

11. The semiconductor device according to claim 10, wherein: A surface of the emitter metal layer facing away from the N-type drift region is a flat surface.

12. A method for preparing a semiconductor device, characterized in that: For preparing a semiconductor device according to any one of claims 1 to 11, the preparation method comprising: Providing an N+ substrate, and forming an N-type high resistance region on one side of the N+ substrate; Forming the P-type floating region having a partition region on the surface of the N-type high resistance region away from the N+ substrate; Forming an N-type buffer layer and an N-type drift region on a surface of the P-type floating region away from the N+ substrate; forming a part of the emitter structure on a surface of the N-type drift region away from the N-type buffer layer; Patterning the N+ substrate to form a through hole that completely penetrates the N+ substrate to form the N+ collector region; Forming the first sub-P+ collector region on a surface of the N-type high resistance region corresponding to the position of the through hole away from the N-type drift region; forming a gate structure on a side of the N-type drift region and a portion of the emitter structure away from the N-type buffer layer; forming another part of the emitter structure on a side of the gate structure away from the N-type buffer layer; The collector metal layer is formed on a side of the N+ collector region and the first sub-P+ collector region away from the gate structure.

13. The preparation method according to claim 12, characterized in that: When the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region is not patterned.

14. The preparation method according to claim 12, characterized in that: When the N+ substrate is patterned to form a through hole that completely penetrates the N+ substrate, the N-type high resistance region is simultaneously patterned to form an opening that penetrates a portion of the thickness of the N-type high resistance region, and the through hole and the opening are interconnected.

15. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 11.

Images