N-type drift region accumulation-type lateral double-diffusion field effect transistor based on double gates and double channels and preparation method of N-type drift region accumulation-type lateral double-diffusion field effect transistor

Abstract

The invention discloses an N-type drift region accumulation type transverse double-diffusion field effect transistor based on double gates and double channels and a preparation method of the N-type drift region accumulation type transverse double-diffusion field effect transistor. The contradictory relation between the turn-off characteristic and the on-resistance of a device in the prior art is mainly improved. The device comprises a P-type substrate, a first N-type drift region, a trench gate dielectric layer, an N + drain region, an accumulation dielectric layer, top silicon, a source electrode, a drain electrode and a substrate electrode, a second N-type drift region is arranged above the first N-type drift region to form a double-N-type drift region structure, so that the device forms two electron conduction and disappearance paths, and an N-type buffer layer is arranged on one side of the first N-type drift region; a first grid electrode is arranged above the trench gate dielectric layer so as to improve the turn-off characteristic of the device; a first P-type region is arranged on one side of the top layer silicon, and a second grid electrode is arranged above the P-type region, so that a thin electron accumulation layer connecting the channel and the N + drain region is formed on the surface of the first N-type drift region. The on-resistance and turn-off characteristics of the device can be optimized at the same time, and the device can be used for high-power devices of automotive electronics.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a lateral double diffused metal oxide field effect transistor, which can be used as a high-power device for industrial control equipment. Background Art

[0002] Power semiconductor devices are widely used in power management, automotive electronics, industrial control, consumer electronics, communication equipment, renewable energy and other fields. With the continuous improvement of the performance and efficiency requirements of electronic equipment, higher requirements are also put forward for the performance of power semiconductor devices to adapt to higher power density, lower on-resistance and better switching performance. Lateral double diffused metal oxide field effect transistors have become an indispensable part of power semiconductor devices due to their high integration, high frequency characteristics and low on-resistance.

[0003] However, traditional LDMOS devices face the problem of increased on-resistance when pursuing high withstand voltage. This is because high withstand voltage usually requires reducing the doping concentration of the drift region or increasing its length, both of which will lead to an increase in on-resistance. Therefore, there is a contradictory relationship between the withstand voltage capability and on-resistance of the device. In order to solve this problem, researchers have proposed an accumulation-type LDMOS device. This device can significantly reduce the on-resistance while maintaining high withstand voltage, achieving a good compromise between withstand voltage and on-resistance. However, since the accumulation-type device will generate a large number of free carriers in the on state, this reduces the turn-off performance of the device.

[0004] Patent document with application number CN201010619485.4 discloses a method for integrated manufacturing of LDD, LDS and buffer layer of SOI super junction LDMOS device. This method uses SOI substrate to perform ion implantation on top silicon to form alternating N-type and P-type column regions as a lateral super junction structure of the drift region. This structure can significantly increase the electron density when the device is turned on, thereby reducing the on-resistance of the device, but weakens the turn-off characteristics of the device.

[0005] Patent document with application number WOCN23108133 discloses an LDMOS structure, in which the drift region is arranged along the width direction of the LDMOS device as an N-type doped column region and a P-type doped column region arranged alternately; the gate is extended to the N-type doped column region to form an N-type accumulation region to enhance the accumulation effect. Although this structure solves the technical problems of large on-resistance and small saturation current of traditional LDMOS devices, it still does not improve the contradictory relationship between the device turn-off characteristics and the device on-resistance. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose an N-type drift region accumulation type lateral double diffused field effect transistor based on dual-gate dual-channel and a preparation method to improve the contradictory relationship between the device's turn-off characteristics and on-resistance, so as to improve the device's turn-off characteristics and reduce the device's on-resistance.

[0007] To achieve the above purpose, the technical idea of ​​the present invention is: by introducing a second gate and an accumulation layer structure above the second N-type drift region, when a forward voltage is applied to the second gate, electrons can be attracted to the surface of the drift region, thereby generating an extremely high concentration of electron accumulation layer, significantly reducing the device on-resistance; by introducing a first gate on one side of the second N-type drift region, electrons can be extracted when the device is turned off, generating an additional electron disappearance path to improve the device's turn-off characteristics, thereby achieving a good compromise between the device's on-resistance and turn-off characteristics.

[0008] According to the above ideas, the technical solutions of the present invention include the following:

[0009] 1. A double-gate double-channel N-type drift region accumulation type lateral double diffused field effect transistor, comprising: a P-type substrate, a P+ source region, a right N+ source region, a left N+ source region, a P-type base region, an N+ drain region, an accumulation dielectric layer, a top silicon layer, a source electrode, a drain electrode, a substrate electrode and an N-type drift region, characterized in that:

[0010] A first N-type drift region and a second N-type drift region are sequentially arranged above the P-type substrate to form a double N-type drift region structure, and an N-type buffer layer is arranged on one side of the second N-type drift region;

[0011] The P-type base region is located on the other side of the second N-type drift region, and a trench gate dielectric layer (14) is provided on one side of the P-type base region, a heavily doped polysilicon layer is deposited inside the trench gate dielectric layer, and a first gate is provided above the trench gate dielectric layer;

[0012] The top silicon layer has a first P-type region and a second P-type region on both sides, an N+ region on one side of the second P-type region, and a second gate is disposed above the first P-type region to form a double-gate structure with the first gate.

[0013] Furthermore, the P-type substrate is made of any one of silicon, germanium, gallium arsenide, and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3 The substrate electrode is located on the back of the P-type silicon substrate; the first N-type drift region is located on the upper part of the P-type substrate, and its doping concentration is 1×10 13 cm -3 ~1×10 16 cm -3 .

[0014] Furthermore, the accumulation dielectric layer is located above the second N-type drift region, and its material is silicon dioxide or high-K material, with a thickness of 0.05 to 0.2 micrometers. The doping concentration of the second N-type drift region is 1×10 13 cm -3 ~1×10 16 cm -3 .

[0015] Furthermore, the thickness of the top silicon layer is 0.5 to 3 micrometers, and the doping concentration is 1×10 13 cm -3 ~7×10 15 cm -3 The doping concentration of the first P-type region, the second P-type region and the N+ region is 1×10 18 cm -3 ~1×10 20 cm -3 .

[0016] Furthermore, the P+ source region is located above the P-type base region, and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 The P-type base region has a doping concentration of 1×10 16 cm -3 ~2×10 17 cm -3 The right N+ source region and the left N+ source region are located on both sides of the P+ source region, and their doping concentrations are both 1×10 19 cm -3 ~1×10 20 cm -3 ; The source is located on the surface of the P-type base region, which covers the area between the right N+ source region and the left N+ source region.

[0017] Furthermore, the trench gate dielectric layer has a lower boundary located below the P-type base region and the second N-type drift region, and is made of silicon dioxide or high-K material, with a thickness of 0.05 to 0.2 microns.

[0018] Furthermore, the N+ drain region is located above the N-type buffer layer, and its lower boundary does not exceed the lower boundary of the first N-type drift region. The doping concentration of the N-type buffer layer is 1×10 15 cm -3 ~2×10 16 cm -3 ;

[0019] The drain electrode is located on the surface of the N+ drain region and the second P region. The doping concentration of the N+ drain region is 1×10 19 cm -3~1×10 20 cm -3 .

[0020] 2. A method for preparing the above device, characterized in that it comprises the following steps:

[0021] 1) Depositing metal on the back side of the P-type substrate to form a substrate electrode;

[0022] 2) placing a P-type substrate with a substrate electrode deposited thereon in a reaction chamber, and forming a first N-type drift region by growing an N-type epitaxial layer on the front side of the P-type substrate through homoepitaxial growth technology;

[0023] 3) using an etching technique to etch a groove at one end of the upper portion of the first N-type drift region, and growing a groove gate dielectric material therein, and then etching back to form a groove gate dielectric layer with a thickness of 0.05 to 0.2 microns;

[0024] 4) depositing a polysilicon layer on the surface of the trench gate dielectric layer, and performing chemical mechanical planarization on the surface;

[0025] 5) In the first N-type drift region, N-type ions are first injected to form a second N-type drift region, and then P-type ions are injected to form a P-type base region and a P+ source region, and then N-type ions are injected to form a right N+ source region, a left N+ source region, and an N+ drain region;

[0026] 6) growing an accumulated oxide layer on the lower surface of the top silicon layer with a thickness of 0.5 to 3 microns, and bonding it to the surface of the second N-type drift region through a bonding process;

[0027] 7) On the upper surface of the top silicon layer, N-type ions are implanted to form an N+ region, and P-type ions are implanted to form a first P region and a second P region;

[0028] 8) Deposit metal in the area between the left N+ source region and the right N+ source region to form a source electrode; deposit metal on the surface of the polysilicon to form a first gate electrode, and deposit metal on the surface of the first P-type region to form a second gate electrode short-circuited with the first gate electrode; deposit metal on the surfaces of the N+ drain region and the second P-type region to form a drain electrode, thereby completing device fabrication.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] 1. The present invention can improve the performance of the device by setting up a double-gate structure. The first gate can generate an additional electron disappearance path when the device is turned off, thereby improving the turn-off characteristics of the device; the second gate can accumulate a high-concentration electron thin layer on the surface of the second N-type drift region, thereby reducing the on-resistance of the device and reducing the on-loss of the device.

[0031] 2. Since the present invention has a dual drift region structure, the device can form two electron conduction and disappearance paths, wherein the first N-type drift region and the first gate form an electron conduction and disappearance path; the second N-type drift region and the second gate form an electron conduction and disappearance path.

[0032] 3. Since the present invention introduces an N-type buffer layer under the N+ drain region, the current controlled by the first gate can be received by the drain electrode, and the lateral and longitudinal electric fields of the device can be adjusted through electric field modulation to increase the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The structure diagram of the N-type drift region accumulation type lateral double diffused field effect transistor based on double gate and double channel of the present invention;

[0034] Figure 2 The invention is made Figure 1 Schematic diagram of the device process;

[0035] Figure 3 A schematic diagram comparing the transfer characteristics of the device of the present invention and the traditional device;

[0036] Figure 4 A schematic diagram comparing the shutdown characteristics of the device of the present invention and the traditional device;

[0037] Figure 5 It is a current density diagram of two conduction paths of the device of the present invention when it is in the turned-on state. DETAILED DESCRIPTION

[0038] The embodiments and effects of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0039] Reference Figure 1 The present invention is based on a double-gate double-channel N-type drift region accumulation type lateral double diffused field effect transistor, comprising: a P+ source region 1, a right N+ source region 2, a left N+ source region 3, a P-type base region 4, a second N-type drift region 5, an N+ drain region 6, an N-type buffer layer 7, a first N-type drift region 8, a P-type substrate 9, a first P-type region 10, a top silicon layer 11, an N+ region 12, a second P-type region 13, a trench gate dielectric layer 14, an accumulation dielectric layer 15, a polysilicon layer 16, a first gate 17, a source 18, a second gate 19, a drain 20, and a substrate electrode 21, wherein:

[0040] The P-type substrate 9 is made of any one of silicon, germanium, and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3 ;

[0041] The substrate electrode 21 is located on the back side of the P-type substrate 9;

[0042] The first N-type drift region 8 is located above the P-type substrate 9 and has a doping concentration of 1×10 15 cm -3 ~1×10 16 cm -3 ;

[0043] The second N-type drift region 5 is located above the first N-type drift region 8 and has a doping concentration of 1×10 14 cm -3 ~5×10 15 cm -3 ;

[0044] The accumulation dielectric layer 15 is located above the second N-type drift region 5 and has a thickness of 0.05 to 0.2 micrometers. The material of the accumulation dielectric layer 15 is silicon dioxide or high-K dielectric.

[0045] The top silicon layer 11 is located above the accumulation dielectric layer 15 and has a thickness of 0.5 to 3 microns and a doping concentration of 1×10 13 cm -3 ~1×10 16 cm -3 ;

[0046] The first P-type region 10 and the second P-type region 13 are located on both sides of the top silicon 11, and the doping concentrations thereof are both 1×10 18 cm -3 ~1×10 20 cm -3 ;

[0047] The N+ region 12 is located on one side of the second P-type region 13 and has a doping concentration of 1×10 18 cm -3 ~1×10 20 cm -3 ;

[0048] The N-type buffer layer 7 is located on one side of the first-type drift region 5 and has a doping concentration of 1×10 15 cm -3 ~2×10 16 cm -3 ;

[0049] The P-type base region 4 is located on the other side of the second-type drift region 5, and its doping concentration is 1×10 16 cm -3 ~2×10 17 cm -3 ;

[0050] The trench gate dielectric layer 14 is located on one side of the P-type base region 4, has a thickness of 0.5 to 3 microns, and is made of silicon dioxide or high-K dielectric;

[0051] The polysilicon layer 16 is deposited inside the groove formed by the groove gate dielectric layer 14;

[0052] The P+ source region 1 is located on one side of the trench gate dielectric layer 14 and has a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 ;

[0053] The right N+ source region 2 and the left N+ source region 3 are located on both sides of the P+ source region 1, and their doping concentrations are both 1×10 19 cm -3 ~1×10 20 cm -3 ;

[0054] The N+ drain region 6 is located above the N-type buffer layer 7 and has a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 ;

[0055] The source electrode 18 is located on the surface of the area between the right N+ source region 2 and the left N+ source region 3;

[0056] The first gate 17 and the second gate 19 are respectively located on the surface of the polysilicon layer 16 and above the first P-type region 10

[0057] The drain electrode 20 is located on the surface of the second P-type region 13 and the N+ drain region 6 .

[0058] Reference Figure 2 The present invention provides a preparation Figure 1 Three embodiments of the device:

[0059] Embodiment 1: A P-type substrate made of silicon is selected, and a trench gate dielectric layer and an accumulation layer dielectric made of silicon dioxide are manufactured thereon, each with a thickness of 0.08 microns, and the top layer of silicon is a double-gate double-channel N-type drift region accumulation-type lateral double diffused field effect transistor with a thickness of 1 micron.

[0060] Step 1: Use silicon material as the P-type substrate of the device, and deposit metal Al on its back to form a substrate electrode, such as Figure 3 (a).

[0061] Step 2, epitaxially grow a first N-type drift region on the front side of the P-type substrate, such as Figure 2 (b).

[0062] It is set to introduce H2 carrying SiCl4, SiHCl3, SiH4 or SiH2Cl2 silicon source gas into the reaction chamber; the reaction chamber temperature is 1150°C, and the first N-type drift region is epitaxially grown on the front side of the P-type substrate.

[0063] Step 3, a groove is formed by etching at one end of the upper portion of the first N-type drift region, and a groove gate dielectric made of silicon dioxide is grown therein, and then a groove gate dielectric layer is formed by etching back to retain a thickness of 0.08 microns, such as Figure 2 (c).

[0064] Step 4, depositing a polysilicon layer in the groove formed by the trench gate dielectric layer, and using chemical mechanical planarization technology to planarize the surface of the polysilicon, such as Figure 2 (d).

[0065] Step 5, forming a second N-type drift region, a P-type base region, a P+ source region, a right N+ source region, a left N+ source region, an N-type buffer layer and an N+ drain region in the first N-type drift region by an ion implantation process, such as Figure 2 (e).

[0066] 5.1) Boron ions are implanted into the surface of the first N-type drift region to form a concentration of 1×10 15 cm -3 A second N-type drift region 5;

[0067] 5.2) Boron ions are implanted on one side of the second N-type drift region to form an implant concentration of 3×10 16 cm -3 P-type base region 4;

[0068] 5.3) Boron ions are implanted on the surface of the P-type base region to form a concentration of 2×10 19 cm -3 P+ source region 1;

[0069] 5.4) Boron ions are implanted on both sides of the P+ source region to form a concentration of 2×10 19 cm -3 The right N+ source 2 and the left N+ source region 3;

[0070] 5.5) Phosphorus ions are implanted into the other side of the second N-type drift region to form a concentration of 1×10 16 cm -3 N-type buffer layer 7;

[0071] 5.6) Phosphorus ions are implanted on the surface of the N-type buffer layer to form a concentration of 2×10 19 cm -3 N+ drain region 6.

[0072] Step 6, select a top silicon layer with a thickness of 1 micron, grow an accumulated oxide layer on its lower surface, and then bond it to the surface of the second N-type drift region through a bonding process, such as Figure 2 (f).

[0073] Step 7, forming a first P region, a second P region and an N+ region on the upper surface of the top silicon by an ion implantation process, such as Figure 2 (g).

[0074] 7.1) Boron ions are implanted on one side of the top silicon layer to form a concentration of 1×10 19 cm -3 The first P region 10;

[0075] 7.2) Boron ions are implanted on the other side of the top silicon layer to form a concentration of 1×10 19 cm -3 The second P zone 13;

[0076] 7.3) Phosphorus ions are implanted into one side of the second P region to form a concentration of 5×10 18 cm -3 N+ region 12.

[0077] Step 8, make electrodes, such as Figure 2 (h).

[0078] 8.1) Deposit metal Al in the area between the left N+ source region and the right N+ source region to form a source electrode;

[0079] 8.2) depositing metal Al on the surface of polysilicon to form a first gate, and depositing metal Al on the surface of the first P-type region to form a second gate short-circuited with the first gate;

[0080] 8.3) Metal Al is deposited on the surface of the N+ drain region and the second P-type region to form a drain electrode, completing the device fabrication.

[0081] Embodiment 2: A P-type substrate made of germanium is selected, and a double-gate double-channel N-type drift region accumulation-type lateral double diffused field effect transistor is manufactured thereon, the thickness of which is 0.07 microns, the materials of which are both high-K dielectric trench gate dielectric layer and accumulation dielectric, and the thickness of the top silicon is 1.5 microns.

[0082] Step 1: Use germanium material as the P-type substrate of the device, and deposit metal Ti on its back to form a substrate electrode, such as Figure 3 (a).

[0083] Step 2: grow an N-type epitaxial layer on the front side of the P-type substrate to form a first N-type drift region, such as Figure 2 (b).

[0084] H2 carrying GeH4 germanium source gas is introduced into the reaction chamber; under the process condition that the temperature of the reaction chamber is 450° C., a first N-type drift region is epitaxially grown on the front side of the P-type substrate.

[0085] Step 3: A groove is formed by etching at one end of the upper portion of the first N-type drift region, and a high-K dielectric material is grown therein, and then a high-K dielectric layer is formed by etching back to retain a thickness of 0.07 microns. Figure 2 (c).

[0086] Step 4: deposit a polysilicon layer in the groove formed by the high-K dielectric layer, and use chemical mechanical planarization technology to planarize the surface of the polysilicon. Figure 2 (d).

[0087] Step 5: Form a second N-type drift region, a P-type base region, a P+ source region, a right N+ source region, a left N+ source region, an N-type buffer layer and an N+ drain region in the first N-type drift region by an ion implantation process, such as Figure 2 (e).

[0088] Gallium ions are implanted into the surface of the N-type drift region to form a concentration of 8×10 14 cm -3 A second N-type drift region 5;

[0089] Gallium ions are implanted into one side of the second N-type drift region to form a concentration of 3×10 16 cm -3 P-type base region 4;

[0090] Gallium ions are implanted on the surface of the P-type base region to form a concentration of 5×10 19 cm -3 P+ source region 1;

[0091] Gallium ions are injected on both sides of the P+ source region to form a concentration of 5×10 19 cm -3 The right N+ source 2 and the left N+ source region 3;

[0092] Antimony ions are implanted on the other side of the second N-type drift region to form a concentration of 8×10 15 cm -3 N-type buffer layer 7;

[0093] Antimony ions are implanted on the surface of the N-type buffer layer to form a concentration of 5×10 19 cm -3 N+ drain region 6.

[0094] Step 6: grow a 0.07 micron thick high-K dielectric accumulation dielectric layer on the lower surface of the 1.5 micron thick top silicon layer, and then bond it to the surface of the second N-type drift region through a bonding process, such as Figure 2 (f).

[0095] Step 7: Form a first P region, a second P region and an N+ region on the upper surface of the top silicon by ion implantation process, such as Figure 2 (g).

[0096] Gallium ions are implanted on one side of the top silicon layer to form a concentration of 2×10 19 cm -3 The first P region 10;

[0097] Gallium ions are implanted on the other side of the top silicon layer to form a concentration of 2×10 19 cm -3 The second P zone 13;

[0098] Antimony ions are implanted into one side of the second P region to form a concentration of 7×10 18 cm -3 N+ region 12.

[0099] Step 8: Make electrodes, such as Figure 2 (h).

[0100] Deposit metal Ti in the area between the left N+ source region and the right N+ source region to form a source electrode;

[0101] Depositing metal Ti on the surface of polysilicon to form a first gate, and depositing metal Ti on the surface of the first P-type region to form a second gate short-connected with the first gate;

[0102] Metal Ti is deposited on the surface of the N+ drain region and the second P-type region to form a drain electrode, completing the device manufacturing.

[0103] Embodiment 3: A P-type substrate made of silicon carbide is selected, and a trench gate dielectric layer and an accumulation dielectric layer made of silicon dioxide with a thickness of 0.05 microns are produced thereon, and the top silicon layer is a double-gate double-channel second N-type drift region accumulation-type lateral double diffused field effect transistor with a thickness of 1 micron.

[0104] Step A, using silicon carbide material as the P-type substrate of the device, and depositing metal Al on its back to form a substrate electrode, such as Figure 2 (a).

[0105] Step B: epitaxially grow an N-type epitaxial layer to form a first N-type drift region. Figure 2 (b).

[0106] The N-type drift region is grown on the front side of the P-type substrate by epitaxial growth technology. The process conditions for epitaxy are:

[0107] A mixed gas consisting of silicon source gas of H2 and SiH4 and carbon source gas of CH4 is introduced into the reaction chamber;

[0108] Set the reaction chamber temperature to 1600 °C.

[0109] Step C: forming a trench gate dielectric layer on the first N-type drift region.

[0110] C1) etching a groove in an upper end region of the N-type drift region;

[0111] C2) growing a trench gate dielectric made of silicon dioxide inside the groove;

[0112] C3) etching back a trench gate dielectric layer with a thickness of 0.06 microns on the trench gate dielectric.

[0113] Step D, depositing a polysilicon layer on the surface of the trench gate dielectric layer, and using chemical mechanical planarization technology to planarize the surface of the polysilicon layer, such as Figure 2 (d).

[0114] Step E, forming a second N-type drift region, a P-type base region, a P+ source region, a right N+ source region, a left N+ source region, an N-type buffer layer and an N+ drain region in the first N-type drift region by an ion implantation process, such as Figure 2 (e).

[0115] E1) Aluminum ions are implanted into the surface of the first N-type drift region to form a second N-type drift region 5. The concentration of the second N-type drift region is 1×10 15 cm -3 ;

[0116] E2) Aluminum ions are implanted on one side of the second N-type drift region to form a P-type base region 4, the concentration of which is 5×10 16 cm -3 ;

[0117] E3) Aluminum ions are implanted on the surface of the P-type base region to form a P+ source region 1. The concentration of the P+ source region is 2×10 19 cm -3 ;

[0118] E4) Arsenic ions are implanted on both sides of the P+ source region to form a right N+ source 2 and a left N+ source region 3. The concentration of the right N+ source and the left N+ source region is 3×10 19 cm -3 ;

[0119] E5) Arsenic ions are implanted on the other side of the second N-type drift region to form an N-type buffer layer 7, the concentration of which is 8×10 15 cm -3 ;

[0120] E6) Arsenic ions are implanted on the surface of the N-type buffer layer to form an N+ drain region 6, the concentration of which is 3×10 19 cm -3 .

[0121] Step F, select a top silicon layer with a thickness of 1 micron, grow a 0.06 micron thick accumulated oxide layer of silicon dioxide on its lower surface, and then bond it to the surface of the second N-type drift region through a bonding process, such as Figure 2 (f).

[0122] Step G, forming a first P region, a second P region and an N+ region on the upper surface of the top silicon by an ion implantation process, such as Figure 2 (g).

[0123] G1) Gallium ions are implanted on one side of the top silicon layer to form a first P region 10, the concentration of which is 4×10 19 cm -3 ;

[0124] G2) Gallium ions are implanted on the other side of the top silicon to form a second P region 13, and the concentration of the second P region is 4×10 19 cm -3 ;

[0125] G3) Antimony ions are implanted into one side of the second P region to form an N+ region 12, and the concentration of the N+ region is 6×10 18 cm -3 .

[0126] Step H, making electrodes, such as Figure 2 (h).

[0127] Metal Al is deposited in the area between the left N+ source region and the right N+ source region to form a source electrode;

[0128] Depositing metal on the surface of polysilicon to form a first gate, and depositing metal Al on the surface of the first P-type region to form a second gate short-connected with the first gate;

[0129] Metal Al is deposited on the surface of the N+ drain region and the second P-type region to form a drain electrode, completing the device manufacturing.

[0130] The effect of the present invention can be further illustrated by the following simulation results:

[0131] 1. Simulation conditions

[0132] The software used for simulation is Sentaurus TCAD.

[0133] Set the device's withstand voltage level to 200V.

[0134] 2. Simulation content

[0135] Simulation 1: Under the above simulation conditions, the output characteristics of the device of embodiment 1 of the present invention and the traditional device are simulated respectively. The results are as follows: Figure 3 As shown. Figure 3It can be seen that the specific on-resistance of the traditional LDMOS is 37.3mΩ·cm 2 , while the specific on-resistance of the present invention is 3.5mΩ·cm 2 , compared with the traditional LDMOS device, the present invention reduces 90.6%.

[0136] Simulation 2: Under the above simulation conditions, the turn-off characteristics of the device in Embodiment 1 of the present invention and the conventional device are simulated respectively. The results are as follows: Figure 4 As shown. Figure 4 It can be seen that the turn-off time of the conventional LDMOS is 0.112 microseconds, while the turn-off time of the device of the present invention is 0.103 microseconds, and the turn-off characteristic of the device of the present invention is improved by 8.0%.

[0137] Simulation 3, under the above simulation conditions, simulates the current density of the two conduction paths of the device in the embodiment 1 of the present invention when it is in the conduction state. The results are as follows: Figure 5 As shown. Figure 5 It can be seen that the current density of the conduction path formed by the first gate in the first N-type drift region is 1×10 3 A / cm 2 ; The current density of the conduction path formed by the second gate in the second N-type drift region is 3×10 5 A / cm 2 , the difference between the current densities of the two is within two orders of magnitude, indicating that the first gate can serve as a good disappearing path for electrons, thereby improving the turn-off characteristics of the device.

[0138] The above are only several preferred embodiments of the present invention and do not constitute any limitation to the present invention. It should be pointed out that, for those skilled in the art, after understanding the content and principle of the present invention, it is possible to make various modifications and changes in form and details without departing from the principle and structure of the present invention. For example, the LDMOS device in the present invention can be a P-type channel in addition to an N-type channel, but these modifications and changes based on the idea of ​​the present invention are still within the protection scope of the present invention.

Claims

1. A double-gate double-channel N-type drift region accumulation type lateral double diffused field effect transistor, include: A P-type substrate (9), a first N-type drift region (8), a P+ source region (1), a right N+ source region (2), a left N+ source region (3), a P-type base region (4), an N+ drain region (6), an accumulation dielectric layer (15), a top silicon layer (11), a source electrode (18), a drain electrode (20) and a substrate electrode (21), characterized in that: The first N-type drift region (8) has a second N-type drift region (5) disposed thereon, and an N-type buffer layer (7) is disposed on one side of the second N-type drift region; The P-type base region (4) is located on the other side of the second N-type drift region (5), and a trench gate dielectric layer (14) is provided on one side of the P-type base region, a heavily doped polysilicon layer (16) is deposited inside the trench gate dielectric layer, and a first gate (17) is provided above the trench gate dielectric layer; The top silicon (11) has a first P-type region (10) and a second P-type region (13) on both sides thereof, a second gate (19) is provided above the first P-type region, and an N+ region (12) is provided on one side of the second P-type region.

2. The lateral double diffused field effect transistor according to claim 1, Features: The P-type substrate (9) is made of any one of silicon, germanium, gallium arsenide and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3 , a substrate electrode (21) is located on the back side of the P-type substrate; The first N-type drift region (8) is located on the upper part of the P-type substrate (9) and has a doping concentration of 1×10 15 cm -3 ~1×10 16 cm -3 .

3. The lateral double diffused field effect transistor according to claim 1, Features: The accumulation dielectric layer (15) is located above the second N-type drift region (5), and its material is silicon dioxide or high-K material, with a thickness of 0.05 to 0.2 micrometers. The doping concentration of the second N-type drift region is 1×10 14 cm -3 ~5×10 15 cm -3 .

4. The lateral double diffused field effect transistor according to claim 1, Features: The thickness of the top silicon layer (11) is 0.5 to 3 micrometers, and the doping concentration is 1×10 13 cm -3 ~7×10 15 cm -3 . The doping concentrations of the first P-type region (10), the second P-type region (13) and the N+ region (12) are all 1×10 18 cm -3 ~1×10 20 cm -3 .

5. The lateral double diffused field effect transistor according to claim 1, Features: The P+ source region (1) is located above the P-type base region (4) and has a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 ; The P-type base region (4) has a doping concentration of 1×10 16 cm -3 ~2×10 17 cm -3 ; The right N+ source region (2) and the left N+ source region (3) are located on both sides of the P+ source region (1), and their doping concentrations are both 1×10 19 cm -3 ~1×10 20 cm -3 ; The source electrode (18) is located on the surface of the P-type base region (4), and covers the area between the right N+ source region (2) and the left N+ source region (3).

6. The lateral double diffused field effect transistor according to claim 1, Features: The groove gate dielectric layer (14) has a lower boundary located below the P-type base region (4) and the second N-type drift region (5), is made of silicon dioxide or high-K material, and has a thickness of 0.05 to 0.2 micrometers.

7. The lateral double diffused field effect transistor according to claim 1, Features: The N+ drain region (6) is located above the N-type buffer layer (7), and its lower boundary does not exceed the lower boundary of the first N-type drift region (8). The doping concentration of the N-type buffer layer (7) is 1×10 15 cm -3 ~2×10 16 cm -3 ; The drain electrode (20) is located on the surface of the N+ drain region (6) and the second P region (13), and the doping concentration of the N+ drain region is 1×10 19 cm -3 ~1×10 20 cm -3 .

8. A method for preparing the device according to claim 1, It is characterized in that The following steps are involved: 1) depositing metal on the back side of a P-type substrate (9) to form a substrate electrode (21); 2) placing a P-type substrate on which a substrate electrode is deposited in a reaction chamber, and forming a first N-type drift region (8) by epitaxially growing an N-type epitaxial layer on the front side of the P-type substrate through homoepitaxial technology; 3) using an etching technique to etch a groove at one end of the upper portion of the first N-type drift region (8), growing a groove gate dielectric material therein, and then etching back to form a groove gate dielectric layer (14) with a thickness of 0.05 to 0.2 microns; 4) depositing a polysilicon layer (16) on the surface of the trench gate dielectric layer (14), and performing chemical mechanical flattening treatment on the surface; 5) In the first N-type drift region (8), N-type ions are firstly injected to form a second N-type drift region (5), and then P-type ions are injected to form a P-type base region (4) and a P+ source region (6), and then N-type ions are injected to form a right N+ source region (2), a left N+ source region (3) and an N+ drain region (6); 6) growing an accumulated oxide layer (15) on the lower surface of the top silicon layer (11) with a thickness of 0.5 to 3 microns, and bonding it to the surface of the second N-type drift region through a bonding process; 7) On the upper surface of the top silicon layer (11), N-type ions are implanted to form an N+ region (12), and P-type ions are implanted to form a first P region (10) and a second P region (13); 8) Depositing metal in the region between the left N+ source region (3) and the right N+ source region (2) to form a source electrode (18); depositing metal on the surface of the polysilicon (16) to form a first gate electrode (17); depositing metal on the surface of the first P-type region (10) to form a second gate electrode (19) short-circuited with the first gate electrode; and depositing metal on the surfaces of the N+ drain region (6) and the second P-type region (13) to form a drain electrode (20), thereby completing device fabrication.

9. The method according to claim 8, Features: In step (2), a carrier gas of H 2 , the reaction gas is SiCl 4 、SiHCl 3 、SiH 4 or SiH 2 Cl 2 of silicon source gas, and set its ambient temperature to 1150°C ~ 1200°C.

10. The method according to claim 8, Features: The N-type ions in step (5) and step (7) are any one of phosphorus, arsenic, and antimony; the P-type ions are any one of boron, aluminum, and gallium; The second N-type drift region (5) formed by injecting N-type ions has a concentration of 1×10 14 cm -3 ~5×10 15 cm -3 ; The right N+ source region (2), the left N+ source region (3) and the N+ drain region (6) are formed by injecting N-type ions, and the concentration of each of the N+ source regions is 1×10 19 cm -3 ~1×10 20 cm -3 ; The N-type buffer layer (7) formed by injecting N-type ions has a concentration of 1×10 15 cm -3 ~2×10 16 cm -3 ; The N+ region (12) formed by injecting N-type ions has a concentration of 1×10 18 cm -3 ~1×10 20 cm -3 ; The P-type base region (4) formed by injecting P-type ions has a concentration of 1×10 16 cm -3 ~2×10 17 cm -3 ; The first P region (10) and the second P region (13) are formed by injecting P-type ions, and the concentration of each of the P-type ions is 1×10 18 cm -3 ~1×10 20 cm -3 .

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