Double-channel asymmetric groove type silicon carbide MOS (Metal Oxide Semiconductor) device and preparation method thereof

Abstract

The invention provides a double-channel asymmetric groove type silicon carbide MOS device and a preparation method thereof, and the preparation method comprises the steps: growing an epitaxial layer above a SiC substrate and a buffer layer, and forming a current expansion layer and a symmetric P + well region on the surface of the epitaxial layer; and forming a P-base region, an N-plus region and a P-plus region in sequence, etching a groove above the P + well region, and etching the P + well region to form an L shape; oxide and polycrystalline silicon deposition is carried out in the trench to form an L-shaped separation gate and a columnar separation gate; oxide and polycrystalline silicon deposition continues to be carried out in the groove, and a grid electrode is formed; and finally generating a source electrode and a drain electrode. According to the MOS device prepared by the invention, the P + well region is newly added to wrap the bottom of the groove, a PN junction is formed to share electricity at the corner of the groove, multiple layers of separation gates are formed in the groove, an electric field at the bottom of the groove can be reduced, and the gate oxide reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a double-channel asymmetric trench type silicon carbide MOS device and a preparation method thereof. Background Art

[0002] With the rise of fast charging of mobile phones, domestic new energy vehicles and brushless motors, the demand for medium and high voltage MOSFETs is increasing, and medium voltage power devices are beginning to flourish. As one of the representatives of medium and high voltage MOSFETs, asymmetric trench silicon carbide MOS devices are widely used as switching devices in motor drive systems, inverter systems and power management systems. They are core power control components, and their specific on-resistance is a very important parameter. Compared with ordinary trench silicon carbide MOS devices, asymmetric trench silicon carbide MOS devices have an increased P + The well region effectively alleviates the electric field concentration effect at the bottom of the trench, improves the device's withstand voltage level, and due to the P + The well region half-wraps the gate, so that the contact area between the gate and the drain is reduced, the Miller capacitance is smaller, the switching loss is reduced, and the switching speed of the device is improved.

[0003] However, the asymmetric trench silicon carbide MOS device has only one current conduction path, with a large on-resistance, and a large electric field at the corner of the trench gate oxide layer, which reduces the reliability of the device gate oxide. Summary of the invention

[0004] The object of the present invention is to provide a dual-channel asymmetric split-gate trench silicon carbide MOS device and a preparation method thereof. + The well region wraps around the bottom of the trench, forming a PN junction to share the electricity at the corner of the trench; the CSL layer replaces the P junction on the right side of the trench. + The well region forms a second current path, which reduces the device's specific on-resistance and improves the device's current-carrying capacity.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a method for preparing a dual-channel asymmetric trench silicon carbide MOS device, comprising: S1, preparing a SiC substrate and a SiC buffer layer, forming an epitaxial layer on the SiC substrate, and forming a drift layer, a current spreading layer and two symmetrical P + Well region; S2, continuing to grow an epitaxial layer on the surface of the epitaxial layer processed in S1, and performing ion implantation on the surface of the epitaxial layer to form a P-base region, an N-plus region and alternately distributed P-plus regions; S3, etching the surface of the epitaxial layer after being processed in S2, +A trench is formed above the well region, and after etching, the P + The well region is etched to form an L shape; S4, depositing oxide and polysilicon in the trench to form an L-shaped separation gate and a columnar separation gate; S5, continuing to deposit oxide and polysilicon in the trench to form a gate; S6, symmetrically etching a portion of the oxide layer at the center of the upper surface of the P-plus region to form a source trench; S7, generate source and drain.

[0006] Preferably, the specific implementation process of S1 includes: Selecting an N-type doped 4H-SiC substrate and an N-type doped 4H-SiC buffer layer, and growing an N-type doped 4H-SiC drift layer on the 4H-SiC substrate by a MOCVD homoepitaxial method; forming a current spreading layer on the upper surface of the drift layer by high energy ion implantation; After cleaning, coating, photolithography and developing the drift layer, high-energy ion implantation is performed symmetrically from the center of the upper surface of the current spreading layer with a spacing of 0.4 um to form two symmetrical P + Well region; The current spreading layer is generated again; The doping element of the 4H-SiC substrate is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 10-12um, width is 2-6um; The doping element of the 4H-SiC buffer layer is nitrogen or phosphorus, and the doping concentration is 1×10 17 ~1×10 20 cm -3 , thickness is 1-5um, width is 2-6um; The doping element of the drift layer is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 6-15um, width is 2-6um; The doping element of the current spreading layer is aluminum, and the doping concentration is 1×10 15 ~1×10 17 cm -3 , thickness is 0.2-4um, width is 2-6um; The P + The doping element of the well region is aluminum or boron, and the doping concentration is 1×1017 ~1×10 19 cm -3 , each P + The thickness of the well region is 0.1-1um and the width is 0.2-1um; The doping element for the current spreading layer is aluminum, with a doping concentration of 1×10 15 ~1×10 17 cm -3 , thickness is 0.2-4um, width is 2-6um.

[0007] Preferably, the specific implementation process of S2 includes: Continue to grow an epitaxial layer on the surface of the epitaxial layer treated with S1 by depositing SiC; Forming a P-base region above the current spreading layer by implanting P-type ions on the surface of the epitaxial layer and annealing; Forming an N-plus region of equal width above the P-base region by N-type ion implantation on the surface of the epitaxial layer; On the surface of the N-plus region, P + The well region is centrally symmetrical, and high-energy ion implantation is performed symmetrically with a spacing of 1.6 μm to form a P-plus region with a spacing distribution, and the thickness of the P-plus region is greater than the thickness of the N-plus region; The doping element of the epitaxial layer that continues to grow is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 0.6-2um, width is 2-6um; The P-base region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1 × 10 17 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 1-4um; The N-plus region is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1 × 10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 1-4um; The P-plus region is P-type doped, and the doping element is aluminum or boron. The doping concentration of each P-plus region is 1 × 10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 0.4-2um.

[0008] Preferably, the specific implementation process of S3 includes: The epitaxial layer treated by S2 is cleaned, coated, photolithographically processed and developed, the P-plus area and the N-plus area which do not need to be etched are protected by photoresist, and the epitaxial layer is etched to form a groove; The trench etching depth does not exceed P + well region, the trench is located in the P + well region, wider than the P + The well area is small; the left side of the groove is connected to the P + The left side of the well region is aligned so that P + The well region is etched to form an L shape; The groove width is 0.5-2um, and the thickness is 2-3um.

[0009] Preferably, the specific implementation process of S4 includes: The epitaxial layer treated by S3 is cleaned, coated, photolithographically processed and developed, and oxide is deposited on the groove; wherein the thickness of the oxide deposited at the bottom of the groove is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall of the groove is 0.05um-0.2um; Polysilicon is deposited in the trench after oxide deposition, with a deposition thickness of 0.5um-3um and a width of 0.3um-2um; Etch the polysilicon on the left side of the trench to a thickness of 0.5um-1.4um and a width of 0.1um-0.5um, so that the remaining polysilicon area is L-shaped, forming an L-shaped separation gate; After etching, an oxide layer is deposited on the bottom and sidewalls of the trench. The thickness of the oxide layer deposited on the bottom is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall is 0.05um-0.2um. Polysilicon is deposited in the trench after oxide deposition to form a columnar separation gate, with a deposition thickness of 0.5um-1um and a width of 0.2um-1um.

[0010] Preferably, the specific implementation process of S5 includes: Continue to deposit oxide on the trench after S4 treatment, the thickness of the oxide layer deposited on the bottom is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall of the trench is 0.05-0.2um; Continue to deposit polysilicon in the trench to form a gate, the deposition thickness is 0.6um-2um, and after deposition, the upper surface of the gate is flush with the upper surfaces of the N plus region and the P plus region; Oxide deposition is performed above the gate, so that the deposited oxide layer is flush with the upper surface of the epitaxial layer.

[0011] Preferably, the specific implementation process of S6 includes: At the center of the upper surface of the P-plus region, part of the oxide layer is symmetrically etched to a thickness of 0.2um-1um and a width of 0.1um-1um to form a source trench.

[0012] Preferably, the specific implementation process of S7 includes: Deposit a metal layer on the top of the epitaxial layer and in the source trench to form a source electrode with a deposition thickness of 2um-4um; A drain is formed by connecting a metal layer to the bottom of the substrate.

[0013] In a second aspect, the present invention provides a dual-channel asymmetric trench type silicon carbide MOS device, which is manufactured using the above-mentioned method for manufacturing a dual-channel asymmetric trench type silicon carbide MOS device.

[0014] The beneficial effects of the present invention are: (1) The present invention provides a dual-channel asymmetric trench silicon carbide MOS device, in which a multi-layer separation gate is formed inside the trench. The multi-layer separation gate includes: a gate 1 at the top, a columnar separation gate 2 at the left side of the bottom, and an "L"-shaped separation gate 3 at the right side of the bottom. This structure further reduces the electric field at the bottom of the trench and improves the gate oxygen reliability of the device.

[0015] (2) The dual-channel asymmetric trench-type silicon carbide MOS device provided by the present invention converts the original right side of the trench P + The well region is replaced by a current expansion layer to form a second current path, which reduces the device's specific on-resistance and improves the device's current-carrying capacity.

[0016] (3) The dual-channel asymmetric trench silicon carbide MOS device of the present invention thickens the oxide layer thickness between the right side of the original gate and the source, reduces the gate-source capacitance and prevents the gate and source from punching through.

[0017] (4) The dual-channel asymmetric trench silicon carbide MOS device of the present invention has a newly added floating P + The well region wraps around the bottom of the trench to form a PN junction to share the electric field at the corner of the trench and improve the gate oxide reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart of preparing a double-channel asymmetric trench silicon carbide MOS device provided by the present invention; Figure 2 The present invention provides a double-channel asymmetric trench type silicon carbide MOS device for preparing a current expansion layer, a P + Schematic diagram of the structure after the well region, P-base region, N-plus region and P-plus region; Figure 3It is a schematic diagram of the structure of the double-channel asymmetric trench-type silicon carbide MOS device provided by the present invention after the trenches are etched; Figure 4 It is a schematic diagram of the structure of the double-channel asymmetric trench silicon carbide MOS device provided by the present invention after preparing an L-shaped separated gate; Figure 5 It is a schematic diagram of the structure of the double-channel asymmetric trench-type silicon carbide MOS device provided by the present invention after preparing a columnar separation gate; Figure 6 It is a schematic structural diagram of the double-channel asymmetric trench silicon carbide MOS device provided by the present invention after preparing the original gate; Figure 7 It is a schematic diagram of the structure of the double-channel asymmetric trench silicon carbide MOS device provided by the present invention after preparation; Figure 8 It is a schematic diagram comparing the double-channel asymmetric trench-type silicon carbide MOS device structure and the single-layer split-gate structure provided by the present invention; Fig. 9 It is a schematic diagram comparing the electric field distribution diagrams of the double-channel asymmetric trench silicon carbide MOS device and the single-layer separated gate structure provided by the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0020] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0023] The specific embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0024] In a first aspect, the present invention provides a method for preparing a dual-channel asymmetric trench silicon carbide MOS device, such as Figure 1 As shown, the following steps are included: S100, preparing a SiC substrate and a SiC buffer layer; forming an epitaxial layer on the SiC substrate by a MOCVD homoepitaxial method; forming a drift layer, a current spreading layer and two symmetrical P layers on the epitaxial layer by an ion implantation method. + Well region; S200, further growing an epitaxial layer by depositing SiC, and then forming a P-base region, an N-plus region, and a P-plus region by ion implantation; S300, etching the surface of the epitaxial layer after S200 treatment, + forming a trench above the well region; S400, depositing an oxide layer and polysilicon in the trench to form an "L"-shaped separation gate and a columnar separation gate; S500, continuing to deposit an oxide layer in the trench, depositing polysilicon on the oxide layer to form a gate, and finally depositing an oxide layer to make the deposited oxide layer flush with the upper surface of the epitaxial wafer; S600, at the center of the upper surface of the P-plus region, a portion of the oxide layer is symmetrically etched to form a source trench; S700, depositing metal in the epitaxial layer and the source trench to form a source electrode, and externally connecting metal on the substrate to form a drain electrode.

[0025] In the present invention, the specific implementation process of step S100 is as follows: S110, the substrate is selected as N-type doped 4H-SiC, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 10-12um, width is 2-6um.

[0026] Preferably, the doping element is nitrogen, and the doping concentration is 1 × 10 18 cm-3 , thickness is 10um and width is 2.4um.

[0027] The buffer layer is N-type doped 4H-SiC, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 17 ~1×10 20 cm -3 , thickness is 1-5um, width is 2-6um.

[0028] Preferably, the doping element is nitrogen, and the doping concentration is 1 × 10 17 cm -3 , thickness is 2um and width is 2.4um.

[0029] The N-type doped 4H-SiC drift layer was grown on the 4H-SiC substrate by MOCVD homoepitaxial method. The doping element was nitrogen or phosphorus, and the doping concentration was 1×10 15 ~1×10 16 cm -3 , thickness is 6-15um, width is 2-6um.

[0030] Preferably, the doping element is nitrogen, and the doping concentration is 6.5 × 10 15 cm -3 , thickness is 8um and width is 2.4um.

[0031] S120, high-energy ion implantation is performed from the upper surface of the drift layer to form a current expansion layer. The doping element is aluminum, and the doping concentration is 1×10 15 ~1×10 17 cm -3 , thickness is 0.2-4um, width is 2-6um.

[0032] The preferred doping concentration is 8×10 16 cm -3 , thickness is 0.3um and width is 2.4um.

[0033] S130, after cleaning, coating, photolithography and developing the drift layer, high-energy ion implantation is performed symmetrically from the center of the upper surface of the current spreading layer with a spacing of 0.4 um to form two symmetrical P + Well region. + The well region is a highly doped P region, the doping element is aluminum or boron, and the doping concentration is 1×10 17 ~1×10 19 cm -3 , each P + The thickness of the well region is 0.1-1um and the width is 0.2-1um.

[0034] Preferably, the doping element is aluminum, and the doping concentration is 6×10 18 cm -3 , thickness is 0.3um and width is 1um.

[0035] S140, the current spreading layer is generated again, which is N-type doped, the doping element is aluminum, and the doping concentration is 1×10 15 ~1×10 17 cm -3 , its thickness is 0.2-4um and its width is 2-6um.

[0036] The preferred doping concentration is 8×10 16 cm -3 , thickness is 2.3um, width is 2.4um; forming a structure such as Figure 2 shown.

[0037] In the present invention, the specific implementation process of step S200 is as follows: S210, further growing an epitaxial layer on the epitaxial wafer treated in S100 by depositing SiC, wherein the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 0.6-2um, width is 2-6um.

[0038] S220, forming a P-base region above the current spreading layer by implanting P-type ions on the surface of the epitaxial layer and performing annealing.

[0039] The P-base region is P-type doped and high-energy ion implantation is performed. The element is aluminum or boron, and the doping concentration is 1×10 17 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 1-4um.

[0040] Preferably, the doping element is aluminum, and the doping concentration is 1.5×10 17 cm -3 , thickness is 0.8um and width is 2.4um.

[0041] S230, forming an N-plus region of equal width above the P-base region by N-type ion implantation on the surface of the epitaxial layer, The N-plus region is N-type doped and high-energy ion implantation is performed. The element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 1-4um; Preferably, the doping element is nitrogen, and the doping concentration is 5×10 19 cm -3 , thickness is 0.3um and width is 2.4um.

[0042] S240, forming spaced P-plus regions on the surface of the N-plus region by implanting P-type ions, The P-plus region is P-type doped. + The well region is centrally symmetrical, and high-energy ion implantation is performed symmetrically with a spacing of 1.6 μm to form a P-plus region with a spacing distribution, and the thickness of the P-plus region is greater than that of the N-plus region. The doping element is aluminum or boron, and the doping concentration of each P-plus region is 1 × 10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 0.4-2um; The preferred doping element is aluminum, with a doping concentration of 5×10 19 cm -3 , thickness is 0.35um, width is 0.5um. The structure is as follows Figure 2 .

[0043] It should be noted that the internal structure and preparation process of epitaxial wafers are common in the industry and there are no special requirements.

[0044] In the present invention, the specific implementation process of step S300 is as follows: The epitaxial wafer treated by S200 is cleaned, coated, photolithographed and developed, and the P-plus area and N-plus area that do not need to be etched are protected with photoresist, and then the epitaxial layer is etched to form grooves.

[0045] It should be noted that the trench etching depth does not exceed P + Well region, located in P + Above the well region, the width is greater than P + The well area is small, and the left side of the trench is connected to the P + The left side of the well region is aligned so that P + The well region is etched into an L shape.

[0046] Among them, the groove width is 0.5-2um and the thickness is 2-3um.

[0047] Preferably, the groove width is 1 um and the thickness is 2.6 um. Figure 3 shown.

[0048] In the present invention, the specific implementation process of step S400 is as follows: S410, cleaning, gluing, photolithography and developing the epitaxial wafer, and performing oxide deposition and polysilicon deposition on the trench; Specifically, oxide deposition is performed on the bottom and sidewalls of the trench, the thickness of the oxide layer deposited on the bottom of the trench is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewalls of the trench is 0.05um-0.2um.

[0049] Polysilicon is deposited on the trench after oxide deposition, with a deposition thickness of 0.5um-3um and a width of 0.3um-2um. It should be noted that the width of the deposited polysilicon is smaller than the width of the trench.

[0050] Preferably, the thickness of the oxide layer deposited at the bottom of the trench is 0.15 um, and the thickness of the oxide layer deposited on the sidewall of the trench is 0.15 um.

[0051] Preferably, the thickness of the polysilicon deposition is 1.4 um and the width is 0.7 um.

[0052] S420, the polysilicon on the left side of the trench is etched to a thickness of 0.5um-1.4um and a width of 0.1um-0.5um, so that the remaining polysilicon area is L-shaped, forming an "L"-shaped separation gate, such as Figure 4 The grid 3 in the middle.

[0053] Preferably, the polysilicon on the left side of the trench is etched to a thickness of 1 um and a width of 0.25 um.

[0054] S430, after etching, an oxide layer is deposited on the bottom and sidewalls of the trench, wherein the thickness of the oxide layer deposited on the bottom is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall is 0.05um-0.2um; Polysilicon is deposited in the trench after oxide deposition to form a columnar separation gate, with a deposition thickness of 0.5um-1um and a width of 0.2um-1um. It should be noted that the width of the deposited polysilicon is smaller than the trench width. Figure 5 The grid 2 in the middle.

[0055] Preferably, the thickness of the oxide layer deposited at the bottom is 0.05 um, the thickness of the oxide layer deposited on the left side wall of the groove is 0.15 um, and the thickness of the oxide layer deposited on the right side wall of the groove is 0.05 um.

[0056] Preferably, the polysilicon deposition thickness is 0.5 um and the width is 0.2 um.

[0057] In the present invention, the specific implementation process of step S500 is as follows: S510, continuing to deposit oxide on the trench processed by S400, the thickness of the oxide layer deposited on the bottom is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall of the trench is 0.05-0.2um; S520, depositing polysilicon in the trench to form a gate, the deposition thickness is 0.6um-2um, and after deposition, the upper surface of the gate is flush with the upper surfaces of the N-plus region and the P-plus region; Figure 6 The grid 1 in the.

[0058] Preferably, the deposition thickness is 0.85 um.

[0059] S530, depositing oxide on the gate so that the deposited oxide layer is flush with the upper surface of the epitaxial layer. Figure 6 The structure shown.

[0060] In the present invention, the specific implementation process of step S600 is as follows: S610, at the center of the upper surface of the P-plus region, a portion of the oxide layer is symmetrically etched with a thickness of 0.2um-1um and a width of 0.1um-1um to form a source trench, such as Figure 7 shown.

[0061] Preferably, the etching thickness is 0.2um and the width is 0.4um.

[0062] In the present invention, the specific implementation process of step S700 is as follows: S710, depositing a metal layer on the top of the epitaxial layer and in the source trench to form a source electrode, with a deposition thickness of 2um-4um; preferably, the deposition thickness is 3um; S720, a drain is formed on the bottom of the substrate by connecting the metal layer externally. The final structure is as follows Figure 7 shown.

[0063] It should be noted that a source ohmic contact metal is provided in the source electrode; and a drain ohmic contact metal is provided in the drain electrode.

[0064] In a second aspect, the present invention provides a dual-channel asymmetric trench silicon carbide MOS device, which is prepared by the above-mentioned preparation method, and has a structure as shown in Figure 7 As shown. Compared with the single-layer split gate structure Figure 8 shown.

[0065] The present invention provides a dual-channel asymmetric trench-type silicon carbide MOS device, which forms a multi-layer separation gate inside the trench, and the multi-layer separation gate includes: a gate 1 at the top, a columnar separation gate 2 on the left side of the lower end, and an "L"-shaped separation gate 3 on the right side of the lower end, wherein the "L"-shaped separation gate 3 half-covers the columnar separation gate 2. The separation gate structure introduces a new capacitor, namely, a capacitor 1 of a structure of "L"-shaped separation gate 3-oxide layers on both sides of gate 3-silicon carbide on one side of the oxide layer, and a capacitor 2 of a structure of gate 2-oxide layer-gate 3. When a forward voltage is applied from the drain of the device, the effect produced by the capacitor 1 is: the overall trend of the electric potential in the drift region is that the high electric potential at the drain points to the low electric potential at the source. Since the electric potential of the gate 3 connected to the source is zero, there is a potential difference between the gate 3 and the silicon carbide on the same side, and induced charges are generated at the interface between the oxide layer and the silicon carbide on both sides of the gate 3, forming a lateral electric field, which alleviates the electric field concentration effect at the bottom of the trench. Effects of capacitor 2: Columnar gate 2 can be regarded as an equipotential body, which has the same potential as the sidewall oxide layer in the same area. The "L"-shaped gate 3 has a large contact area with columnar gate 2, that is, a larger capacitor 2 is introduced. Under the same voltage, the larger the capacitance, the more charge will be induced on the plate. Since the potential difference will form the charging and discharging process of the capacitor, more induced charges will be generated at the interface between the oxide layer and silicon carbide on both sides of gate 2. Therefore, the electric field originally concentrated at the bottom of the trench moves to the vicinity of the two ends of the floating electrode, bringing a new electric field peak, further reducing the electric field at the bottom of the trench and improving the gate oxide reliability of the device.

[0066] from Fig. 9 It can be seen from the electric field distribution diagram shown that compared with the single-layer separated gate, the present structure forms three electric field peaks on the sides of the groove, reducing the two high electric field peaks of the single-layer separated gate into three low electric field peaks, effectively improving the gate oxide reliability of the device.

[0067] Finally, it should be noted that the drawings of the embodiments disclosed in the present invention only involve the structures involved in the embodiments disclosed in the present invention, and other structures can refer to the general design; in the absence of conflict, the embodiments disclosed in the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.

[0068] The above are only specific implementation methods disclosed in the present invention, but the protection scope disclosed in the present invention is not limited thereto. The protection scope disclosed in the present invention shall be based on the protection scope of the claims.

Claims

1. A method for preparing a dual-channel asymmetric trench silicon carbide MOS device, characterized in that: include: S1, preparing a SiC substrate and a SiC buffer layer, forming an epitaxial layer on the SiC substrate, and forming a drift layer, a current spreading layer and two symmetrical P + Well region; S2, continuing to grow an epitaxial layer on the surface of the epitaxial layer processed in S1, and performing ion implantation on the surface of the epitaxial layer to form a P-base region, an N-plus region and alternately distributed P-plus regions; S3, etching the surface of the epitaxial layer after being processed in S2, + A trench is formed above the well region, and after etching, the P + The well region is etched to form an L shape; S4, depositing oxide and polysilicon in the trench to form an L-shaped separation gate and a columnar separation gate; S5, continuing to deposit oxide and polysilicon in the trench to form a gate; S6, symmetrically etching a portion of the oxide layer at the center of the upper surface of the P-plus region to form a source trench; S7, generate source and drain.

2. The method for preparing a dual-channel asymmetric trench silicon carbide MOS device according to claim 1, characterized in that: The specific implementation process of S1 includes: Selecting an N-type doped 4H-SiC substrate and an N-type doped 4H-SiC buffer layer, and growing an N-type doped 4H-SiC drift layer on the 4H-SiC substrate by a MOCVD homoepitaxial method; forming a current spreading layer on the upper surface of the drift layer by high energy ion implantation; After cleaning, coating, photolithography and developing the drift layer, high-energy ion implantation is performed symmetrically from the center of the upper surface of the current spreading layer with a spacing of 0.4 um to form two symmetrical P + Well region; The current spreading layer is generated again; The doping element of the 4H-SiC substrate is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 10-12um, width is 2-6um; The doping element of the 4H-SiC buffer layer is nitrogen or phosphorus, and the doping concentration is 1×10 17 ~1×10 20 cm -3 , thickness is 1-5um, width is 2-6um; The doping element of the drift layer is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 6-15um, width is 2-6um; The doping element of the current spreading layer is aluminum, and the doping concentration is 1×10 15 ~1×10 17 cm -3 , thickness is 0.2-4um, width is 2-6um; The P + The doping element of the well region is aluminum or boron, and the doping concentration is 1×10 17 ~1×10 19 cm -3 , each P + The thickness of the well region is 0.1-1um and the width is 0.2-1um; The doping element for the current spreading layer is aluminum, with a doping concentration of 1×10 15 ~1×10 17 cm -3 , thickness is 0.2-4um, width is 2-6um.

3. The method for preparing a dual-channel asymmetric trench silicon carbide MOS device according to claim 2, characterized in that: The specific implementation process of S2 includes: Continue to grow an epitaxial layer on the surface of the epitaxial layer treated with S1 by depositing SiC; Forming a P-base region above the current spreading layer by implanting P-type ions on the surface of the epitaxial layer and annealing; Forming an N-plus region of equal width above the P-base region by N-type ion implantation on the surface of the epitaxial layer; On the surface of the N-plus region, P + The well region is centrally symmetrical, and high-energy ion implantation is performed symmetrically with a spacing of 1.6 μm to form a P-plus region with a spacing distribution, and the thickness of the P-plus region is greater than the thickness of the N-plus region; The doping element of the epitaxial layer that continues to grow is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 0.6-2um, width is 2-6um; The P-base region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1 × 10 17 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 1-4um; The N-plus region is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1 × 10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 1-4um; The P-plus region is P-type doped, and the doping element is aluminum or boron. The doping concentration of each P-plus region is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-1um, width is 0.4-2um.

4. The method for preparing a dual-channel asymmetric trench silicon carbide MOS device according to claim 3, characterized in that: The specific implementation process of S3 includes: The epitaxial layer treated by S2 is cleaned, coated, photolithographically processed and developed, the P-plus area and the N-plus area which do not need to be etched are protected by photoresist, and the epitaxial layer is etched to form a groove; The trench etching depth does not exceed P + well region, the trench is located in the P + well region, wider than the P + The well area is small; the left side of the groove is connected to the P + The left side of the well region is aligned so that P + The well region is etched to form an L shape; The groove width is 0.5-2um, and the thickness is 2-3um.

5. The method for preparing a dual-channel asymmetric trench silicon carbide MOS device according to claim 4, characterized in that: The specific implementation process of S4 includes: The epitaxial layer treated by S3 is cleaned, coated, photolithographically processed and developed, and oxide is deposited on the groove; wherein the thickness of the oxide deposited at the bottom of the groove is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall of the groove is 0.05um-0.2um; Polysilicon is deposited in the trench after oxide deposition, with a deposition thickness of 0.5um-3um and a width of 0.3um-2um; Etch the polysilicon on the left side of the trench to a thickness of 0.5um-1.4um and a width of 0.1um-0.5um, so that the remaining polysilicon area is L-shaped, forming an L-shaped separation gate; After etching, an oxide layer is deposited on the bottom and sidewalls of the trench. The thickness of the oxide layer deposited on the bottom is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall is 0.05um-0.2um. Polysilicon is deposited in the trench after oxide deposition to form a columnar separation gate, with a deposition thickness of 0.5um-1um and a width of 0.2um-1um.

6. The method for preparing a dual-channel asymmetric trench silicon carbide MOS device according to claim 5, characterized in that: The specific implementation process of S5 includes: Continue to deposit oxide on the trench after S4 treatment, the thickness of the oxide layer deposited on the bottom is 0.05um-0.2um, and the thickness of the oxide layer deposited on the sidewall of the trench is 0.05-0.2um; Continue to deposit polysilicon in the trench to form a gate, the deposition thickness is 0.6um-2um, and after deposition, the upper surface of the gate is flush with the upper surfaces of the N plus region and the P plus region; Oxide deposition is performed above the gate, so that the deposited oxide layer is flush with the upper surface of the epitaxial layer.

7. The method for preparing a dual-channel asymmetric trench silicon carbide MOS device according to claim 6, characterized in that: The specific implementation process of S6 includes: At the center of the upper surface of the P-plus region, part of the oxide layer is symmetrically etched to a thickness of 0.2um-1um and a width of 0.1um-1um to form a source trench.

8. The method for preparing a dual-channel asymmetric trench silicon carbide MOS device according to claim 7, characterized in that: The specific implementation process of S7 includes: Deposit a metal layer on the top of the epitaxial layer and in the source trench to form a source electrode with a deposition thickness of 2um-4um; A drain is formed by connecting a metal layer to the bottom of the substrate.

9. A dual-channel asymmetric trench silicon carbide MOS device, characterized in that: The device is manufactured by the method for manufacturing a dual-channel asymmetric trench silicon carbide MOS device according to any one of claims 1 to 8.

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