Solar cell and method for manufacturing solar cell

Abstract

The invention provides a solar cell and a preparation method thereof, and the solar cell comprises a silicon substrate which is provided with a first surface, a second surface and a side surface, which are opposite to each other; the tunneling layer and the first doping layer are stacked on the first surface, and the first doping layer comprises doped polycrystalline silicon; the intrinsic amorphous silicon layer and the second doped layer are stacked on the second surface, the intrinsic amorphous silicon layer extends to the first doped layer from the side face, the second doped layer extends to the side face, the doping type of the first doped layer is opposite to that of the second doped layer, and the second doped layer comprises doped microcrystalline silicon; the first transparent conductive layer is arranged on the first doping layer; the second transparent conducting layer is arranged on the second doping layer, and the edge and the side face of the second transparent conducting layer are spaced by a preset distance; and the first electrode and the second electrode are electrically connected with the first transparent conductive layer and the second transparent conductive layer respectively. The intrinsic amorphous silicon layer can passivate the side face of the silicon substrate, and the risk of short circuit is reduced.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a solar cell and a method for preparing the solar cell. Background Art

[0002] Solar cells have made an important contribution to reducing carbon emissions. There are many types of solar cells, among which fully passivated crystalline silicon solar cells have the advantage of high efficiency. However, the contact between some film layers in fully passivated crystalline silicon solar cells can cause short circuits. How to solve the short circuit problem is one of the important research directions in this field. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a solar cell and a method for preparing the solar cell, which can reduce the risk of short circuit of the solar cell.

[0004] To solve the above technical problems, the present application provides a solar cell, comprising: a silicon substrate, having a first surface, a second surface and a side surface connecting the first surface and the second surface; a tunneling layer and a first doping layer, stacked on the first surface, the first doping layer comprising doped polycrystalline silicon; an intrinsic amorphous silicon layer and a second doping layer, stacked on the second surface, and the intrinsic amorphous silicon layer extends from the side surface to the first doping layer, and the second doping layer extends to the side surface, the doping type of the first doping layer is opposite to the doping type of the second doping layer, and the second doping layer comprises doped microcrystalline silicon; a first transparent conductive layer, arranged on the first doping layer; a second transparent conductive layer, arranged on the second doping layer, and an edge of the second transparent conductive layer is spaced a preset distance from the side surface; and a first electrode and a second electrode, electrically connected to the first transparent conductive layer and the second transparent conductive layer, respectively.

[0005] In one embodiment of the present application, the width of the intrinsic amorphous silicon layer located on the first doping layer is 0.1 mm~10 mm, wherein the first transparent conductive layer located on the first doping layer covers the intrinsic amorphous silicon layer located on the first doping layer, and the thickness of the intrinsic amorphous silicon layer located on the first doping layer gradually decreases in a direction away from the side.

[0006] In an embodiment of the present application, the first transparent conductive layer extends to the side surface and covers at least a portion of the intrinsic amorphous silicon layer and the second doped layer located on the side surface.

[0007] In an embodiment of the present application, the tunneling layer includes one or more of silicon oxide, silicon oxynitride, and aluminum oxide, and / or the thickness of the tunneling layer is equal to or less than 3 nm.

[0008] In one embodiment of the present application, the first doping layer includes a doped polysilicon layer, and / or the first doping layer contains one or more of oxygen, carbon, and nitrogen, and / or the thickness of the first doping layer is 20 nm to 600 nm.

[0009] In an embodiment of the present application, the intrinsic amorphous silicon layer contains one or more of oxygen, carbon, and nitrogen, and / or the thickness of the intrinsic amorphous silicon layer is 3 nm to 15 nm.

[0010] In one embodiment of the present application, the second doping layer includes doped amorphous silicon and / or doped microcrystalline silicon, and / or the second doping layer contains one or more of oxygen, carbon, and nitrogen, and / or the thickness of the second doping layer is 3nm~60nm.

[0011] The present application also proposes a method for preparing a solar cell, comprising: providing a silicon substrate, the silicon substrate having a first surface, a second surface and a side surface connecting the first surface and the second surface; forming a tunneling layer and a first doping layer in sequence on the first surface, the first doping layer comprising doped polycrystalline silicon; forming a continuous intrinsic amorphous silicon layer on the second surface, the side surface and the first doping layer; forming a second doping layer on the intrinsic amorphous silicon layer, the doping type of the first doping layer is opposite to the doping type of the second doping layer, the second doping layer comprising doped microcrystalline silicon; forming a first transparent conductive layer on the first doping layer; forming a second transparent conductive layer on the second doping layer, the edge of the second transparent conductive layer being spaced a preset distance from the side surface; and forming a first electrode and a second electrode electrically connected to the first transparent conductive layer and the second transparent conductive layer, respectively.

[0012] In one embodiment of the present application, the width of the intrinsic amorphous silicon layer located on the first doping layer is 0.1 mm~10 mm, wherein the first transparent conductive layer located on the first doping layer covers the intrinsic amorphous silicon layer located on the first doping layer, and the thickness of the intrinsic amorphous silicon layer located on the first doping layer gradually decreases in a direction away from the side.

[0013] In an embodiment of the present application, the first transparent conductive layer is also formed on the side surface, and covers at least a portion of the intrinsic amorphous silicon layer and the second doped layer located on the side surface.

[0014] In one embodiment of the present application, a method for forming an intrinsic amorphous silicon layer includes: after forming the first doped layer, placing a solar cell intermediate on a first carrier, the first carrier having a first base plate and an annular first support portion arranged on the first base plate, the first support portion contacting the first doped layer, the first support portion isolating the front side of the first doped layer surrounded by it from the outside, and forming the intrinsic amorphous silicon layer using a PECVD process.

[0015] In one embodiment of the present application, the first carrier plate further has a plurality of first limiting blocks distributed around the first supporting portion, and the first limiting blocks do not contact the solar cell intermediate body.

[0016] In one embodiment of the present application, a method for forming an intrinsic amorphous silicon layer includes: after forming the first doping layer, placing a solar cell intermediate on a second carrier, the second carrier having a second base plate and a plurality of second support portions spaced apart on the second base plate, and forming the intrinsic amorphous silicon layer using a PECVD process.

[0017] Compared with the prior art, this application has the following advantages: (1) In addition to the second surface of the silicon substrate, the present application also forms an intrinsic amorphous silicon layer on the side surface and part of the first surface of the silicon substrate, so that the intrinsic amorphous silicon layer can passivate the side surface and part of the first surface of the silicon substrate.

[0018] (2) Due to the potential difference, the carriers near the tail will flow toward the first electrode instead of flowing along the first transparent conductive layer located on the side toward the second doped layer. Therefore, the intrinsic amorphous silicon layer of the present application can reduce the risk of short circuit in the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings: Figures 1 to 4 is a schematic cross-sectional view of a solar cell in different embodiments of the present application; Figure 5 is a schematic flow chart of a method for preparing a solar cell in one embodiment of the present application; Figures 6 to 11 is a schematic cross-sectional view of a solar cell at different stages in a method for preparing a solar cell in an embodiment of the present application; Figures 12 to 16 is a schematic diagram of using a first carrier to prepare an intrinsic amorphous silicon layer in one embodiment of the present application; Figures 17 to 21 is a schematic diagram of using a second carrier to prepare an intrinsic amorphous silicon layer in one embodiment of the present application; Figure 22 to Figure 27 Schematic cross-sectional view of solar cells in different embodiments of the present application.

[0020] Reference numerals Silicon substrate 110, first surface 111, second surface 112, side surface 113, tunneling layer 120, first doped layer 130, front surface 131, intrinsic amorphous silicon layer 140, tail 141, second doped layer 150, first transparent conductive layer 160, second transparent conductive layer 170, first electrode 180, second electrode 190, third doped layer 210, first carrier 220, first bottom plate 221, first support portion 222, stopper 223, first venting hole 224, solar cell intermediate 230, second carrier 240, second bottom plate 241, second support portion 242, second stopper 243, second venting hole 244, initial tunneling layer 120-1, initial first doped layer 130-1 and initial third doped layer 210-1. DETAILED DESCRIPTION

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0022] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0023] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0024] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or component referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0025] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0026] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0027] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0028] Next, the solar cell and the method for preparing the solar cell of the present application are described through examples.

[0029] refer to Figure 1 As shown, Figure 1 In the embodiment, the solar cell includes a silicon substrate 110 , a tunneling layer 120 , a first doping layer 130 , an intrinsic amorphous silicon layer 140 , a second doping layer 150 , a first transparent conductive layer 160 , a second transparent conductive layer 170 , a first electrode 180 , a second electrode 190 and a third doping layer 210 .

[0030] Specifically, the silicon substrate 110 has a first surface 111, a second surface 112, and a side surface 113 connecting the first surface 111 and the second surface 112, which are opposite to each other in the thickness direction thereof. The silicon substrate 110 may be N-type or P-type doped single crystal silicon, and the thickness of the silicon substrate 110 may be any value within the range of 60 μm to 250 μm, for example, 60 μm, 100 μm, 140 μm, 160 μm, 200 μm, 240 μm, or 250 μm.

[0031] The third doping layer 210, the tunneling layer 120, and the first doping layer 130 are stacked on the first surface 111, and the third doping layer 210 covers the first surface 111. In some embodiments, the solar cell may not have the third doping layer 210 (eg, Figure 2 As shown), in this case, the tunneling layer 120 and the first doping layer 130 are directly stacked on the first surface 111, and the tunneling layer 120 is in contact with the first surface 111.

[0032] The doping type of the third doping layer 210 is the same as the doping type of the first doping layer 130, and the doping concentration is less than or equal to the doping concentration of the first doping layer 130. The third doping layer 210 can be N-type or P-type doped single crystal silicon. The thickness of the third doping layer 210 can be any value in the range of 10nm to 1500nm, for example, the thickness is 10nm, 200nm, 400nm, 600nm, 800nm, 1000nm, 1200nm, 1400nm or 1500nm.

[0033] In one embodiment, the tunneling layer 120 includes one or more of silicon oxide, silicon oxynitride, and aluminum oxide. The thickness of the tunneling layer 120 may be equal to or less than 3 nm, for example, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm.

[0034] The first doped layer 130 includes a doped polysilicon layer, and the first doped layer 130 may include N-type or P-type doped polysilicon. The first doped layer 130 may also contain one or more of oxygen, carbon, and nitrogen. The thickness of the first doped layer 130 may be 20nm to 600nm, for example, 20nm, 120nm, 220nm, 320nm, 420nm, 520nm, or 600nm.

[0035] The intrinsic amorphous silicon layer 140 and the second doped layer 150 are stacked on the second surface 112, and the intrinsic amorphous silicon layer 140 and the second doped layer 150 extend from the second surface 112 to the side surface 113, and the second doped layer 150 may include doped microcrystalline silicon. Specifically, the intrinsic amorphous silicon layer 140 is formed on the second surface 112, the side surface 113 of the silicon substrate 110, the side surface of the third doped layer 210, the side surface of the tunneling layer 120, and the side surface of the first doped layer 130. The second doped layer 150 is formed on the intrinsic amorphous silicon layer 140 located on the second surface 112 and the intrinsic amorphous silicon layer 140 located on the side surface 113. Figure 1 In the embodiment, the second doping layer 150 covers a portion of the intrinsic amorphous silicon layer 140 located on the side 113, and the thickness of the second doping layer 150 located on the side 113 gradually decreases. The intrinsic amorphous silicon layer 140 may contain one or more of oxygen, carbon, and nitrogen, and / or the thickness of the intrinsic amorphous silicon layer 140 is 3nm~15nm, for example, the thickness is 3nm, 5nm, 7nm, 9nm, 11nm, 13nm or 15nm. The second doping layer 150 may include doped amorphous silicon, and / or the second doping layer 150 may contain one or more of oxygen, carbon, and nitrogen, and / or the thickness of the second doping layer 150 may be 3nm~60nm, for example, the thickness is 3nm, 13nm, 23nm, 33nm, 43nm, 53nm or 60nm.

[0036] The doping type of the first doping layer 130 is opposite to the doping type of the second doping layer 150 . In one embodiment, the silicon substrate 110 is N-type doped, the first doping layer 130 is N-type doped, and the second doping layer 150 is P-type doped.

[0037] According to the above description, those skilled in the art can know that the solar cell in the above embodiment is a hybrid solar cell, that is, it includes both a tunnel passivation structure and a heterojunction passivation structure.

[0038] Continue to refer Figure 1 As shown, the first transparent conductive layer 160 is disposed on the first doping layer 130. The first transparent conductive layer 160 may include one or more of ZnO, InO, and SnO. The first transparent conductive layer 160 may include one or more of Ga, Sn, Mo, Ce, F, W, and Al. The thickness of the first transparent conductive layer 160 may be any value within the range of 10nm to 200nm, for example, the thickness is 10nm, 60nm, 110nm, 160nm, or 200nm.

[0039] The second transparent conductive layer 170 is disposed on the second doping layer 150, and a preset distance D1 is spaced between the edge of the second transparent conductive layer 170 and the side surface 113 in the horizontal direction. The preset distance D1 can be any value in the range of 500 μm to 2000 μm, for example, 500 μm, 1000 μm, 1500 μm or 2000 μm. The preset distance D1 between the edge of the second transparent conductive layer 170 and the side surface 113 can avoid or reduce the short-circuit current between the first electrode 180 and the second electrode 190.

[0040] The second transparent conductive layer 170 may include one or more of ZnO, InO, and SnO. The second transparent conductive layer 170 may include one or more of Ga, Sn, Mo, Ce, F, W, and Al. The thickness of the second transparent conductive layer 170 may be any value within the range of 10 nm to 200 nm, for example, the thickness is 10 nm, 60 nm, 110 nm, 160 nm, or 200 nm.

[0041] The first electrode 180 and the second electrode 190 are electrically connected to the first transparent conductive layer 160 and the second transparent conductive layer 170 , respectively.

[0042] refer to Figure 3 As shown, Figure 3 and Figure 1 A major difference is that Figure 3 The intrinsic amorphous silicon layer 140 in the first surface 111 extends from the side surface 113 to the third doped layer 210. For ease of understanding and description, the intrinsic amorphous silicon layer 140 located on the first surface 111 is marked as a tail portion 141. The width D2 of the tail portion 141 is any value in the range of 0.1 mm to 10 mm, for example, the width D2 is 0.1 mm, 2 mm, 4 mm, 6 mm, 8 mm or 10 mm. The thickness of the tail portion 141 gradually decreases in a direction away from the side surface 113. The first transparent conductive layer located on the third doped layer 210 covers the tail portion 141.

[0043] refer to Figure 4 As shown, Figure 4 and Figure 3 One difference is that Figure 4 The solar cells in the Figure 3 The third doped layer 210, the tunneling layer 120 and the first doped layer 130 are directly stacked on the first surface 111, and the tunneling layer 120 is in contact with the first surface 111. Figure 4 In the embodiment, the intrinsic amorphous silicon layer 140 also extends from the side surface 113 to the third doped layer 210. Figure 3 and Figure 4 In the embodiment, the tail portion 141 is in contact with the surface of the third doped layer 210 facing away from the silicon substrate 110 . Figure 4The width D2 of the tail portion 141 can be any value in the range of 0.1 mm to 10 mm, for example, the width D2 is 0.1 mm, 2 mm, 4 mm, 6 mm, 8 mm or 10 mm, and the thickness of the tail portion 141 gradually decreases in the direction away from the side surface 113.

[0044] exist Figures 1 to 4 In the embodiment, the first transparent conductive layer 160 extends from the first surface 111 to the side surface 113 and covers at least a portion of the intrinsic amorphous silicon layer 140 and the second doping layer 150 located on the side surface 113 .

[0045] On the other hand, the present application also proposes a method for preparing a solar cell, referring to Figure 5 As shown, in Figure 5 In the embodiment of the present invention, the method for preparing a solar cell includes the following steps S110 to S170: Step S110: providing a silicon substrate, wherein the silicon substrate has an opposite first surface, a second surface, and a side surface connecting the first surface and the second surface; Step S120: forming a tunneling layer and a first doping layer in sequence on the first surface, wherein the first doping layer includes doped polysilicon; Step S130: forming a continuous intrinsic amorphous silicon layer on the second surface, the side surface and the first doped layer; Step S140: forming a second doping layer on the intrinsic amorphous silicon layer, wherein the doping type of the first doping layer is opposite to the doping type of the second doping layer, and the second doping layer includes doped microcrystalline silicon; Step S150: forming a first transparent conductive layer on the first doped layer; Step S160: forming a second transparent conductive layer on the second doped layer, wherein an edge and a side surface of the second transparent conductive layer are spaced apart by a preset distance; Step S170: forming a first electrode and a second electrode electrically connected to the first transparent conductive layer and the second transparent conductive layer respectively.

[0046] Next, steps S110 to S170 are described in detail.

[0047] refer to Figure 6 As shown, in step S110 , a silicon substrate 110 is provided. The silicon substrate 110 has an opposite first surface 111 , a second surface 112 , and a side surface 113 connecting the first surface 111 and the second surface 112 .

[0048] refer to Figures 6 to 8 As shown, in step S120, a tunneling layer 120 and a first doping layer 130 are sequentially formed on the first surface 111, and the first doping layer 130 includes doped polysilicon. Figure 7As shown, an initial tunneling layer 120-1 and an initial first doping layer 130-1 may be formed first, the initial tunneling layer 120-1 covering the first surface 111, the side surface 113 and a portion of the second surface 112, and the initial first doping layer 130-1 is formed on the surface of the initial tunneling layer 120-1 away from the silicon substrate 110; then, the initial tunneling layer 120-1 and the initial first doping layer 130-1 located on the side surface 113 and the second surface 112 are removed, and the initial tunneling layer 120-1 and the initial first doping layer 130-1 located on the first surface 111 are retained as the tunneling layer 120 and the first doping layer 130.

[0049] In one embodiment, a third doping layer 210 may be formed between the silicon substrate 110 and the tunneling layer 120. The third doping layer 210 may be formed by diffusing doping elements into the silicon substrate 110 during the process of forming the first doping layer 130. Figure 7 and Figure 8 As shown, an initial third doping layer 210-1 can be formed first, and the initial third doping layer 210-1 covers the first surface 111, the side surface 113 and a portion of the second surface 112; then, the initial third doping layer 210-1 located on the side surface 113 and the second surface 112 is removed, and the initial third doping layer 210-1 located on the first surface 111 is retained as the third doping layer 210.

[0050] refer to Figure 8 and Fig. 9 As shown, the front side 131 of the first doped layer 130 is away from the silicon substrate 110, and in step S130, a continuous intrinsic amorphous silicon layer 140 is formed on the second surface 112, the side surface 113 and a portion of the front side 131. It can be understood that, since the intrinsic amorphous silicon layer 140 continuously extends from the side surface 113 to the front side 131, the intrinsic amorphous silicon layer 140 located on the side surface 113 will cover the side surface of the third doped layer 210, the side surface of the tunneling layer 120 and the side surface of the first doped layer 130.

[0051] refer to Fig. 9 As shown, similar to the above, for ease of understanding and description, the intrinsic amorphous silicon layer 140 located on the front surface 131 is marked as a tail portion 141. In one embodiment, the thickness of the tail portion 141 gradually decreases in a direction away from the side surface 113. In another embodiment, the width D2 of the tail portion 141 is 0.1 mm to 10 mm, for example, the width D2 is 0.1 mm, 2 mm, 4 mm, 6 mm, 8 mm or 10 mm.

[0052] In some embodiments, the intrinsic amorphous silicon layer 140 is not formed on the first doping layer 130 (ie, the tail portion 141 is not formed). Instead, the intrinsic amorphous silicon layer 140 is formed on the second surface 112 and the side surface 113 .

[0053] refer to Fig. 9 and Fig.10 As shown, in step S140, a second doping layer 150 is formed on the intrinsic amorphous silicon layer located on the second surface 112 and the intrinsic amorphous silicon layer located on the side 113, and the second doping layer 150 can continuously extend from the second surface 112 to the side 113. The doping type of the first doping layer 130 is opposite to the doping type of the second doping layer 150, and the second doping layer 150 includes doped microcrystalline silicon.

[0054] refer to Fig.10 and Fig.11 As shown, in step S150 , a first transparent conductive layer 160 is formed on the first surface 111 and the side surface 113 , and the first transparent conductive layer 160 covers the intrinsic amorphous silicon layer 140 and the second doped layer 150 on the side surface 113 . The first transparent conductive layer 160 also covers the first doped layer 130 and the tail portion 141 .

[0055] In some embodiments, the first transparent conductive layer 160 may not be formed on the side surface 113 .

[0056] refer to Fig.10 and Fig.11 As shown, in step S160, a second transparent conductive layer 170 is formed on the second doping layer 150 (i.e., the second transparent conductive layer 170 is formed on the surface of the second doping layer 150 away from the silicon substrate 110), and the edge of the second transparent conductive layer 170 is spaced from the side surface 113 by a preset distance D1 in the horizontal direction. The preset distance D1 can be any value in the range of 500μm to 2000μm, for example, 500μm, 1000μm, 1500μm or 2000μm.

[0057] refer to Fig.11 and Figure 1 As shown, in step S170 , a first electrode 180 and a second electrode 190 electrically connected to the first transparent conductive layer 160 and the second transparent conductive layer 170 , respectively, are formed.

[0058] refer to Figures 12 to 16 As shown, Fig.16 yes Fig.15 In one embodiment, the intrinsic amorphous silicon layer 140 is prepared by means of the first carrier 220. Fig.12 The first carrier 220 is shown in a top view, a cross-sectional view along line AA, and a cross-sectional view along line BB. The first carrier 220 has a first bottom plate 221, an annular first support portion 222, and a first stopper 223. The first support portion 222 is disposed on the first bottom plate 221 and is a closed ring. Fig.12In the figure, the first support portion 222 is a rectangular ring, and the first support portion 222 of the present application is not limited to a rectangular ring. After the first doping layer is formed, the solar cell intermediate 230 is placed on the first carrier, with the first doping layer facing the first base plate 221, and the first support portion 222 in contact with the first doping layer to support the solar cell intermediate 230. The first support portion 222 is a closed ring, and the first support portion 222 isolates the front side 131 of the first doping layer it surrounds from the outside. In other words, there is a space between the first base plate 221 and the solar cell intermediate 230, and the space can be divided into a first space S1 and a second space S2 with the first support portion 222 as the boundary. The first base plate 221, the first support portion 222 and the solar cell intermediate 230 jointly define the first space S1 (such as Fig.12 As shown, from the perspective of the figure, the first space S1 is surrounded by the first support portion 222). It can be understood that the solar cell intermediate 230 refers to a solar cell that has formed a first doping layer but has not yet formed an intrinsic amorphous silicon layer during the production process.

[0059] In the process of forming the intrinsic amorphous silicon layer 140 using a plasma enhanced chemical deposition process (PECVD), the plasma used to form the intrinsic amorphous silicon layer 140 cannot enter the first space S1 due to the obstruction of the first support portion 222. Fig.16 As shown, the intrinsic amorphous silicon layer 140 cannot be formed on the front side 131 surrounded by the first supporting portion 222 (i.e., the front side of the first doped layer located in the first space S1), and the intrinsic amorphous silicon layer 140 is formed on the second surface 112, the side surface 113 and the front side 131 not surrounded by the first supporting portion 222 (i.e., the front side of the first doped layer located in the second space S2). The intrinsic amorphous silicon layer 140 formed on the first doped layer 130 not surrounded by the first supporting portion 222 is the tail portion 141.

[0060] refer to Fig.13 As shown, the first limit block 223 does not contact the side of the solar cell intermediate body 230, and there is a gap between the two. This is because if the first limit block 223 contacts the side of the solar cell intermediate body 230, the first limit block 223 will prevent plasma from forming an intrinsic amorphous silicon layer on the side.

[0061] refer to Fig.12 As shown, a plurality of first stoppers 223 are disposed on the first bottom plate 221, and the plurality of first stoppers 223 are spaced apart around the first support portion 222, and the stoppers 223 do not contact the solar cell intermediate body 230. Fig.13 As shown, the first limiting block 223 has the function of limiting the solar cell intermediate body 230 at a specific position.

[0062] refer to Fig.12As shown, in one embodiment, the first carrier plate 220 has a first vent hole 224, and the first vent hole 224 penetrates the first bottom plate 221. After the solar intermediate is placed in the process chamber, during the vacuuming process, the first vent hole 224 is used to discharge the gas in the second space S2.

[0063] refer to Figures 17 to 21 As shown, Fig.21 yes Fig. 20 In one embodiment, the intrinsic amorphous silicon layer 140 is prepared by means of the second carrier 240. Fig.17 As shown, Fig.17 The top view, the cross-sectional view along the CC line, and the cross-sectional view along the DD line of the second carrier 240 are shown. The second carrier 240 has a second bottom plate 241, a plurality of second support portions 242, and a plurality of second stop blocks 243. The plurality of second support portions 242 are arranged on the second bottom plate 241 in an annular manner, and the plurality of second stop blocks 243 are arranged on the second bottom plate 241 in an annular manner. A major difference between the second carrier 240 and the first carrier 220 is that the second support portion 242 is not a closed ring.

[0064] There is a space between the second bottom plate 241 and the solar cell intermediate body 230. Fig.17 The boundary L in the space can be divided into a third space S3 and a fourth space S4 (such as Fig.17 As shown, from the perspective of the accompanying figure, the third space S3 is surrounded by a boundary L). Fig.17 In the embodiment, the boundary L is a rectangle, and the distances between the four sides of the rectangle and the adjacent boundaries in the second bottom plate 241 may be substantially equal.

[0065] After forming the first doped layer 130, the solar cell intermediate body 230 is placed on the second carrier, and the second support portion 242 contacts the first doped layer 130 and supports the solar cell intermediate body 230. In the process of forming the intrinsic amorphous silicon layer 140 using PECVD, the plasma used to form the intrinsic amorphous silicon layer 140 contacts the first doped layer 130 located in the fourth space S4, but it is difficult to contact the first doped layer 130 located in the third space S3. Therefore, the intrinsic amorphous silicon layer (i.e., the first doped layer 130 located in the fourth space S4) can be formed on the first doped layer 130. Fig.21 However, substantially no intrinsic amorphous silicon layer is formed on the first doped layer 130 located in the fourth space S3.

[0066] refer to Fig.18 As shown, similar to the first carrier plate 220 , the second stopper 243 does not contact the side surface of the solar cell intermediate body 230 , and there is a gap between the two.

[0067] refer to Fig.17 As shown, in one embodiment, the second carrier plate 240 has a second air release hole 244 , and the second air release hole 244 passes through the second bottom plate 241 .

[0068] Apart from Figures 1 to 4 In addition to the solar cell structure shown in FIG. Figure 22 to Figure 27 The solar cell structure shown in the figure is Figure 22 to Figure 27 The solar cell structure in the example is described in detail here. For the unexplained parts, please refer to the previous text. In addition, for easy understanding, Figure 22 to Figure 27 The relevant membrane layers are numbered, and the same membrane layers as before use the same numbers.

[0069] refer to Fig. 22 As shown, the tunneling layer 120 , the first doping layer 130 and the first transparent conductive layer 160 are stacked on a local area of ​​the first surface 111 , and the tail portion 141 is in direct contact with the first surface 111 .

[0070] refer to Fig.23 As shown, Fig.23 The solar cell in the embodiment comprises a third doping layer 210, the third doping layer 210 is located on the first surface 111, the tunneling layer 120, the first doping layer 130 and the first transparent conductive layer 160 are stacked on a local area of ​​the third doping layer 210, Fig.23 The solar cells in Fig.21 The tail 141 in.

[0071] refer to Fig.24 As shown, Fig.23 compared to, Fig.24 The first transparent conductive layer 160 in the structure further covers the area of ​​the third doped layer 210 not covered by the tunneling layer 120 , and extends onto the side surface 113 .

[0072] refer to Fig.25 As shown, Fig.24 compared to, Fig.25 The solar cell has a tail portion 141 , which is located on the third doping layer 210 , and a width of the tail portion 141 is D2 . For the description of D2 , please refer to the above text.

[0073] refer to Fig.26 As shown, Fig.25 compared to, Fig.26 The solar cells in the Fig.25 The third doped layer 210 in the tunnel layer 120 is directly in contact with the first surface 111 , and the first transparent conductive layer 160 is in contact with the first surface 111 not covered by the tunnel layer 120 .

[0074] refer to Fig. 27 As shown, Fig. 22compared to, Fig. 27 The solar cell structure has a third doped layer 210, a tunneling layer 120, a first doped layer 130 and a first transparent conductive layer 160 are stacked on a local area of ​​the third doped layer 210, and the tail 141 is located on the third doped layer 210 and contacts the surface of the third doped layer 210 facing away from the silicon substrate 110.

[0075] For other descriptions about the method for preparing solar cells of the present application, please refer to the relevant parts of the description of solar cells in the previous text, which will not be elaborated here.

[0076] In the foregoing embodiments of the present application, in addition to the second surface of the silicon substrate, an intrinsic amorphous silicon layer is formed on the side and part of the first surface of the silicon substrate, so that the intrinsic amorphous silicon layer can passivate the side and part of the first surface of the silicon substrate. In addition, the resistance of the intrinsic amorphous silicon is relatively high, which causes the carriers near the tail to flow to the first electrode due to the potential difference, rather than flowing along the first transparent conductive layer located on the side to the second doped layer, so the intrinsic amorphous silicon layer of the present application reduces the risk of short circuit.

[0077] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0078] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0079] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0080] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used for the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which can be changed according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the method of general digit retention. Although the numerical domains and parameters used to confirm the breadth of the range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0081] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate having an opposite first surface, a second surface, and a side surface connecting the first surface and the second surface; A tunneling layer and a first doped layer, stacked on the first surface, the first doped layer comprising doped polysilicon; An intrinsic amorphous silicon layer and a second doped layer are stacked on the second surface, and the intrinsic amorphous silicon layer extends from the side to the first doped layer, the second doped layer extends to the side, the doping type of the first doped layer is opposite to the doping type of the second doped layer, and the second doped layer includes doped microcrystalline silicon; A first transparent conductive layer, disposed on the first doped layer; A second transparent conductive layer, disposed on the second doped layer, wherein an edge of the second transparent conductive layer is spaced a preset distance from the side surface; as well as The first electrode and the second electrode are electrically connected to the first transparent conductive layer and the second transparent conductive layer respectively.

2. The solar cell according to claim 1, wherein: The width of the intrinsic amorphous silicon layer located on the first doping layer is 0.1 mm~10 mm, wherein the first transparent conductive layer located on the first doping layer covers the intrinsic amorphous silicon layer located on the first doping layer, and the thickness of the intrinsic amorphous silicon layer located on the first doping layer gradually decreases in a direction away from the side.

3. The solar cell according to claim 2, characterized in that The first transparent conductive layer extends to the side surface and covers at least a portion of the intrinsic amorphous silicon layer and the second doping layer located on the side surface.

4. The solar cell according to claim 1, wherein: The tunneling layer includes one or more of silicon oxide, silicon oxynitride, and aluminum oxide, and / or the thickness of the tunneling layer is equal to or less than 3 nm.

5. The solar cell according to claim 1, wherein: The first doping layer includes a doped polysilicon layer, and / or the first doping layer contains one or more of oxygen, carbon, and nitrogen, and / or the thickness of the first doping layer is 20 nm to 600 nm.

6. The solar cell according to claim 1, wherein: The intrinsic amorphous silicon layer contains one or more of oxygen, carbon, and nitrogen, and / or the thickness of the intrinsic amorphous silicon layer is 3 nm to 15 nm.

7. The solar cell according to claim 1, wherein: The second doping layer includes doped amorphous silicon and / or doped microcrystalline silicon, and / or the second doping layer contains one or more of oxygen, carbon, and nitrogen, and / or the thickness of the second doping layer is 3nm~60nm.

8. A method for preparing a solar cell, characterized in that: include: Providing a silicon substrate, the silicon substrate having an opposite first surface, a second surface, and a side surface connecting the first surface and the second surface; forming a tunneling layer and a first doping layer on the first surface in sequence, wherein the first doping layer comprises doped polysilicon; forming a continuous intrinsic amorphous silicon layer on the second surface, the side surface and the first doped layer; forming a second doping layer on the intrinsic amorphous silicon layer, wherein the doping type of the first doping layer is opposite to the doping type of the second doping layer, and the second doping layer comprises doped microcrystalline silicon; forming a first transparent conductive layer on the first doped layer; forming a second transparent conductive layer on the second doped layer, wherein an edge of the second transparent conductive layer is spaced a preset distance from the side surface; as well as A first electrode and a second electrode are formed which are electrically connected to the first transparent conductive layer and the second transparent conductive layer, respectively.

9. The preparation method according to claim 8, characterized in that: The width of the intrinsic amorphous silicon layer located on the first doping layer is 0.1 mm~10 mm, wherein the first transparent conductive layer located on the first doping layer covers the intrinsic amorphous silicon layer located on the first doping layer, and the thickness of the intrinsic amorphous silicon layer located on the first doping layer gradually decreases in a direction away from the side.

10. The preparation method according to claim 9, characterized in that: The first transparent conductive layer is also formed on the side surface and covers at least a portion of the intrinsic amorphous silicon layer and the second doping layer located on the side surface.

11. The preparation method according to claim 8, characterized in that: The method for forming an intrinsic amorphous silicon layer includes: after forming the first doped layer, placing a solar cell intermediate on a first carrier, the first carrier having a first base plate and a first annular support portion arranged on the first base plate, the first support portion being in contact with the first doped layer, the first support portion isolating the front side of the first doped layer surrounded by it from the outside, and forming the intrinsic amorphous silicon layer using a PECVD process.

12. The preparation method according to claim 11, characterized in that: The first carrier plate further has a plurality of first limiting blocks distributed around the first supporting portion, and the first limiting blocks are not in contact with the solar cell intermediate body.

13. The preparation method according to claim 8, characterized in that: The method for forming an intrinsic amorphous silicon layer includes: after forming the first doping layer, placing a solar cell intermediate on a second carrier, the second carrier having a second base plate and a plurality of second support portions spaced apart on the second base plate, and forming the intrinsic amorphous silicon layer using a PECVD process.

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