High-voltage integrated circuit with under-voltage protection

Abstract

The invention relates to the technical field of high-voltage integrated circuits, and provides an under-voltage protection high-voltage integrated circuit. Comprising an RC filter circuit, a Schmidt circuit, a filter, a level conversion circuit, a temperature protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit, a bootstrap circuit, a dead zone interlocking circuit, a time delay circuit, a pulse circuit, a first high-voltage DMOS, a second high-voltage DMOS, an RS trigger, an output circuit and an AND gate. The under-voltage protection circuit comprises a voltage stabilizing circuit, a power supply voltage detection circuit, a comparator and a first NMOS tube. The input end of the voltage stabilizing circuit serves as the input end of the under-voltage protection circuit to be connected with power supply voltage, and the output end of the voltage stabilizing circuit is connected with the input end of the power supply voltage detection circuit and the negative input end of the comparator. According to the invention, the working stability and reliability of the HIVC in an application occasion with relatively large temperature change are improved, and the market competitiveness of a product is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage integrated circuits, and in particular to a high-voltage integrated circuit with undervoltage protection. Background Art

[0002] With the rapid development of industry, IPM intelligent power modules are widely used in various fields, especially in the field of white household appliances. With the intelligentization, miniaturization, high reliability and full safety functions of household products, it is difficult to adapt to the development needs. The driver IC chip inside the traditional IPM intelligent power module has basic stability and various functional requirements that are more perfect and stable. It must maintain stable working performance under the allowable temperature environment to be suitable for various applications.

[0003] The driver IC chip is a high-voltage integrated circuit, namely HVIC, which is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low-voltage level, high-voltage level, pulse generation circuit, delay circuit, filter circuit, over-current protection circuit, over-heat protection circuit, bootstrap circuit and other circuits. On the one hand, HVIC receives the control signal of MCU to drive the subsequent IGBT or MOS to work, and on the other hand, it sends the system status detection signal back to MCU.

[0004] However, in traditional high-voltage integrated circuits, the undervoltage protection function is single, which makes the driver IC chip have poor stability and reliability, a small application range, and poor product market competitiveness. Summary of the invention

[0005] The present invention provides a high-voltage integrated circuit with undervoltage protection, aiming to solve the problems of poor stability and reliability, small application range and poor product market competitiveness of a driver IC chip of a high-voltage integrated circuit in the prior art.

[0006] The embodiment of the present invention provides a high-voltage integrated circuit for undervoltage protection, comprising: an RC filtering circuit, a plurality of Schmitt circuits, a plurality of filters, a plurality of level conversion circuits, a temperature protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit, a bootstrap circuit, a dead zone interlocking circuit, a delay circuit, a pulse circuit, a first high-voltage DMOS, a second high-voltage DMOS, an RS trigger, an output circuit, and an AND gate;

[0007] The input end of the RC filter circuit is used to connect the HIN drive signal and the LIN drive signal respectively, the output end of the RC filter circuit passes through the multiple Schmitt circuits, the multiple filters, the multiple level conversion circuits and the dead zone interlock circuit in sequence, the output end of the dead zone interlock circuit is respectively connected to the input end of the pulse circuit and the input end of the delay circuit, the output end of the pulse circuit is respectively connected to the gate of the first high-voltage DMOS and the gate of the second high-voltage DMOS, the source of the first high-voltage DMOS is connected to the source of the second high-voltage DMOS and grounded, the drain of the first high-voltage DMOS and the drain of the second high-voltage DMOS are connected and connected to the input end of the RS trigger, and the output end of the RS trigger is connected to the output circuit; the output end of the delay circuit is connected to the input end of the AND gate, and the output end of the AND gate is connected The output circuit; the input end of the undervoltage protection circuit is used to connect the power supply voltage, the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit, and the output end of the fault logic control circuit is respectively connected to the input end of the AND gate and the input end of the pulse circuit; the input end of the undervoltage protection circuit is also connected to the input end of the bootstrap circuit, and the output end of the bootstrap circuit is connected to the drain of the first high-voltage DMOS; the input end of the temperature protection circuit and the input end of the overcurrent protection circuit are respectively connected to the output ends of the multiple level conversion circuits, and the output end of the temperature protection circuit and the output end of the overcurrent protection circuit are respectively connected to the input end of the fault logic control circuit; the input end of the fault output circuit is used to connect the FO port, and the output end of the fault output circuit is connected to the input end of the fault logic control circuit, which is used to output a fault signal;

[0008] The undervoltage protection circuit includes a voltage stabilizing circuit, a power supply voltage detection circuit, a comparator and a first NMOS tube; the input end of the voltage stabilizing circuit is connected to the power supply voltage as the input end of the undervoltage protection circuit, the output end of the voltage stabilizing circuit is respectively connected to the input end of the power supply voltage detection circuit and the negative input end of the comparator, the output end of the power supply voltage detection circuit is respectively connected to the positive input end of the comparator and the drain and source of the first NMOS tube, the gate of the first NMOS tube is connected to the output end of the comparator, and the output end of the comparator serves as the output end of the undervoltage protection circuit.

[0009] Preferably, the voltage stabilizing circuit includes a first MOS tube, a second MOS tube, a first resistor, a second resistor and a voltage stabilizing diode;

[0010] The drain of the first MOS tube is connected to the drain of the second MOS tube, the drain of the first MOS tube serves as the input end of the voltage stabilizing circuit, and the drain of the second MOS tube serves as the first output end of the voltage stabilizing circuit and is connected to the input end of the power supply voltage detection circuit; the gate of the first MOS tube is connected to the gate of the second MOS tube, the source of the first MOS tube is connected to the gate of the first MOS tube, the source of the first MOS tube is also connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the source of the second MOS tube is connected to the negative electrode of the voltage stabilizing diode, the source of the second MOS tube is also connected to the negative input end of the comparator as the second output end of the voltage stabilizing circuit, and the positive electrode of the voltage stabilizing diode is connected to the second end of the second resistor and is grounded.

[0011] Preferably, the power supply voltage detection circuit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor;

[0012] The first end of the third resistor serves as the input end of the power supply voltage detection circuit, the second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor serves as the first output end of the power supply voltage detection circuit and is connected to the positive input end of the comparator; the second end of the fourth resistor is also connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the first end of the sixth resistor, and the second end of the sixth resistor serves as the second output end of the power supply voltage detection circuit and is connected to the drain of the first NMOS tube; the second end of the sixth resistor is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the first end of the eighth resistor, and the second end of the eighth resistor is respectively connected to the source of the first NMOS tube, the positive electrode of the voltage regulator diode and the second end of the second resistor and is grounded.

[0013] Preferably, the voltage regulator diode is a Zener diode.

[0014] Preferably, the fault output circuit is a third MOS tube, the drain of the third MOS tube serves as the input end of the fault output circuit, the source of the third MOS tube is grounded, and the gate of the third MOS tube serves as the output end of the fault output circuit.

[0015] Preferably, the first resistor is an N-Well resistor with a positive temperature coefficient, and the second resistor is a Poly resistor with a negative temperature coefficient and high resistance.

[0016] Compared with the prior art, the beneficial effect of the present invention lies in that, by electrically connecting an RC filtering circuit, multiple Schmitt circuits, multiple filters, multiple level conversion circuits, a temperature protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, a fault logic control circuit, a fault output circuit, a bootstrap circuit, a dead zone interlock circuit, a delay circuit, a pulse circuit, a first high-voltage DMOS, a second high-voltage DMOS, an RS trigger, an output circuit and an AND gate to each other, the input end of the voltage stabilizing circuit is connected to the power supply voltage as the input end of the undervoltage protection circuit, the output end of the voltage stabilizing circuit is respectively connected to the input end of the power supply voltage detection circuit and the negative input end of the comparator, the output end of the power supply voltage detection circuit is respectively connected to the positive input end of the comparator and the drain and source of the first NMOS tube, the gate of the first NMOS tube is connected to the output end of the comparator, and the output end of the comparator serves as the output end of the undervoltage protection circuit. The HVIC with low temperature floating high precision undervoltage protection circuit is realized by using voltage stabilizing circuit, which improves the stability and reliability of the HVIC in applications with large temperature changes, reduces the false protection caused by temperature changes, makes the driver IC suitable for more applications, has higher stability and reliability, and improves the market competitiveness of products. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0018] Figure 1 is a circuit diagram of a high-voltage integrated circuit for undervoltage protection provided by an embodiment of the present invention;

[0019] Figure 2 is a circuit diagram of an undervoltage protection circuit provided by an embodiment of the present invention;

[0020] Figure 3 Schematic diagram of temperature change of the undervoltage protection circuit provided by an embodiment of the present invention.

[0021] In the figure, 0101, a high-voltage integrated circuit for undervoltage protection, 0102, an RC filtering circuit, 0103, multiple Schmitt circuits, 0104, multiple filters, 0105, multiple level conversion circuits, 0111, a temperature protection circuit, 0110, an undervoltage protection circuit, 0112, an overcurrent protection circuit, 0113, a fault logic control circuit, 0114, a fault output circuit, 0109, a bootstrap circuit, 0106, a dead zone interlocking circuit, 0108, a delay circuit, 0107, a pulse circuit, a first high-voltage DMOS, a second high-voltage DMOS, 0115, an RS trigger, 0116, an output circuit, 0117, an AND gate, 10, a voltage stabilization circuit, and 20, a power supply voltage detection circuit. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] Combined with Figure 1-Figure 3 As shown, an embodiment of the present invention provides a high-voltage integrated circuit 0101 for undervoltage protection, including: an RC filtering circuit 0102, multiple Schmitt circuits 0103, multiple filters 0104, multiple level conversion circuits 0105, a temperature protection circuit 0111, an undervoltage protection circuit 0110, an overcurrent protection circuit 0112, a fault logic control circuit 0113, a fault output circuit 0114, a bootstrap circuit 0109, a dead zone interlocking circuit 0106, a delay circuit 0108, a pulse circuit 0107, a first high-voltage DMOS Q1, a second high-voltage DMOS Q2, an RS trigger 0115, an output circuit 0116 and an AND gate 0117.

[0024] The input end of the RC filter circuit 0102 is used to connect the HIN drive signal and the LIN drive signal respectively. The output end of the RC filter circuit 0102 passes through the multiple Schmitt circuits 0103, the multiple filters 0104, the multiple level conversion circuits 0105 and the dead zone interlocking circuit 0106 in sequence. The output end of the dead zone interlocking circuit 0106 is respectively connected to the input end of the pulse circuit 0107 and the input end of the delay circuit 0108. The output end of the pulse circuit 0107 is respectively connected to the gate of the first high-voltage DMOS Q1 and the gate of the second high-voltage DMOS Q2. The source of the first high-voltage DMOS Q1 is connected to the source of the second high-voltage DMOS Q2 and is grounded. The drain of the first high-voltage DMOS Q1 and the drain of the second high-voltage DMOS Q2 are connected to the drain of the first high-voltage DMOS Q1. The drain of Q2 is connected to the input of the RS trigger 0115, and the output of the RS trigger 0115 is connected to the output circuit 0116; the output of the delay circuit 0108 is connected to the input of the AND gate 0117, and the output of the AND gate 0117 is connected to the output circuit; the input of the undervoltage protection circuit 0110 is used to connect the power supply voltage VCC, the output of the undervoltage protection circuit 0110 is connected to the input of the fault logic control circuit 0113, and the output of the fault logic control circuit 0113 is respectively connected to the input of the AND gate 0117 and the input of the pulse circuit 0107; the input of the undervoltage protection circuit 0110 is also connected to the input of the bootstrap circuit 0109, and the output of the bootstrap circuit 0109 is connected to the first high-voltage DMOS The drain of Q1; the input end of the temperature protection circuit 0111 and the input end of the overcurrent protection circuit 0112 are respectively connected to the output ends of the multiple level conversion circuits 0105, and the output end of the temperature protection circuit 0111 and the output end of the overcurrent protection circuit 0112 are respectively connected to the input end of the fault logic control circuit 0113; the input end of the fault output circuit 0114 is used to connect to the FO port, and the output end of the fault output circuit 0114 is connected to the input end of the fault logic control circuit 0113 for outputting a fault signal.

[0025] Among them, the driving signal is input through the HIN port and the LIN port, and after passing through the RC filter circuit 0102, the Schmitt circuit, the filter, the level conversion circuit and the dead zone interlock circuit 0106, the HINa pulse signal is output, and the pulse circuit 0107 outputs the G1 and G2 short pulse signals respectively through the rising edge and the falling edge of the HINa pulse signal to drive the first high-voltage DMOS Q1 and the second high-voltage DMOS Q2. The high-voltage DMOS is turned on and off to trigger the RS trigger 0115 to output the pulse signal, and control HO to output the driving pulse signal; the output LINa pulse signal passes through the delay circuit 0108 and the AND gate 0117 to control LO to output the driving pulse signal. The output of the driving signals HO and LO is protected by the undervoltage protection circuit 0110, the temperature protection circuit 0111, the overcurrent protection circuit 0112 and the fault logic circuit. The bootstrap circuit 0109 provides the bootstrap voltage to the HO, and the fault output circuit 0114 is used to output the fault signal according to the fault feedback of the fault logic control circuit 0113.

[0026] The undervoltage protection circuit 0110 includes a voltage stabilizing circuit 10, a power supply voltage detection circuit 20, a comparator A1, and a first NMOS tube NM1; the input end of the voltage stabilizing circuit 10 is connected to the power supply voltage VCC as the input end of the undervoltage protection circuit 0110, the output end of the voltage stabilizing circuit 10 is respectively connected to the input end of the power supply voltage detection circuit 20 and the negative input end of the comparator A1, the output end of the power supply voltage detection circuit 20 is respectively connected to the positive input end of the comparator A1 and the drain and source of the first NMOS tube NM1, the gate of the first NMOS tube NM1 is connected to the output end of the comparator A1, and the output end of the comparator A1 is used as the output end of the undervoltage protection circuit 0110. The HVIC of the low-temperature floating high-precision undervoltage protection circuit 0110 is realized by using the voltage stabilizing circuit 10, the stability and reliability of the HVIC in applications with relatively large temperature changes are improved, and a false protection caused by temperature changes is reduced, so that the driver IC is suitable for more applications, has higher stability and reliability, and improves the market competitiveness of the product.

[0027] In this embodiment, the voltage stabilizing circuit 10 includes a first MOS transistor PM1, a second MOS transistor PM2, a first resistor R1, a second resistor R2 and a voltage stabilizing diode.

[0028] The drain of the first MOS transistor PM1 is connected to the drain of the second MOS transistor PM2, the drain of the first MOS transistor PM1 serves as the input end of the voltage stabilizing circuit 10, and the drain of the second MOS transistor PM2 serves as the first output end of the voltage stabilizing circuit 10 and is connected to the input end of the power supply voltage detection circuit 20; the gate of the first MOS transistor PM1 is connected to the gate of the second MOS transistor PM2, the source of the first MOS transistor PM1 is connected to the gate of the first MOS transistor PM1, the source of the first MOS transistor PM1 is also connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, the source of the second MOS transistor PM2 is connected to the negative electrode of the voltage stabilizing diode, the source of the second MOS transistor PM2 is also connected to the negative input end of the comparator A1 as the second output end of the voltage stabilizing circuit 10, and the positive electrode of the voltage stabilizing diode is connected to the second end of the second resistor R2 and is grounded.

[0029] In this embodiment, the power supply voltage detection circuit 20 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8;

[0030] The first end of the third resistor R3 serves as the input end of the power supply voltage detection circuit 20, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 serves as the first output end of the power supply voltage detection circuit 20 and is connected to the positive input end of the comparator A1; the second end of the fourth resistor R4 is also connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 serves as the second output end of the power supply voltage detection circuit 20 and is connected to the drain of the first NMOS tube NM1; the second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8, and the second end of the eighth resistor R8 is respectively connected to the source of the first NMOS tube NM1, the positive electrode of the voltage regulator diode and the second end of the second resistor R2 and is grounded.

[0031] In this embodiment, the voltage regulator diode is a Zener diode.

[0032] In this embodiment, the fault output circuit 0114 is a third MOS transistor, the drain of the third MOS transistor serves as the input end of the fault output circuit 0114, the source of the third MOS transistor is grounded, and the gate of the third MOS transistor serves as the output end of the fault output circuit 0114.

[0033] In this embodiment, the first resistor R1 is an N-Well resistor with a positive temperature coefficient, and the second resistor R2 is a Poly resistor with a negative temperature coefficient and high resistance.

[0034] In this embodiment, the working principle of the undervoltage protection circuit 0110 is as follows:

[0035] To achieve high precision and low temperature drift performance, the undervoltage protection circuit 0110 needs to meet the following requirements:

[0036] 1. The first MOS transistor PM1, the second MOS transistor PM2, the first resistor R1, the second resistor R2, and the voltage stabilizing diode DZ1 form a voltage stabilizing branch to obtain a Vref undervoltage threshold value, which is not affected by changes in the power supply VCC and the HVIC temperature.

[0037] 2. The power supply voltage detection circuit composed of six voltage-dividing resistors, namely, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8, has a detection voltage which remains unchanged but changes with the change of the HVIC temperature.

[0038] The working principle of the voltage stabilizing circuit 10 is as follows:

[0039] The undervoltage threshold Vref is obtained from the voltage-stabilizing characteristics of the voltage-stabilizing diode DZ1. The most common use of the voltage-stabilizing diode DZ1 is as a voltage reference source to provide a stable reference voltage to the circuit, but it will be more or less affected by temperature. When the breakdown voltage is greater than 6V, the breakdown mechanism is avalanche breakdown, and the temperature coefficient is positive (the breakdown voltage decreases with increasing temperature); when the breakdown voltage is less than 4V, the breakdown mechanism is Zener breakdown, and the temperature coefficient is negative (the breakdown voltage decreases with increasing temperature). When the breakdown voltage is between 4 and 6V, both breakdown mechanisms will take effect, and the effects of temperature on the two breakdown mechanisms will offset each other, but it is necessary to ensure that the current flowing through the voltage-stabilizing diode DZ1 remains unchanged at this time. This makes the Zener diode have a "zero temperature coefficient". The undervoltage threshold Vref of the present invention is selected to be 5V, and the Zener diode will have better temperature stability at this time. The current Iout flowing through the Zener diode DZ1, in order to confirm that Iout will not change with changes in the power supply VCC and temperature changes, the present invention adopts the following Figure 2 The current mirror principle ensures that Iout is not affected by power supply VCC and temperature.

[0040] The principle of the current mirror composed of the first MOS transistor PM1, the second MOS transistor PM2, the first resistor R1, and the second resistor R2. The working principle of the CMOS current mirror mainly utilizes the characteristic that the base voltages of the two transistors are equal. In the current mirror circuit, the mirror part is composed of two transistors, the first MOS transistor PM1 and the second MOS transistor PM2, the base of one transistor is connected to the input end (signal source), and the base of the other transistor is connected to the output end (load). The current mirror can ensure that the static current between the input and the output is equal, and when the output current changes, the current in the two transistors changes proportionally. When the input signal enters the circuit, the current of the two transistors will change proportionally, thus showing an amplification effect.

[0041] 1. Unsaturated region (Triode Region, also known as "linear region", "triode region", "variable resistance region");

[0042] Among them, the DC current and voltage equation of the Sazhitang equation MOSFET in the non-saturation region is as follows:

[0043] I D =β[(V GS -V TH )V DS -V 2 DS / 2];

[0044] Among them, β is called the gain factor of MOSFET:

[0045] β=μ n CoxW / L (for NMOS);

[0046] β=μ n CoxW / L (for NMOS);

[0047] Wherein, W is the channel width, L is the effective channel length, Cox is the gate oxide capacitance Cox = εox / Tox, εox is the gate oxide dielectric constant, and Tox is the gate oxide thickness.

[0048] If V DS ≤V GS -V TH , the device is considered to work in the "triode region" (TriodeRegion);

[0049] If V DS ≤2(V GS -V TH ), that is, when the MOSFET operates in the non-saturation region and V DS When it is very small (i.e., the "deep triode region"), there is I D =β(V GS -VTH )V DS =μ n CoxW / L-(V GS -V TH )V DS ;

[0050] That is, when V DS Especially when the drain current I D Yes V DS A linear function of .

[0051] The above-mentioned Sazhitang equation shows that I D Yes V DS The quadratic function, that is, I D -V DS The characteristic curve (i.e., the output characteristic curve of MOSFET) is a parabola that opens downward, and the vertex of the parabola is I D The extreme point of corresponds to the channel being pinched off at the drain end.

[0052] Let dI D |dV DS =0, the saturated drain-source voltage V Dsat =V Dsat =V GS -V TH ;

[0053] Saturation drain-source voltage V Dsat Also called "over-drive voltage" (Vov). Dsat =V GS -V TH Substituting back into the Saxodon equation, we get the saturated drain current I Dsat for:

[0054] I Dsat =β(V GS -V TH )2 / 2=μ n Cox(V GS -V TH )2W / 2L;

[0055] When V DS ≤V GS -V TH When the device is considered to be working in the "non-saturation region" (also known as the linear region, triode region, variable resistance region), the MOSFET can be used as a V GS The nonlinear factor comes from V in the Sazhitang equation. 2 DS item.

[0056] 2. Saturation Region (also known as "pinch-off region" and "constant current region");

[0057] Ideally, if V GS unchanged, as V DS The increase of V DS >V GS -V TH After that, the MOSFET is considered to have entered the saturation region. At this time, I D should remain constant with V DS However, due to the effective channel length modulation effect, the effective length of the conductive channel between the drain and the source will increase with V DS As the velocity increases, it gradually shortens, so the Saatchi-Tang equation must be corrected.

[0058] For MOSFET, the parameter used to describe the effective channel length modulation effect is the inverse of the Early voltage, that is, λ = 1 / V A ;

[0059] Then, the modified MOSFET current-voltage equation applied to the saturation region should be:

[0060] I D =μ n Cox(V GS -V TH ) 2 (1+V DS / V A )W / 2L;

[0061] =μ n Cox(V GS -V TH ) 2 (1+λVps)W / L;

[0062] On the boundary between the unsaturated region and the saturated region, there is V DS =V GS -V TH , then I Dsat =μ n Cox(V DS )2W / 2L;

[0063] That is, the boundary between the unsaturated region and the saturated region is a line with V DS The associated parabola.

[0064] According to the above characteristics, it can be considered that I D With V DS Not relevant.

[0065] The first MOS transistor PM1, the second MOS transistor PM2, the first resistor R1, and the second resistor R2 of the present invention form a current mirror circuit:

[0066] Iref=μ n Cox(V GS1 -V TH )2W pm1 / 2L pm1 ;

[0067] Iout=μ n Cox(V GS2 -V TH )2W pm2 / 2L pm2 ;

[0068] And V GS1 =V GS2 , so we have:

[0069] Iout=(W pm2 / L pm2 ) / (W pm1 / L pm1 );

[0070] From the above analysis, Iout has nothing to do with VCC, that is, Iref = V GS1 / (R1+R2);

[0071] As one of the most common passive components, resistors are widely used in a wide range of applications, such as digital-to-analog converters, delay devices, and bias circuits. In semiconductors, integrated resistors are usually correlated with the external temperature within a certain temperature range. The temperature coefficient of resistance is generally used to represent the correlation between the resistance value and temperature. The temperature coefficient of resistance α is TCR It refers to the relative change of resistance value when the temperature changes by 1°C, and the unit is ppm / °C. Usually, the correlation between resistance and temperature can be expressed as:

[0072] R(T)=R0(1+α TCR1 (TT r )+α TCR2 (TT r ) 2 ;

[0073] In the above formula, R0 represents the resistance value at temperature T = Tr, α TCR1 represents the first-order temperature coefficient of resistance, α TCR2 It represents the second-order temperature coefficient of resistance, Tr represents the reference temperature, and both T and Tr represent thermodynamic temperature in K.

[0074] In the integrated circuit process, according to different manufacturing methods, resistors are divided into well resistors, P+ / N+ resistors, Poly resistors and metal resistors, among which P+ / N+ resistors and Poly resistors are divided into silicided resistors and non-silicided resistors, and the performance of different resistors varies greatly. As shown in Table 1, in the 0.35μm~0.7μm standard CMOS process, these different types of resistors have their own unique temperature dependence.

[0075] Table 1 - Temperature characteristics of different resistors in standard CMOS process

[0076] Resistor Type Sheet resistance (Ω / □) αTCR1(*103ppm / ℃) αTCR2(*103ppm / ℃) Poly resistor 25-150 -1.1～+0.9 0～+3 High resistance poly resistor 1000-2000 -2.1～-0.9 0～+5 P+Resistance 70-100 +1.1～+1.9 0～+2 N+ resistor 50-70 +1.4～+1.5 0～+2 N-well resistor 800-1400 +3.5～+5.5 +8～+15

[0077] Among different types of resistors, Poly resistors have positive / negative temperature coefficients, and N-Well resistors have positive temperature coefficients. Among them, Poly resistors are resistors made of Poly layers used as MOS tube gates, and are divided into low-resistance Poly resistors and high-resistance Poly resistors. The temperature coefficient of Poly resistors can be positive or negative, mainly depending on the impurity ions (such as P+ or N+) injected into it, and a larger temperature coefficient can be obtained by reducing the doping concentration of impurity ions such as P+ / N+. For high-resistance Poly resistors, it is precisely because of its lower doping concentration that high-resistance Poly resistors usually have a larger negative temperature coefficient; while N-Well resistors are resistors realized by N-Well in the P substrate process, and usually have a larger square resistance value. It is precisely because N-Well resistors generally have a very low P+ doping concentration that they have a larger positive temperature coefficient, and like Poly resistors, a larger positive temperature coefficient can be obtained by reducing the P+ injection concentration. In a certain process, the high-resistance Poly resistor has a negative temperature coefficient of -3050ppm / ℃, and the N-Well resistor has a positive temperature coefficient of 5600ppm / ℃.

[0078] The first MOS transistor PM1, the second MOS transistor PM2, the first resistor R1, and the second resistor R2 of the present invention form a current-limiting resistor of a current mirror. The first resistor R1 adopts an N-Well resistor with a positive temperature coefficient, and the second resistor R2 adopts a high-resistance Poly resistor (polycrystalline silicon) with a negative temperature coefficient. The temperature coefficients of the resistors are reduced by connecting them in series in a certain proportion, thereby performing temperature compensation, so that the current mirror will not change due to changes in the ambient temperature, and low temperature drift performance is achieved. Similarly, the power supply voltage detection circuit composed of six voltage-dividing resistors, namely, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8, uses a positive temperature coefficient N-Well resistor, and the fourth resistor R4, the sixth resistor R6 and the eighth resistor R8 use a negative temperature coefficient high-resistance Poly resistor, so that the third resistor R3 and the fourth resistor R4 are connected in series to form a low-temperature drift resistor, the fifth resistor R5 and the sixth resistor R6 are connected in series to form a low-temperature drift resistor, and the seventh resistor R7 and the eighth resistor R8 are connected in series to form a low-temperature drift resistor, so that the voltage value V1 of the power supply VCC detected will not change due to temperature changes, affecting the accuracy of the undervoltage protection circuit. The low-temperature drift resistor is formed by connecting the positive temperature coefficient N-Well resistor and the negative temperature coefficient high-resistance Poly resistor in series. Figure 3 shown.

[0079] The invention has the following beneficial effects:

[0080] 1. The design of low-temperature floating high-precision undervoltage protection circuit is realized by sampling the combination of positive and negative temperature coefficient resistors. CADENCE's VIRTUOSO is used for layout design and MMSIM is used for DRC and LVS error checking.

[0081] 2. The low-temperature floating high-precision undervoltage protection circuit design is integrated into the HVIC through the combined sampling of positive and negative temperature coefficient resistors, and the circuit function simulation of the complete HVIC circuit and MMSIM are used to perform DRC and LVS error checking.

[0082] 3. The positive and negative temperature coefficient resistor combination sampling realizes low temperature floating high precision undervoltage protection circuit design layout is integrated into the HVIC layout, and the layout circuit connection is connected according to the circuit schematic diagram, which is convenient for integration.

[0083] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0084] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A high voltage integrated circuit with undervoltage protection, characterized in that: include: RC filter circuit, multiple Schmitt circuits, multiple filters, multiple level conversion circuits, temperature protection circuit, undervoltage protection circuit, overcurrent protection circuit, fault logic control circuit, fault output circuit, bootstrap circuit, dead zone interlock circuit, delay circuit, pulse circuit, first high voltage DMOS, second high voltage DMOS, RS trigger, output circuit and AND gate; The input end of the RC filter circuit is used to connect the HIN drive signal and the LIN drive signal respectively, the output end of the RC filter circuit passes through the multiple Schmitt circuits, the multiple filters, the multiple level conversion circuits and the dead zone interlocking circuit in sequence, the output end of the dead zone interlocking circuit is respectively connected to the input end of the pulse circuit and the input end of the delay circuit, the output end of the pulse circuit is respectively connected to the gate of the first high-voltage DMOS and the gate of the second high-voltage DMOS, the source of the first high-voltage DMOS is connected to the source of the second high-voltage DMOS and is grounded, the drain of the first high-voltage DMOS and the drain of the second high-voltage DMOS are connected to the drain of the second high-voltage DMOS. The drain of OS is connected and connected to the input of the RS trigger, and the output of the RS trigger is connected to the output circuit; the output of the delay circuit is connected to the input of the AND gate, and the output of the AND gate is connected to the output circuit; the input of the undervoltage protection circuit is used to connect the power supply voltage, the output of the undervoltage protection circuit is connected to the input of the fault logic control circuit, and the output of the fault logic control circuit is respectively connected to the input of the AND gate and the input of the pulse circuit; the input of the undervoltage protection circuit is also connected to the input of the bootstrap circuit, and the output of the bootstrap circuit is connected to the drain of the first high-voltage DMOS; The input end of the temperature protection circuit and the input end of the overcurrent protection circuit are respectively connected to the output ends of the multiple level conversion circuits, and the output end of the temperature protection circuit and the output end of the overcurrent protection circuit are respectively connected to the input end of the fault logic control circuit; The input end of the fault output circuit is used to connect to the FO port, and the output end of the fault output circuit is connected to the input end of the fault logic control circuit to output a fault signal; The undervoltage protection circuit includes a voltage stabilizing circuit, a power supply voltage detection circuit, a comparator and a first NMOS tube; the input end of the voltage stabilizing circuit is connected to the power supply voltage as the input end of the undervoltage protection circuit, the output end of the voltage stabilizing circuit is respectively connected to the input end of the power supply voltage detection circuit and the negative input end of the comparator, the output end of the power supply voltage detection circuit is respectively connected to the positive input end of the comparator and the drain and source of the first NMOS tube, the gate of the first NMOS tube is connected to the output end of the comparator, and the output end of the comparator serves as the output end of the undervoltage protection circuit.

2. The high voltage integrated circuit with undervoltage protection as claimed in claim 1, characterized in that: The voltage stabilizing circuit comprises a first MOS tube, a second MOS tube, a first resistor, a second resistor and a voltage stabilizing diode; The drain of the first MOS tube is connected to the drain of the second MOS tube, the drain of the first MOS tube serves as the input end of the voltage stabilizing circuit, and the drain of the second MOS tube serves as the first output end of the voltage stabilizing circuit and is connected to the input end of the power supply voltage detection circuit; the gate of the first MOS tube is connected to the gate of the second MOS tube, the source of the first MOS tube is connected to the gate of the first MOS tube, the source of the first MOS tube is also connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the source of the second MOS tube is connected to the negative electrode of the voltage stabilizing diode, the source of the second MOS tube is also connected to the negative input end of the comparator as the second output end of the voltage stabilizing circuit, and the positive electrode of the voltage stabilizing diode is connected to the second end of the second resistor and is grounded.

3. The high voltage integrated circuit with undervoltage protection as claimed in claim 2, characterized in that: The power supply voltage detection circuit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; The first end of the third resistor serves as the input end of the power supply voltage detection circuit, the second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor serves as the first output end of the power supply voltage detection circuit and is connected to the positive input end of the comparator; the second end of the fourth resistor is also connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the first end of the sixth resistor, and the second end of the sixth resistor serves as the second output end of the power supply voltage detection circuit and is connected to the drain of the first NMOS tube; the second end of the sixth resistor is connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the first end of the eighth resistor, and the second end of the eighth resistor is respectively connected to the source of the first NMOS tube, the positive electrode of the voltage regulator diode and the second end of the second resistor and is grounded.

4. The high voltage integrated circuit with undervoltage protection as claimed in claim 2, characterized in that: The voltage regulator diode is a Zener diode.

5. The high voltage integrated circuit with undervoltage protection as claimed in claim 1, characterized in that: The fault output circuit is a third MOS tube, the drain of the third MOS tube serves as the input end of the fault output circuit, the source of the third MOS tube is grounded, and the gate of the third MOS tube serves as the output end of the fault output circuit.

6. The high voltage integrated circuit with undervoltage protection as claimed in claim 1, characterized in that: The first resistor is an N-Well resistor with a positive temperature coefficient, and the second resistor is a Poly resistor with a negative temperature coefficient and high resistance.

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