Driver circuit for resonant converter, related integrated circuit, electronic converter and method

Abstract

The invention relates to a driver circuit for a resonant converter, a related integrated circuit, an electronic converter and a method. A driver circuit for a resonant converter includes an analog zero current comparator configured to generate a first control signal indicative of when a resonant current of the resonant converter changes a sign; a triangular wave generator circuit configured to provide a triangular wave signal at an output; and a comparison circuit configured to generate a second control signal indicating whether the triangular wave signal reaches a reference threshold. The driver circuit is configured to drive high-side and low-side electronic switches via respective drive signals during successive first and second switching half cycles, wherein each of the first and second switching half cycles ends when the comparison circuit indicates that the triangular wave signal has reached the reference threshold.

Description

Technical Field

[0001] Embodiments of the present specification relate to a control device for a switching resonant converter. Background Art

[0002] Resonant converters are a wide range of switching converters characterized by the presence of a resonant circuit that plays an active role in determining the input-output power flow. Considering the most common implementation, in these converters a full bridge (or half bridge) consisting of four (or two) power switches (usually power field effect transistors, FETs, such as metal oxide semiconductor field effect transistors, MOSFETs) is powered by a DC voltage, generating a voltage square wave that is applied to a resonant circuit tuned to a frequency close to the fundamental frequency of the square wave. Therefore, due to its selective characteristics, the resonant circuit responds mainly to the fundamental component and negligibly to the higher-order harmonics of the square wave.

[0003] As a result, the circulating power can be modulated by varying the frequency of the square wave while keeping the duty cycle constant at 50%. In addition, depending on the resonant circuit configuration, the current and / or voltage associated with the power flow has a sinusoidal or segmented sinusoidal shape.

[0004] These voltages are rectified and filtered in order to provide DC power to the load. In offline applications, in order to comply with safety regulations, the rectification and filtering system that supplies the load is usually coupled to the resonant circuit through a transformer that provides isolation between the source and the load, as required by the above regulations. As in all isolated network converters, in this case there is also a distinction between the primary side (associated with the primary winding of the transformer) connected to the input source and the secondary side (associated with the secondary winding of the transformer) that provides power to the load through the rectification and filtering system.

[0005] Currently, among many types of resonant converters, the so-called LLC resonant converter is widely used, especially in its half-bridge version. The name LLC comes from the resonant circuit using two inductors (L) and one capacitor (C).

[0006] Figure 1 An example of an LLC resonant converter 20 is shown. Typically, the electronic converter 20 comprises:

[0007] A positive input terminal 200a and a negative input terminal 200b for receiving a DC input voltage Vin; and

[0008] The positive output terminal 202 a and the negative output terminal 202 b are used to provide a regulated (DC) output voltage Vout or an output current Iout.

[0009] For example, the input voltage Vin can be provided by a DC voltage generator 10 such as a battery. However, the input voltage Vin can also be obtained from an AC voltage, for example, through a rectifier circuit such as a bridge rectifier and an optional filter circuit such as a capacitor. Instead, the regulated output voltage Vout or output current Iout can be used to power a load 30.

[0010] In the example considered, the electronic converter 20 comprises a half-bridge comprising two electronic switches SW1 and SW2, such as FETs, such as n-channel FETs, such as NMOS, connected in series (e.g. directly) between input terminals 200a and 200b, wherein the negative input terminal 200b generally represents the first ground GND1. For example, in the example considered, the drain terminal of the transistor SW1 is directly connected to the terminal 200a, the source terminal of the transistor SW1 is directly connected to the drain terminal of the transistor SW2, and the source terminal of the transistor SW2 is directly connected to the terminal 200b.

[0011] Hence, the half-bridge SW1 , SW2 is powered via the input voltage Vin and the intermediate node between the electronic switches SW1 and SW2 (eg the drain terminal of the transistor SW1 ) represents the switching node HB.

[0012] In the considered example, the control terminals of the electronic switches SW1 and SW2 (eg gate terminals of respective FETs) are driven via a driver circuit 210 which is configured to generate respective drive signals HSGD and LSGD for the electronic switches SW1 and SW2.

[0013] Typically, the driver circuit 210 is configured to generate the drive signals HSGD and LSGD so that the following four phases are repeated for each switching cycle:

[0014] During the first time interval, the first electronic switch SW1 is closed and the second electronic switch SW2 is opened, whereby the switch node HB is connected to the positive input node 200a, i.e., the input voltage Vin;

[0015] During a second time interval, opening the first and second electronic switches SW1 / SW2;

[0016] During a third time interval, the first electronic switch SW1 is opened and the second electronic switch SW2 is closed, whereby the switch node HB is connected to the negative input node 200a, such as the ground GND1; and

[0017] During the fourth time interval, the first and second electronic switches SW1 / SW2 are turned off.

[0018] In the example considered, the switch node HB between the electronic switches SW1 and SW2 is connected to a (resonant) circuit block.

[0019] In particular, in the example considered, the circuit comprises a transformer T comprising a primary winding T1 and a center-tapped secondary winding comprising a first secondary winding T2a and a second secondary winding T2b connected in series.

[0020] In the example considered, the primary winding T1 of the transformer T is connected (e.g. directly) with the capacitor Cr and the first inductor Ls between the switching node HB and the negative terminal 200b. In addition, the second inductor Lp is connected (e.g. directly) in parallel with the primary winding T1. Thus, in the example considering the capacitor Cr, the first inductor Ls and the second inductor Lp are connected in series (hence the name LLC converter), and the inductor Lp is connected in parallel to the primary winding T1. For example, in Figure 1 , a first terminal of capacitor Cr is connected (eg, directly) to switching node HB, a second terminal of capacitor Cr is connected (eg, directly) to a first terminal of primary winding T1 via inductor Ls, and a second terminal of primary winding T1 is connected (eg, directly) to terminal 200b.

[0021] In any case, in the actual transformer T, the two windings T1 and T2 are not fully coupled, and the transformed T also includes leakage inductance and magnetizing inductance. Basically, this leakage inductance can be modeled by an inductor connected in series with the primary winding T1. On the contrary, the magnetizing inductance (used to simulate magnetic flux) of the transformer T can be simulated by an inductor connected in parallel with the primary winding T1. Therefore, the inductance Ls can be included in the leakage inductance of the transformer T, can be implemented by an inductor connected in series with the primary winding T1, or can be generated by both the leakage inductance of the transformer T and such an inductor. Similarly, the inductance Lp can be included in the magnetizing inductance of the transformer T, can be implemented by an inductor connected in parallel with the primary winding T1, or can be generated by both the magnetizing inductance of the transformer T and such an inductor.

[0022] As mentioned above, in Figure 1A center-tap arrangement on the secondary side is used, i.e. the secondary winding comprises first, second and center-tap terminals. Specifically, in the example considered, the center-tap terminal is connected (e.g. directly) to one of the output terminals 202a / 202b, and the first and second terminals of the secondary winding T2 are connected to the other output terminal 202a / 202b via respective diodes D1 and D2 (e.g. directly). For example, in the example considered, the center-tap terminal is connected (e.g. directly) to the output terminal 202b, and the first and second terminals of the secondary winding T2 are connected (e.g. directly) to the anodes of respective diodes D1 and D2, and the cathodes of the diodes D1 and D2 are connected (e.g. directly) to the terminal 202a. Therefore, due to the rectifying function of the diodes D1 and D2, the terminal 202a corresponds to the positive output terminal, while the terminal 202b corresponds to the negative output terminal, which usually corresponds to the second ground GND2. However, by reversing the orientation of the diodes D1 and D2, the terminal 202b will correspond to the positive output terminal.

[0023] In general, other rectifiers (instead of diodes D1 and D2) may also be used between the secondary winding T2 and the output terminals 202a and 202b. For example, the first and second terminals of the secondary winding T2 (and therefore the center tap terminal may not be included) may be connected to the output terminals 202a and 202b via a bridge rectifier.

[0024] Typically, the electronic converter 20 may also include an output filter connected between the rectifier and the output terminals 202a and 202b. Figure 1 , capacitor Cout is connected (eg, directly) between output terminals 202a and 202b.

[0025] Compared to conventional switching converters (non-resonant converters, typically PWM - pulse width modulation - controlled), resonant converters offer considerable advantages, such as waveforms without sharp edges, low switching losses in the power switches due to their "soft" switching, high conversion efficiency (typically >95%), the ability to operate at high frequencies, low EMI (electromagnetic interference) generation and / or high power density (i.e., the ability to build conversion systems capable of handling considerable power levels in a relatively small space).

[0026] Thus, in the example considered, the electronic converter provides a voltage Vout and a current Iout via output terminals 202a and 202b. Typically, a closed loop (typically implemented using a negative feedback control system) maintains the output voltage Vout or output current Iout of the converter constant when changing operating conditions (e.g., changes in the input voltage Vin and / or the output load 30).

[0027] For example, Figure 2An example of a control circuit for regulating the output voltage Vout in a typical half-bridge resonant converter 20 is shown.

[0028] As previously described, the half-bridge resonant converter 20 includes a half-bridge including two electronic switches connected in series between input terminals 200a and 200b of the electronic converter 20. In addition, the converter 20 includes a circuit 204 including a resonant tank (e.g., capacitor Cr, inductors Ls and Lp, and transformer T), a rectifier circuit (e.g., diodes D1 and D2), and an optional filter circuit (e.g., capacitor Cout). Specifically, the circuit 204 is connected to the switching node HB (between the electronic switches SW1 and SW2) and the negative input terminal 200b (or optionally, the positive input terminal 200a) on one side to receive a substantially square wave signal, and to the output terminals 202a and 202b on the other side to provide a regulated output voltage Vout or an output current Iout.

[0029] Specifically, in order to implement closed-loop control, the converter 20 includes a sensor configured to monitor a value indicative of the output voltage Vout (for a voltage source) or the output current Iout (for a current source). Figure 2 In the embodiment considered, the converter 20 is configured to provide a regulated voltage. Therefore, in the embodiment considered, the converter 20 includes a voltage sensor 212 configured to monitor the output voltage Vout. For example, in Figure 2 In the embodiment of the present invention, a voltage divider comprising two resistors R1 and R2 connected between terminals 202a and 202b is used, whereby the voltage sensor provides a measurement signal proportional to the output voltage Vout. In contrast, in the case of a regulated current source, the converter will include a sensor configured to monitor the output current Iout, such as a shunt resistor connected in series with the load 30.

[0030] The measurement signal (representing the current Iout or the voltage Vout) provided by the sensor 212 is provided to an error amplifier, which is configured to generate an error signal Er. For example, the error amplifier can compare the measurement signal with a reference signal (e.g., a reference voltage Vref) and generate an error signal Er indicating the difference between the measurement signal and the reference voltage Vref.

[0031] In the example considered, the error signal Er is then supplied to the driver circuit 210 in order to modify a given controlled quantity x, wherein the energy delivered during each switching cycle substantially depends on the controlled quantity x. Typically, the error signal Er may be supplied directly to the driver circuit 210, or indirectly to the driver circuit 210, for example via an optocoupler 218 (which is typically used in the case of isolated electronic converters). Furthermore, the error signal Er supplied to the driver circuit 210 or a signal representing (e.g., proportional to) the error signal Er (e.g., in the case where an optocoupler 218 is also used) may be any suitable control signal, such as a voltage Vc or a current Ic. Without loss of generality, it will be assumed hereinafter that the quantity x is modified according to the control current Ic. Furthermore, although the current Ic is primarily represented as representing the output voltage Vout of the converter, the current Ic may also represent the output current Iout.

[0032] Typically, the error amplifier is implemented with an operational amplifier 214 that receives at its inputs a measurement signal (e.g., at an inverting / negative input) and a reference signal (e.g., at a non-inverting / positive input). In addition, the operational amplifier 214 is associated with a feedback network 216 connected between an output terminal of the operational amplifier and one of its inputs (typically the inverting input). For example, the feedback network 216 may include components for implementing the error amplifier as a regulator having a proportional (P) component (e.g., via a resistor) and / or an integral (I) component (e.g., via a capacitor). Thus, typically, the feedback network 216 implements a filter for the error amplifier. For example, such a filter 216 may be useful in order to select an appropriate frequency response of the error amplifier, for example, in order to ensure that:

[0033] a stable control loop (i.e., after a disturbance in the operating conditions of the converter, the output parameter Vout / Iout tends to return to a constant steady state once the transients caused by the disturbance have subsided);

[0034] Good regulation (i.e., the new constant value recovered by the output parameter Vout / Iout after the disturbance is very close to the value before the disturbance); and

[0035] Good dynamic performance (i.e., during the transient period following a disturbance, the output parameter Vout / Iout does not deviate too much from the desired value, and the transient itself is short).

[0036] The above control objectives can be expressed in terms of some characteristic quantities of the transfer function of the control loop, such as bandwidth, phase margin, dc gain. For example, in a DC-DC converter, these objectives can be achieved by modifying the feedback network 216 so that:

[0037] Regarding the frequency response of the error amplifier,

[0038] Modify its gain, and

[0039] Conveniently set the poles and zeros of its transfer function (frequency compensation).

[0040] As previously described, this is typically accomplished through the use of a passive feedback network 216 comprising one or more resistors and / or one or more capacitors of appropriate value.

[0041] However, in order to determine the frequency compensation required to obtain the desired characteristics of the transfer function of the control loop, it is helpful to know the modulator gain (i.e. the gain of the system that converts the control current Ic into the control quantity x) and the frequency response of the converter itself to changes in the control quantity x.

[0042] The inventors have observed that the modulator gain is generally independent of the switching frequency (at least within the range of relevant frequencies) and is fixed within the driver circuit 210. Moreover, although DC-DC converters are strongly nonlinear systems (due to the switching action), their frequency response can be described and represented by a transfer function characterized by gain, zeros and poles, under suitable approximations and certain assumptions. This transfer function depends essentially on the converter topology, i.e. the mutual configuration of the elements that process the power, on its operating mode, i.e. whether there is a continuous current circulation (continuous current mode, CCM) (discontinuous current mode, DCM) in the magnetic part during the switching cycle, and on the control quantity x controlled by the control loop.

[0043] For example, in a resonant converter, the control variable x for controlling the converter is often directly the switching frequency of a square wave applied to the resonant circuit (direct frequency control, DFC).

[0044] This simple control method may suffer from a dynamic behavior characterized by a strongly variable DC gain, and a number of poles that varies from 1 to 3 and has a very mobile position depending on the operating point. In addition, the energy transfer depends strongly on the input voltage Vin (e.g. resulting in poor audio sensitivity), so that the control loop has to change the operating frequency significantly to compensate for this change, which is almost unavoidable in a converter operated from the power line (in the range in which the input voltage Vin may vary due to changes in the rectified mains voltage), thus implying the need for a high open-loop gain in the relevant frequency range.

[0045] All these characteristics make it practically impossible to obtain optimized dynamic behavior under all operating conditions and require a considerable compromise between stability, dynamic performance and input ripple rejection.

[0046] The inventors have observed that a possible compensation for these drawbacks consists in using a driver circuit 210 comprising a control module 220 that implements a control technique known as "time-shift control" (TSC). The literature teaches that the dynamics of a TSC-controlled converter are those of a low-Q second-order system, i.e., characterized by a pair of real poles that are well separated (at least 5 times) from each other. In practice, this means that excellent dynamic performance can be achieved with a small compromise relative to other constraints and with significantly less design effort.

[0047] For example, US Pat. No. 8,773,872 B2 discloses two TSC implementations.

[0048] In the first implementation (such as US8,773,872B2 Figure 4 As shown), TSC is implemented in the following way:

[0049] 1. When the voltage applied to the resonant tank and the current flowing through the resonant tank have equal signs, the capacitor is alternately charged and discharged with a constant current between two voltage levels in the time interval of the switching cycle,

[0050] 2. When the resonant voltage and current have opposite signs, the capacitor voltage is kept constant during the time interval of one switching cycle

[0051] 3. When the capacitor voltage touches any of the above voltage levels, the half-bridge is switched and the charge / discharge phase of the capacitor is reversed.

[0052] In the second embodiment (such as US 8,773,872 B2 Figure 6 or Fig. 9 As shown), TSC is implemented in the following ways:

[0053] 1. When the voltage applied to the resonant tank and the current flowing through the resonant tank have equal signs, the capacitor is charged with a constant current until the voltage level reaches 1.

[0054] 2. When the resonant voltage and current have opposite signs, the capacitor voltage is kept constant during the time interval of one switching half cycle

[0055] 3. When the capacitor voltage touches the above voltage level, the half-bridge is switched and the capacitor is reset (usually to zero).

[0056] In both implementations, the constant current used to charge the capacitor (and also discharge it in the first implementation) is proportional to the control current Ic. In addition, in both implementations, the control module 220 also monitors the current Is flowing from the half-bridge SW1 / SW2 into the resonant tank. For example, as previously described, the resonant tank can be connected between the switch node HB and the negative terminal 200b (or the positive terminal 200a). In this case, the current sensor 222 can be connected in series with the resonant tank. For example, the current sensor 222 can be a shunt resistor (e.g., connected between the resonant tank and the terminal 200b, such as between the primary winding T1 of the transformer T and the terminal 200b), which provides a voltage Vs representing the current Is flowing through the resonant tank (e.g., proportional to the current Is flowing through the resonant tank). Specifically, document US8,773,872B2 uses a zero current comparator to detect the sign of the current Is in the resonant tank. For example, in document US Pat. No. 8,773,872 B2, a zero / ground referenced comparator (reference symbol CO1 in document US Pat. No. 8,773,872 B2) is used, which receives a voltage Vs proportional to the instantaneous resonant current (tank circuit).

[0057] The inventors have observed that these implementations tend to make the resonant current Is asymmetric at light (small) loads. In particular, the inventors have observed that this asymmetry can be derived from the input voltage offset of the zero current comparator and / or disturbances in the signal, resulting in a duty cycle of the square wave at node HB that is different from the ideal 50%. This is due to a cumulative effect: in a kind of "positive feedback loop", any disturbance or asymmetry in the zero current moment in the cycle propagates in subsequent cycles maintaining its positive sign. If the equivalent gain of this positive loop exceeds 1, the loop becomes unstable and causes the duty cycle to deviate from the ideal 50%. The worst result is an unequal distribution of the secondary current and, for example, leads to unequal thermal rise in the secondary rectifiers (D1 and D2). Another harmful effect is an increase in the output voltage ripple.

[0058] The operating conditions under which this instability occurs depend on the characteristics of the resonant tank, for example, on the values ​​of Cr, Ls, Lp of the LLC converter and the turns ratio of the transformer (in Figure 1 denoted as a:1:1 in ). For example, the inventors have observed that this instability typically occurs at very light loads (i.e., when the current sense signal Vs is very small and the offset of the zero current comparator has a significant effect). However, in this case, although not understood, there are typically no noticeable practical consequences due to the small current Is. In contrast, in some electronic converters, this may occur even at relatively high loads (e.g., at half load), and in this case, unequal thermal stresses may affect the reliability of the system. Likewise, the increased output voltage ripple may exceed the maximum specified value.

[0059] In this regard, US Pat. No. 11,387,739 B2 discloses a TSC controller that is less sensitive to input voltage offsets of a zero current comparator and / or disturbances that tend to change the duty cycle of a generated square wave from 50% by using an oscillator with a dual slope charge.

[0060] For example, in the first embodiment disclosed therein (such as US 11,387,739 B2 Figure 5 , Fig. 9 , Figure 23 and Figure 24), TSC is implemented in the following way:

[0061] 1. When the voltage applied to the resonant tank and the current flowing through the resonant tank have opposite signs, charging the capacitor with a first constant current during a time interval of a switching half cycle,

[0062] 2. When the voltage applied to the resonant tank and the current flowing through the resonant tank have equal signs, charging the capacitor with a second constant current (e.g., greater than the first constant current) up to the voltage level during the time interval of the switching half cycle, wherein such second constant current includes a current representing a feedback loop controlling the voltage (or current) output of the resonant converter (Ic of US 11,387,739 B2),

[0063] 3. When the capacitor voltage reaches the above voltage level, the half-bridge is switched and the capacitor is reset (usually to zero).

[0064] The solution proposed in patent US11,387,739B2 provides a control law for this current representing the feedback loop (Ic of US11,387,739B2), which depends on the circuit components (e.g., Ic of Figures 25 and 26 of US11,387,739B2). z and C z , even US11,387,739B2 Figure 3 and Figure 5 The capacitor C T ). Therefore, the accuracy of this current representing the feedback loop depends on the size of the circuit components, and even a small mismatch in such size can lead to significant deviations in the value of this current, resulting in additional trimming of the components and a larger die size.

[0065] A first solution not suffering from this problem can be found in "Self-Sustained Oscillating Resonant Converters Operating Above the Resonant Frequency" by H. Pinheiro, PK Jain, G. Joós, IEEE Transactions on Power Electronics, Vol. 14, No. 5, September 1999, pp. 803-814, which discloses a completely different circuit structure based on controlling the displacement angle between one of the resonant circuit variables (usually the current through the resonant inductor) and the voltage at the converter output. The proposed control technique is implemented with a controller comprising two cascaded integrators, based on a constant amplitude sawtooth signal synchronized with the switching frequency, and in which the amplitude is kept constant with respect to the changes in the switching frequency by a negative feedback loop, resulting in a high complexity overall. Summary of the invention

[0066] With the foregoing in mind, some embodiments of the present invention provide a simple control device. In particular, various embodiments relate to a PSC ("Phase Shift Control") device that receives a current representing a feedback loop and controls the displacement angle between the current flowing through the resonant circuit and the voltage at the output of the converter, and as such, the PSC device is not (or at least less) dependent on circuit components and their tolerances. This is achieved by still maintaining low sensitivity to input voltage offsets of the zero current comparator and / or to disturbances that tend to change the duty cycle of the generated square wave from 50%. This therefore results in a simpler and less critical resonant converter, and in the controller integrated circuit (IC), fine-tuning of the components can be simplified, resulting in a smaller die size.

[0067] Embodiments also relate to related integrated circuits, electronic converters, and methods.

[0068] The claims form an integral part of the technical teaching of the description provided herein.

[0069] As described above, various embodiments of the present disclosure relate to a driver circuit for an electronic resonant converter, such as a driver circuit integrated in a control IC. Such a resonant converter is configured to generate an output voltage or an output current at two output terminals from an input voltage applied to a positive input terminal and a negative input terminal.

[0070] For example, in various embodiments, the electronic converter includes at least one half-bridge, the half-bridge includes a high-side electronic switch and a low-side electronic switch connected in series between a positive input terminal and a negative input terminal, wherein the intermediate node between the high-side electronic switch and the low-side electronic switch represents a switch node. In addition, the resonant circuit, the rectifier and the filter circuit are connected between the switch node and the two output terminals. For example, the resonant circuit, the rectifier and the filter circuit may include a transformer. In this case, the capacitor and the first inductor may be connected in series with the primary winding of the transformer between the switch node and the positive or negative input terminal. In addition, the second inductor may be connected in parallel with the primary winding. Finally, the rectifier circuit may be connected between the secondary winding and the two output terminals. In various embodiments, the electronic converter also includes a current sensor, a rectifier and a filter circuit, and a feedback circuit, the current sensor being configured to generate a signal proportional to the resonant current flowing from the switch node to the resonant circuit, the feedback circuit being configured to generate a feedback signal, and the feedback signal is determined as a function of the output voltage (for the regulating voltage generator) or the output current (for the regulating current generator).

[0071] Therefore, in various embodiments, the driver circuit includes: first and second terminals configured to be connected to control terminals of a high-side electronic switch and a low-side electronic switch of the resonant converter so as to drive the high-side electronic switch and the low-side electronic switch via corresponding drive signals; a third terminal configured to be connected to a current sensor so as to receive a signal proportional to a resonant current flowing from a switching node between the high-side electronic switch and the low-side electronic switch to the resonant tank, rectifier and filter circuit of the resonant converter; and a fourth terminal configured to be connected to the feedback circuit so as to receive the feedback signal determined based on the output voltage or the output current.

[0072] In various embodiments, the driver circuit also includes: an analog zero current comparator configured to generate a first control signal indicating when the resonant current changes sign based on a signal received at the third terminal; a triangle wave generator circuit configured to provide a triangle wave signal at the output; and a comparison circuit configured to generate a second control signal indicating whether the triangle wave signal reaches a reference threshold.

[0073] Specifically, in various embodiments, the driver circuit is configured to drive the high-side and low-side electronic switches via the drive signal during the first and second consecutive switching half-cycles, wherein each of the first and second switching half-cycles ends when the comparison circuit indicates that the triangular wave signal has reached a reference threshold. Specifically, for this purpose, once the first switching half-cycle begins, the driver circuit disconnects the low-side electronic switch and closes the high-side electronic switch after a given first delay. Similarly, once the second switching half-cycle begins, the driver circuit disconnects the high-side electronic switch and closes the low-side electronic switch after a given second delay. The second delay can correspond to the first delay.

[0074] Instead, the duration of the first and second half cycles is controlled by a triangular wave generator circuit and an analog comparator. Specifically, in various embodiments, the triangular wave generator circuit is configured to generate a triangular wave signal in each of the first and second switching half cycles by:

[0075] increasing the triangular wave signal with a first slope in a first interval starting from the time when the corresponding half cycle starts and ending at the time when the first control signal indicates that the resonant current has changed sign, and

[0076] In a second interval starting from the time when the first control signal indicates that the resonant current has changed sign and ending at the time when the second control signal indicates that the triangular wave signal has reached the reference threshold, the triangular wave signal is decreased with a second slope.

[0077] Specifically, in various embodiments, the first slope has a positive value obtained by summing a negative first value and a positive second value, and the second slope has a negative value corresponding to the first negative value, wherein the absolute value of the first value is smaller than the absolute value of the second value, and the first value is proportional to the feedback signal.

[0078] For example, in various embodiments, the triangle wave generator circuit for this purpose includes an integrator circuit configured to generate a triangle wave signal by integrating the sum of the positive second value and the negative first value during the first interval and integrating the negative first value during the second interval.

[0079] For example, in the case of an analog implementation, the integrator circuit may include: an integrating capacitor connected to a node; a first current source configured to sink a first current corresponding to the first value from the node; and a second current source configured to supply a second current corresponding to the second value to the node, wherein the second current source is enabled during the first interval and the triangular wave signal corresponds to the voltage at the integrating capacitor. For example, to indicate the first interval, the driver circuit may be configured to assert a third control signal in response to determining that the second control signal indicates that the triangular wave signal reaches a reference threshold, and de-assert the third control signal in response to determining that the first control signal indicates that the resonant current changes sign. Therefore, in this case, when the third control signal is asserted, the second current source may be enabled.

[0080] Conversely, in a digital implementation, the triangle wave generator circuit may include a bidirectional digital counter configured to increase a count value at a rate proportional to the sum of a positive second value and a negative first value during a first interval and to decrease the count value at a rate proportional to the negative first value during a second interval.

[0081] In various embodiments, the reference threshold may not be constant, but may correspond to a ramp with a positive slope that starts at the beginning of the first and second switching half cycles. Alternatively, the reference threshold may be a ramp with a positive slope that starts after a fixed delay from the beginning of the first and second switching half cycles. In both cases, the ramp may be reset at the end of the first and second switching half cycles. Specifically, in various embodiments, the reference threshold has a slope greater than the first slope, or the ramp reference threshold has a first slope during the first interval and a second slope during the second interval, wherein the second slope is greater than the first slope, and wherein an average of the first slope and the second slope of the reference threshold is greater than the first slope of the triangle wave generator circuit.

[0082] For example, to generate such a ramp reference threshold, the driver circuit may include a threshold generation circuit including a capacitor connected between an output node and a ground node, a current generator configured to apply a current to the output node (thereby charging the capacitor), and a switch connected between the output node and the ground node (thereby selectively discharging the capacitor), wherein the ramp reference threshold corresponds to a voltage at the capacitor. In addition, the threshold generation circuit may include a control block or circuit configured to generate a control signal indicating a change in the reference signal, and to close the switch when the control signal indicates a change in the reference signal, or to open the switch when the control signal does not indicate a change in the reference signal.

[0083] In one embodiment, the device includes a driver circuit. The driver circuit includes: a first terminal configured to output a high-side gate drive signal; a second terminal configured to output a low-side gate drive signal; and a third terminal configured to receive a resonant current signal indicating a resonant current outside the driver circuit. The driver circuit includes: a fourth terminal configured to receive a feedback signal based on an output signal outside the driver circuit; an integrator circuit configured to generate a triangular wave integral signal based on the feedback signal; and a control circuit configured to receive the integral signal and the resonant current signal, and generate the high-side gate drive signal and the low-side gate drive signal based on the integral signal and the resonant current signal.

[0084] In one embodiment, a method includes: using a driver circuit of a resonant converter to drive a high-side switch of the resonant converter using a high-side gate drive signal; and using a driver circuit to drive a low-side switch of the resonant converter using a low-side gate drive signal. The method includes: using the driver circuit to receive a resonant current signal representing a resonant current in the primary side of the resonant converter; using the driver circuit to receive a feedback signal based on an output signal of the resonant converter; using an integrator circuit of the driver circuit to generate a triangular wave integration signal based on the feedback signal; and using the driver circuit to generate a high-side gate drive signal and a low-side gate drive signal based on the integration signal and the resonant current signal.

[0085] The solution as described herein helps to obtain a current representation of the feedback loop that is fairly independent of the circuit components, resulting in a less critical resonant converter and in a controller integrated circuit where component fine-tuning can be simplified, thus resulting in a smaller circuit die size. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] The characteristics and advantages of the present disclosure will become apparent from the following detailed description of practical embodiments thereof, which are illustrated by way of non-limiting example in the accompanying drawings, in which:

[0087] Figure 1 A circuit diagram of an LLC resonant converter according to the prior art is shown;

[0088] Figure 2 shows a block diagram of a resonant converter with TSC regulation of the output voltage according to the prior art;

[0089] Figure 3 An embodiment of a control device for a resonant converter using a PSC method is shown;

[0090] Figure 4 Shows Figure 3 Embodiment of the control device;

[0091] Figure 5 Various embodiments according to the present solution are shown. Figure 4 time diagram of the voltages involved in the device;

[0092] Figure 6 and Figure 7 Shows Figure 4 Details of the circuit;

[0093] Figure 8 An example of a particular type of interference amplification addressed by embodiments of the present solution is shown;

[0094] Fig. 9 An example of a circuit that may be used to generate a down ramp threshold according to an embodiment of the present solution is shown.

[0095] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. DETAILED DESCRIPTION

[0096] In the following description, various specific details are shown for the purpose of providing a deeper understanding of the embodiments. Embodiments may be provided without one or more specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the corresponding aspects of the embodiments.

[0097] References to "an embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc. that may appear in corresponding points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0098] The references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0099] Described below Figures 3 to 7 In, reference has been made Figure 1 or Figure 2 The parts, elements or components described are indicated by the same reference numerals used previously in these figures. These elements have been described, and in order not to burden this detailed description, these descriptions will not be repeated below.

[0100] Figure 3 FIG. 4 is a circuit diagram of a control device 210 for a resonant converter according to an embodiment of the present disclosure.

[0101] For example, such a control device 210 can be used to control Figure 1 and Figure 2 The operation of the (LLC) electronic converter is shown and the corresponding description all applies.

[0102] Therefore, in various embodiments, the driver circuit 210 receives a feedback signal, such as a current Ic, which is determined according to the output voltage Vout or the output current Iout. For example, in various embodiments, the control signal Ic is determined by a negative feedback control loop of the output voltage (see Figure 2 For example, when the driver circuit 210 is implemented in an integrated circuit, the driver circuit 210 may receive the feedback signal Ic via a pin of the integrated circuit.

[0103] In particular, in the embodiment considered, the control current Ic is connected to an optional input stage 2100 which essentially implements a power amplifier. Figure 8 A possible implementation of such an input stage is disclosed.

[0104] The output signal of the optional input stage 2100 , or if the optional input stage 2100 is not present, directly provides the control current Ic to the integration circuit 2300 , and in particular to the first current generator 2302 comprised therein.

[0105] exist Figure 3 In the embodiment shown, the driver circuit comprises:

[0106] an integration circuit 2300 configured to receive the output signal from the optional input stage 2100, or directly receive the control current Ic, and generate an integrated signal INT proportional to the integral of the feedback signal Ic (received directly from the input or through the optional input stage 2100 as previously described) during a given time period; and

[0107] The control circuit 2106 is configured to control the operation of the integration circuit 2300 via one or more control signals CTR1 , CTR2 based on the measurement signal Vs (proportional to the resonant current Is) and the integration signal INT received from the integration circuit 2300 .

[0108] Furthermore, the control circuit 2106 is configured to generate driving signals HSGD and LSGD for the high-side switch SW1 and the low-side switch SW2 , respectively, according to the measurement signal Vs and the integration signal INT received from such an integration circuit 2300 .

[0109] For example, in Figure 3 In FIG. 2 , the integration circuit 2300 includes an analog integrator 2304 , which includes a capacitor CT and a first current generator 2302 .

[0110] Specifically, in the embodiment considered, the analog integrator 2304 comprises an input terminal N1 and is configured to generate a signal INT proportional to the integral of the current received via the node N1. Specifically, in the embodiment considered, the capacitor CT is connected between the node N1 and a reference voltage such as ground, and the signal INT corresponds to the voltage VCT at the capacitor CT.

[0111] In the considered embodiment, the first current generator 2302 is configured to sink / drain a current I1 from the node N1 , wherein the current I1 is proportional to the feedback signal Ic, for example by a factor k. In various embodiments, this operation is done according to a control signal CTR1 received from the control circuit 2106 .

[0112] In various embodiments, capacitor CT may be external to an integrated circuit including driver circuit 210. Thus, node N1 may be connected to a pin of such an integrated circuit. Alternatively, capacitor CT may be internal and / or integrated within an integrated circuit including driver circuit 210.

[0113] like Figure 3 As shown, in various embodiments, the integrated circuit 2300 includes a second current generator 2306. Specifically, the second current generator 2306 provides / supplies the second current I2 to the node N1. In various embodiments, this operation is completed according to the control signal CTR2 received from the control circuit 2106.

[0114] Thus, in the embodiment considered, due to the directions of currents I1 and I2 , analog integrator 2304 receives (and capacitor CT is charged with) a current corresponding to the difference ( I2 − I1 ) between currents I2 and I1 .

[0115] Specifically, in various embodiments, the first current generator 2302 may be always enabled and provide a current I1 proportional to the current Ic, i.e., in each half cycle TA and TB (see Figure 5 ),thus:

[0116] During a first time period between the moment when the corresponding half cycle TA / TB starts and the moment when the signal Vs indicates that the resonant current Is changes its sign, the capacitor CT receives a (constant) current I2=Io from the second current generator 2306 and is simultaneously discharged by the first current generator 2302 with a current I1 proportional to the current Ic (e.g., I1=k·Ic); therefore, during such a time period, when the resonant voltage V HBWhen the current I2 / Io has an opposite sign to the current Is, the capacitor CT is charged by a current proportional to I2-I1 (i.e., Io-k·Ic). Therefore, in order to achieve the charging of the capacitor CT, the absolute value of the current I2 / Io should be higher / greater than the absolute value of the current I1; and

[0117] During a second time period between the moment when the signal Vs indicates that the resonant current Is has changed its sign and the moment when the corresponding half cycle TA / TB ends, the capacitor CT is discharged by the first current generator 2302 with a current I1 proportional to the current Ic (e.g., I1=k·Ic), while the second current generator 2306 is turned off (i.e., I2=0), for example, via the control signal CTR2; therefore, during such a time period, when the resonant voltage V HB When the current I1 and the current Is have the same sign, the capacitor CT is discharged via the current I1 (ie, k·Ic), that is, is discharged via a current proportional to Ic.

[0118] like Figure 5 As shown, basically, Figure 3 The embodiment shown is configured to charge and discharge the capacitor CT during each half cycle TA and TB, generating a voltage V having a triangular waveform. CT .

[0119] In order to obtain such a triangular waveform in the subsequent charge / discharge cycle of the capacitor CT, it may be beneficial to reach a steady-state condition. To this end, the following description may be considered.

[0120] As described above, in various embodiments, the voltage V CT The triangular waveform consists of and The rising / rising slope and falling / falling slope are composed of

[0121] The magnitude of the rising slope It depends linearly on the charging current I2-I1 and can be expressed as:

[0122]

[0123] Where T z Corresponds to the moment when the corresponding half cycle TA / TB begins (i.e., when the voltage V at the capacitor CT CT (substantially) equal to or less than the (lower) threshold V z , such as the voltage of ground GND1 or any other voltage) and the time interval between the moment when the signal Vs indicates that the resonant current Is has changed its sign. Figure 5 As shown, in various embodiments, the control circuit 2106 may be configured to generate the indication interval T in the following manner: zThe control signal S1:

[0124] In response to detecting the voltage V at the capacitor CT CT Equal to or less than the threshold V z and asserting signal S1; and

[0125] The signal S1 is de-asserted in response to detecting that the signal Vs indicates that the resonant current Is has changed sign.

[0126] Therefore, in the interval T z At the end, the voltage V at the capacitor CT CT Roughly corresponds to

[0127] Conversely, the magnitude of the downward slope depends linearly on the discharge current I1 and can be expressed as:

[0128]

[0129] Where T s is the duration of the time interval of the corresponding period (TA+TB). s At the end, the voltage V at the capacitor CT CT Approximately corresponds to V z .

[0130] Therefore, in order to achieve steady-state conditions in subsequent charge / discharge cycles of capacitor CT, it may be advantageous to satisfy the following conditions:

[0131]

[0132] This leads to the following expression:

[0133]

[0134] The inventors have observed that item T z / T s Proportional to the current-voltage phase shift Φ, that is:

[0135]

[0136] This leads to the following conditions:

[0137]

[0138] And, if I1 and current Ic are in proportion according to I1=k·Ic, then

[0139]

[0140] This is a condition that can ensure a steady-state condition in the charging and discharging of capacitor CT in subsequent cycles.

[0141] This condition provides a control law for this current representation of the feedback loop Ic which is (in principle) independent of the circuit components and their tolerances, facilitating the achievement of a desired accuracy of this current representation of the feedback loop Ic which is not affected by the dimensions of the circuit components, e.g. it is independent of the dimensions of the capacitor CT and the lower threshold V z In this way, mismatches in the dimensions of such components do not lead to any deviations in the value of such current Ic, so that capacitors and current matching are not required and additional fine-tuning of the dimensions of the components and larger die of the control integrated circuit can be avoided.

[0142] Figure 4 In more detail, Figure 3 Embodiments of the control device 210. Specifically, in the embodiment considered, the control circuit 210 further comprises a node (e.g., a pin or pad) N1 configured to be connected to a reference voltage via a capacitor CT. Furthermore, the control circuit 210 comprises a discharge circuit / first current generator 2302 within the integration circuit 2300, configured to generate a current I1 proportional to the current Ic absorbed / drawn from the node N1, e.g., I1=k·Ic (thus, providing a discharge current to the capacitor CT).

[0143] Specifically, in various embodiments, the current generator / discharge circuit 2302 is always enabled, i.e., the discharge circuit 2102 is enabled for each half cycle TA and TB. As previously described, the discharge circuit 2302 can receive the output signal of the optional input stage 2100, or directly receive the control current Ic if the optional input stage 2100 is not present, and generate a current I1 proportional to the feedback signal Ic.

[0144] Figure 3 The second current generator 2306 is implemented with a charging circuit / second current generator 2306 that provides a current I2=Io to the node N1 (therefore, provides a charging current to the capacitor CT). Specifically, in various embodiments, the charging circuit 2306 is only z During the enablement, for example, the charging circuit 2306 is enabled in response to the determination signal S1 being asserted, and the charging circuit 2306 is disabled in response to the determination signal S1 being de-asserted.

[0145] Therefore, in various embodiments, the Figure 3 The signal CTR1 corresponds to the signal S1, and the signal CTR2 corresponds to the signal S1.

[0146] As mentioned above, the control signal S1 may be a binary signal which is set at the time when the corresponding half-period TA / TB starts (ie, the voltage V CT Basically equal to or less than the threshold V z The voltage V at the capacitor CT is set to a high value, for example, in the interval between the moment when the signal Vs indicates that the resonant current Is has changed its sign and the moment when the corresponding half cycle TA / TB ends. CT is substantially equal to or less than the same previous lower threshold V z hour.

[0147] Therefore, if Figure 5 As shown, basically, Figure 4 The embodiment shown allows charging and discharging the capacitor CT during each half cycle TA and TB, thereby generating a voltage V having a triangular waveform. CT .

[0148] In the embodiment considered, the control circuit 2106 is therefore configured to CT (at node N1, corresponding to the integrated signal INT in different embodiments), the lower threshold V z The control signal S1 and the drive signals LSGD and HSGD are generated by the measurement signal Vs.

[0149] To this end, the control circuit 2106 may include:

[0150] A first comparator module 2108, configured to receive the measurement signal Vs and generate a control signal S3;

[0151] The second comparator block 2110 is configured to receive the voltage signal V at the capacitor CT. CT and the lower threshold V z , such as a voltage of ground GND1 or any other voltage, and generates a control signal S4; and

[0152] The circuit 2112 is configured to receive the control signals S3 and S4 and generate the control signal S1 and the drive signals LSGD and HSGD according to their values.

[0153] For example, in various embodiments, a signal Vs proportional to the resonant current Is is provided to the first comparator block 2108, which thus generates a binary control signal S3 indicating whether the signal Vs (corresponding to the resonant current Is) is positive or negative. Figure 4In the embodiment shown, the circuit 2108 can be implemented with a comparator CO1 receiving a voltage Vs at its positive input terminal, while its negative input terminal is connected to ground, for example GND1, and the output of such a comparator provides a signal S3. Thus, in the embodiment considered, when the signal Vs (resonant current Is) is positive, the signal S3 is high.

[0154] Furthermore, in the embodiment considered, the control circuit 2106 comprises a second comparator block 2110 configured to:

[0155] When the voltage V CT Reaching the lower threshold V z and the control signal S4 was previously asserted / set to another logic level (e.g., to high), de-asserting / setting the binary control signal S4 to a first logic level (e.g., to low), and

[0156] When the voltage V CT Reaching the lower threshold V z And when the control signal S4 was previously de-asserted / set to a first logic level (eg, low), the binary control signal S4 is asserted / set to a second logic level (eg, high).

[0157] Therefore, the control signal S4 indicates the periods TA and TB.

[0158] For example, in Figure 4 In the embodiment shown, the circuit 2110 can be implemented by a comparator CO2, which receives a voltage V at a positive input terminal. z , and the negative input terminal is connected to the voltage V at the capacitor CT CT , and the output of comparator CO2 provides a signal for triggering the output value of flip-flop FF1, which provides signal S4 at an output terminal. For example, in the embodiment considered, flip-flop FF1 is a JK flip-flop configured to have J and K inputs connected to a high logic level, and the output of comparator CO2 is connected to the clock input of flip-flop FF1.

[0159] In various embodiments, signals S3 and S4 are processed by circuit 2112 to generate control signal S1 and drive signals HSGD and LSGD for switches SW1 and SW2 .

[0160] In particular, in the embodiment under consideration, when the signal S3 indicates that the resonant current Is is negative and the signal S4 is set to a high logic level, the charging circuit 2114 is enabled via the signal S1, and when the signal S3 indicates that the resonant current Is is positive and the signal S4 is set to a low logic level, such a charging circuit 2114 is also enabled again via the signal S1. Conversely, in all other cases, the charging circuit 2114 is disabled via the signal S1. Thus, in various embodiments, the charging circuit 2114 is enabled in response to determining that the signal S1 is asserted, and is disabled in response to determining that the signal S1 is deasserted.

[0161] Specifically, the driver circuit 210 may generate the drive signals HSGD and LSGD so as to repeat the following four phases for each switching cycle (see Figure 5 ):

[0162] During the first time interval Δt1, the first electronic switch SW1 is closed and the second electronic switch SW2 is opened, whereby the switch node HB is connected to the positive input node 200a, i.e., the input voltage Vin;

[0163] During a second time interval Δt2, the first and second electronic switches SW1 / SW2 are turned off;

[0164] During a third time interval Δt3, the first electronic switch SW1 is opened and the second electronic switch SW2 is closed, whereby the switch node HB is connected to the negative input node 200 b , such as the ground GND1 ; and

[0165] During the fourth time interval Δt4, the first and second electronic switches SW1 / SW2 are turned off.

[0166] Thus, the half period TA corresponds to the second time interval Δt2 and the third time interval Δt3 (TA=Δt2+Δt3), and the half period TB corresponds to the fourth time interval Δt4 and the first time interval Δt1 (TB=Δt4+Δt1). Specifically, in various embodiments, the time interval Δt2 and the time interval Δt4 may have a constant duration Td (see again Figure 5 ).

[0167] As mentioned above, the signal S4 has indicated the half-cycles TA and TB, for example, the signal S4 is asserted during the half-cycle TA and is de-asserted during the half-cycle TB. Therefore, in various embodiments, the circuit 2106 can be configured as:

[0168] In response to the rising edge of signal S4 , immediately de-asserting signal LSGD and asserting signal HSGD after delay Δt2 = Td; and

[0169] In response to the falling edge of signal S4 , signal HSGD is de-asserted immediately after a delay Δt4 =Td and signal LSGD is asserted.

[0170] For example, Figure 6 An embodiment is shown in which the signal S4 is also fed to the monostable device MF1. Specifically, the output of the monostable device MF1 is set high after a delay of Td relative to each rising or falling edge of the signal S4. The output of the monostable device MF1 and the signal S4 are fed to a logic gate AND1, such as an AND gate, to generate the signal HSGD. In addition, the output of the monostable device MF1 and an inverted version of the signal S4 (as schematically shown by the invertor INV1) are fed to a logic gate AND2, such as an AND gate, to generate the signal LSGD. In general, the monostable device MF1 can also be implemented with other delay circuits, such as a delay line.

[0171] In parallel, the driver circuit 210 is configured to determine the instant at which the intervals TA and TB should end, ie the instant at which the intervals Δt3 and Δt1 should end.

[0172] For example, in Figure 4 In the illustrated embodiment, the control circuit 2106 may be configured to perform the following steps during the time interval TA:

[0173] Once the interval TA begins, for example in response to the falling edge of the signal S4, the signal Vs is waited for to indicate that the resonant current Is becomes zero / negative. During this interval, both the charging circuit 2114 and the discharging circuit 2102 are enabled, thereby charging the capacitor CT with a current proportional to I2-I1;

[0174] At the moment when signal Vs indicates that resonant current Is becomes negative, charging circuit 2114 is disabled (e.g., via signal S1), thereby discharging capacitor CT with a current proportional to I1 (and therefore proportional to Ic), and

[0175] Once the integrated signal (the voltage V at the capacitor CT) CT ) reaches the threshold V z (e.g., signaled via a rising edge of signal S4), the charging circuit 2114 is enabled again (via signal S1) and ends interval TA, thereby ending interval Δt3 and starting interval TB.

[0176] Instead, the control circuit 2106 may be configured to perform the following steps during the time interval TB:

[0177] Once interval TB begins, for example in response to the rising edge of signal S4, the signal Vs is waited for to indicate that the resonant current Is becomes zero / positive. During this interval, both the charging circuit 2114 and the discharging circuit 2102 are enabled, thereby charging the capacitor CT with a current proportional to I2-I1;

[0178] At the moment when signal Vs indicates that resonant current Is becomes positive, charging circuit 2114 is disabled (via signal S1), thereby discharging capacitor CT with a current proportional to I1 (and therefore proportional to Ic), and

[0179] Once the integrated signal (the voltage V at the capacitor CT) CT ) reaches the lower threshold V z , as signaled, for example, via the falling edge of signal S4 , the charging circuit 2114 is enabled again (via signal S1 ) and ends the interval TB, thereby ending the interval Δt1 and starting the interval TA.

[0180] Specifically, during each half cycle TA or TB, the control circuit 2106 is configured as follows:

[0181] Once the corresponding half cycle starts, for example in response to the edge of the signal S4, the waiting signal Vs indicates that the resonant current Is changes its sign, i.e. becomes positive or negative;

[0182] At the moment when the signal Vs indicates that the resonant current Is has changed sign, the charging circuit 2114 is disabled, thereby discharging the capacitor CT with a current proportional to I1, and

[0183] Once the integrated signal INT (the voltage V at the capacitor CT) CT ) reaches the lower threshold V z , for example, in response to the immediately following edge of the signal S4, the charging circuit 2114 is enabled again and the corresponding half cycle ends, thereby starting the subsequent half cycle (TB or TA).

[0184] In parallel, the control circuit 2106 may:

[0185] Once the interval TA starts, for example, in response to the falling edge of the signal S4, the signal LSGD is set to high after a period Td, thereby turning on the low-side switch SW2, and at the end of the interval TA, for example, in response to the rising edge of the signal S4, the signal LSGD is set to low at the same time, thereby turning off the low-side switch SW2.

[0186] Once interval TB starts, for example in response to the rising edge of signal S4, signal HSGD is set high after period Td to turn on high-side switch SW1, and at the end of interval TB, for example in response to the falling edge of signal S4, signal HSGD is set low at the same time to turn off high-side switch SW1.

[0187] In various embodiments, one or more of the above analog circuits may also be implemented digitally. Figure 7 As shown, the analog integrator / ramp generator 2300 can be replaced by a digital counter configured to receive (e.g., via an analog-to-digital converter) a digital sample Icd of the current Ic, wherein the counter 2300a is a bidirectional counter that counts at a speed proportional to the current I2-I1 when counting up and at a speed proportional to I1 when counting down. For example, the "counting speed" of the counter can be controlled by changing the step size / increment value of the counter and / or the frequency of the clock signal CLK used by the counter. Therefore, in this case, the circuit 2110 can also be replaced by a corresponding digital circuit that is configured to compare the digital ramp signal provided by the counter 2300a with the current representing the threshold value V z For example, circuits 2300a and 2110 may be implemented using a microprocessor programmed with software instructions. Similarly, Figure 6 The circuit shown (or the complete circuit 2112) can also be implemented by software instructions. Thus, since modern microcontrollers typically include analog-to-digital converters and analog comparators, circuits 2106 and 2300a can be implemented using a microcontroller.

[0188] As mentioned above, Figure 5 Shows Figure 4 Time diagram of the voltages involved in the device.

[0189] Figure 5 The first figure shows the resonant voltage V HB (dashed line) and the behavior of a voltage Vs which represents (eg is proportional to) the current Is flowing through the resonant tank circuit (solid line).

[0190] As described above, in various embodiments, the control signal S4 can be at a voltage V CT Reaching the lower threshold V z is set to a first logic level (eg, set to low), and the control signal S4 is previously set to another logic level (eg, set to high), and at the voltage V CT Reaching this lower threshold V z is set to the second logic level (eg, set to high), and the control signal S4 was previously set to the first logic level (eg, set to low), that is, whenever the voltage V CT Reaching the threshold V z In various embodiments, the control signal S4 can be set to low as a first logic level and set to high as a second logic level (e.g., Figure 5In other embodiments, the control signal S4 may be set high as a first logic level and set low as a second logic level.

[0191] As previously mentioned, in various embodiments, the control signal S3 indicates whether the signal Vs (corresponding to the resonant current Is) is positive or negative.

[0192] In various embodiments, when the signal Vs (corresponding to the resonant current Is) is positive (eg, Figure 5 As shown in FIG. 1 , the control signal S3 may be set to high. In other embodiments, when the signal Vs (corresponding to the resonant current Is) is positive, the control signal S3 may be set to low.

[0193] Signal S1 is set by circuit 2112 according to the values ​​of control signals S3 and S4. For example, in various embodiments, the circuit 2112 is configured as follows:

[0194] If the signal S3 is set to a low logic level and the signal S4 is set to a high logic level, or if the signal S3 is set to a high logic level and the signal S4 is set to a low logic level, the signal S1 is set to a high logic level. Otherwise, the signal S1 is set to a low logic level. If the control signal S4 is set to a low logic level, as a first logic level, and is set to a high logic level, as a second logic level, and the control signal S3 is set to a high logic level when the signal Is is positive (this is the case in Figure 5 ), or this configuration is used if control signal S4 is set high as a first logic level and is set low as a second logic level, and control signal S3 is set low when signal Is is positive.

[0195] If the signal S3 is set to a low logic level and the signal S4 is set to a low logic level, or if the signal S3 is set to a high logic level and the signal S4 is set to a high logic level, the signal S1 is set to a high logic level. Otherwise, the signal S1 is set to a low logic level. This configuration is used if the control signal S4 is set to high, as a first logic level, and is set to low, as a second logic level, and the control signal S3 is set to high when the signal Is is positive, or if the control signal S4 is set to low, as a first logic level, and is set to high, as a second logic level, and the control signal S3 is set to low when the signal Is is positive.

[0196] As previously described, when the control signal S1 is asserted / set to a high level, the charging circuit 2114 is enabled by the circuit 2112, and the capacitor CT is charged by a current proportional to I2-I1. In practice, the control signal S1 is set in the period between the moment when the corresponding half-cycle TA / TB begins and the moment when the signal Vs indicates that the resonant current Is has changed its sign. During this period, the capacitor CT is charged by the (constant) current I2=Io from the charging circuit 2114, and is discharged by the discharge circuit 2102 with a current I1 proportional to the current Ic (e.g., I1=k·Ic). This generally results in the charging of the capacitor CT, and results in a voltage V at the capacitor CT From substantially equal to or less than the lower threshold V z The value rises to a value close to the rising slope The value of the amplitude.

[0197] Similarly, when the control signal S1 is deasserted / set to a low logic level, the charging circuit 2114 is disabled by the circuit 2112, and the capacitor CT is discharged by a current proportional to I1, thereby being discharged to Ic. In fact, the control signal S1 is not set in the period between the moment when the signal Vs indicates that the resonant current Is has changed sign and the moment when the corresponding half cycle TA / TB ends. In this period, the capacitor CT is discharged by the discharge circuit 2102 with a current I1 proportional to the current Ic (e.g., I1=k·Ic), resulting in a voltage V at the capacitor CT of CT From the approaching downhill slope The value of the amplitude (which is essentially equal to the rising slope The amplitude of the z The value of .

[0198] Figure 5 Another embodiment is shown, in which the threshold V z is not constant, but the driver circuit 210 is configured to:

[0199] Increase threshold V with (constant) slope P3 z ;as well as

[0200] In response to detecting the start of the next half cycle, for example, in response to each edge in the signal S4, that is, whenever the voltage V CT Equal to or less than the threshold V z When the reset threshold V z .

[0201] The behavior of signals HSGD and LSGD has been previously described in detail, and therefore, their description will not be repeated in order not to overburden the current description.

[0202] Figure 8 shows the influence of voltage VCT An example of a specific type of interference amplification behavior that is addressed by embodiments of the present solution.

[0203] Figure 8 shows that in a given half cycle During the voltage V CT behavior, i.e., during TA or TB, such that the voltage V CT Since the voltage transformer CT( Figure 8 The charging (i.e., with a current proportional to I2-I1) and discharging (i.e., with a current proportional to I1, Ic) of the battery (i.e., with a current proportional to I1) and discharging (i.e., with a current proportional to I1, Ic) of the battery have a triangular waveform and show that the same half cycle The voltage V affected by the disturbance (continuous line) during CT of the example behavior.

[0204] Specifically, if the lower threshold V z is a constant voltage value, and if the voltage V CT The disturbance is due to the change of the duty cycle of the signal S1, i.e., the modification of the time when the control signal S1 should be set to a high logic level, i.e., ΔT z , for voltage V CT The effect is the half cycle considered a reduction in the number of.

[0205] Such amount is greater than the original change in the duty cycle of signal S1, ΔT z , therefore, the original change propagates to the voltage V CT When it is magnified.

[0206] In fact, if the lower threshold V z is a constant voltage value, then any change in the duty cycle of the signal S1, for example, a modification of the time during which the control signal S1 should be set to a high logic level, ie, ΔT z , resulting in a half cycle The change in TA and / or TB is equal to:

[0207]

[0208] in

[0209]

[0210] Where P1 and P2 are the voltages V during the charging and discharging phases respectively. CT The slope of the side of the triangular waveform. Therefore, the slope P1 is proportional to the charging current I2-I1, and the slope P2 is proportional to the discharging current I1, and therefore proportional to IC.

[0211] Therefore, any change in the duty cycle of the signal S1, i.e., a modification of the time at which the control signal S1 should be set to a high logic level, ie, ΔT z , is amplified and causes the duty cycle of the half-bridge to deviate from the desired value of 50%. Specifically, the square wave voltage V HB The duty cycle deviation is equal to the amount 50%, resulting in an asymmetry on the primary side of the circuit and therefore different secondary currents flowing on the secondary side.

[0212] In various embodiments, in order to avoid (or at least reduce) the amplification of this type of interference and maintain the symmetry of the circuit, at the beginning of each half cycle TA and / or TB, the voltage V at the capacitor CT is set to CT With the lower threshold V z For comparison, the lower threshold V z is a ramp with a slope P3 that is synchronized with the switch, that is, its value is reset to an initial value, for example, to the ground value GND3. Therefore, when the voltage V at the capacitor CT CT The falling part is connected to the lower ramp threshold V with slope P3. z When the two phases intersect, the voltage V at the capacitor CT CT is considered to be substantially equal to or less than the downslope threshold V having a slope P3. z .

[0213] In this case, the change of half-cycle TA and / or TB, i.e. can be restated as:

[0214]

[0215] in

[0216] If P3>P1

[0217] Therefore, the change of the half-period TA and / or TB depends on the slope P3, and therefore, by choosing a slope P3 with a value greater than the slope P1, proportional to the current I1, the impact of this type of interference on the duty cycle of the half-bridge and on the symmetry of the circuit can be reduced or even substantially eliminated.

[0218] Notice, Figure 6 shows the use of a downslope threshold V having a slope P3 that does not satisfy the condition P3>P1 z Therefore, even by using the down-slope threshold value V having a slope P3 smaller than the slope P1 z , it is also possible to obtain the change in the half-cycle TA and / or TB Significantly smaller than the change in TA and / or TB in half a period That is, considering a constant lower threshold V z The amount of change obtained is such that in this case also the effect of alleviating the undesired change of the half-period TA and / or TB is obtained.

[0219] Therefore, by satisfying the condition P3>P1, the change of the obtained half-period TA and / or TB can be reduced by an amount This amount is further reduced if compared to the reduction obtained if the value of slope P3 is less than the value of slope P1. In various embodiments, by satisfying the condition P3>P1, the resulting change of half periods TA and / or TB can have an amount that is even negligible if compared to the length of half periods TA and / or TB.

[0220] In addition, the lower ramp threshold V z Neither the value of the slope P3 nor the value of the slope P3 affect the accuracy of the control law used to represent this current of the feedback loop Ic used to ensure steady-state conditions for charging and discharging the capacitor CT in subsequent cycles.

[0221] In a variant embodiment, the down-slope threshold V z It may not start at the same time as the commutation of the half-bridge (e.g. Figure 8 ), but can be equal to the delay T d The delay starts after a fixed delay where switches SW1 and SW2 are both open. The delay down ramp threshold V z The start of can have a larger value that allows the use of slope P3 without increasing the downslope threshold V z This technical effect is for increasing the value of the slope P3 without increasing the downslope threshold V z The final value may be of interest because if the downslope threshold V z The final value is too large, that is, if the downslope threshold V z The maximum value reached, that is, the peak value is too high, then the maximum dynamic characteristics of the circuit are reached, and finally the down-slope threshold V z will be distorted.

[0222] In a variant embodiment, the down-slope threshold V z Can have dual slope behavior. For example, the down slope threshold V z At time interval T z The period may have a first slope greater than zero, for example, and in the half switching period T z During the remaining portion of the period, the lower slope threshold V may have a second slope, for example, having a value higher than the value of such a first slope. zModification of the ratio between the first slope and the second slope of can modify the dynamic behavior of the circuit. For example, if such a ratio is increased, the response to a control step change tends to be more overdamped. Note that if the downslope threshold V z With dual slope behavior, the expected downslope threshold V z The average slope of the first slope and the second slope is P avg Requirements:

[0223] P avg >P1

[0224] Note that in a variant embodiment of this solution, the down-slope threshold V may be implemented using a resettable up-counter clocked at a higher speed than the bidirectional counter uses when counting. z .

[0225] Fig. 9 An example of a circuit 30 is shown, which may be used to generate a lower threshold V such as a ramp having a slope P3. z .

[0226] The circuit 30 is configured to receive the control signal S4, that is, when the voltage V CT Reaching the lower threshold V z The pulse width modulation (PWM) control signal that changes its state when the comparator block 2110 is switched to provide a lower ramp threshold value V with a slope P3 to the second comparator block 2110. z .

[0227] The input control signal S4 is provided to the control block 302 which is configured to output a control signal, for example, when a change / edge in the logic input S4 is detected, ie on both rising and falling edges.

[0228] This control block 302 is coupled to the gate terminal of a third electronic switch SW3, eg a FET, eg an n-channel FET, eg an NMOS, having its drain terminal coupled to the output node N2 and its source terminal coupled to the ground GND3.

[0229] The current generator 304 and the capacitor C are coupled in parallel with the third switch SW3 between the same nodes, ie, between the output node N2 and the ground GND3. x 306 , the current generator 304 is configured to generate a current having a value equal to Ix.

[0230] Therefore, during the time when the control signal S4 is constant (ie, does not change its state), the third switch SW3 is turned off so that the current Ix generated by the current generator 304 can be applied to the capacitor C x306 charging, causing the voltage of the output node N2 to rise (i.e., slope), which rise is proportional to the value of the current Ix down slope threshold V z .

[0231] Conversely, when the control block 302 detects a state change in the signal S4, the third switch SW3 is closed, connecting the output node N2 to the ground GND3, thereby resetting the lower threshold V z The value of capacitor C x 306 is discharged to ground GND3.

[0232] In order to effectively reduce the interference amplification discussed above, in various embodiments, during the charging phase of capacitor CT, the slope value of such ramp P3 should preferably be higher than the voltage V CT In fact, if the interference attenuation condition P3>P1 is met, the lower slope threshold V z The slope of may not be critical.

[0233] Therefore, it is ideal to satisfy:

[0234] in

[0235] In this solution, the current I x The value of does not need to closely match the value of current I2, but such a current I x In addition, the capacitor C x There is also no need to closely match the value of capacitor CT, thus avoiding additional trimming of components and larger die size, resulting in an overall less complex control circuit that consumes less silicon.

[0236] In various embodiments, both currents I1 and I2 may be internally fixed or externally programmable via dedicated pins, for example, by providing a reference voltage and external resistors and / or current mirrors with appropriate transfer ratios.

[0237] It can thus be understood how the solution described herein facilitates obtaining a simple PSC control device having a current representing the feedback loop Ic that is independent of the circuit components and their tolerances and that still retains low sensitivity to input voltage offsets of the zero-current comparator and / or to disturbances tending to vary the duty cycle of the generated square wave from 50%, thus resulting in a simpler and less critical resonant converter in which fine-tuning of the components can be simplified and with a smaller die size.

[0238] Without prejudice to the essential principles, the details and embodiments may vary even significantly with respect to what has been described merely by way of example, without departing from the scope of the embodiments.

[0239] In one embodiment, a driver circuit (210) for a resonant converter (20) is configured to generate an output voltage (Vout) or an output current (Iout) at two output terminals (202a, 202b) from an input voltage (Vin) applied to positive (200a) and negative (200b) input terminals. The driver circuit (210) includes: a first terminal and a second terminal configured to be connected to control terminals of a high-side electronic switch (SW1) and a low-side electronic switch (SW2) of the resonant converter (20) so as to drive the high-side electronic switch (SW1) and the low-side electronic switch (SW2) via corresponding drive signals (HSGD, LSGD); and a third terminal configured to be connected to a current sensor (222) so as to receive a signal (Vs) proportional to a resonant current (Is) flowing from a switch node (HB) between the high-side electronic switch (SW1) and the low-side electronic switch to a resonant tank, a rectifier and a filter circuit (204) of the resonant converter (20). a fourth terminal configured to be connected to a feedback circuit (212-218) so as to receive a feedback signal (Ic) determined according to an output voltage (Vout) or an output current (Iout); an analog zero current comparator (2108) configured to generate a first control signal (S3) indicating when the resonant current (Is) changes sign according to a signal (Vs) received at the third terminal; a triangular wave generator circuit (2300; 2300a) configured to provide a triangular wave signal (INT) at an output; and a comparison circuit (2110) configured to generate a signal indicating whether the triangular wave signal (INT) reaches a reference threshold value (V z ) of the first control signal (S4); wherein the driver circuit (210) is configured to: drive the high-side (SW1) and the low-side (SW2) electronic switches via the drive signal (HSGD, LSGD) during consecutive first (TB) and second (TA) switching half cycles, wherein when the comparison circuit (2110) indicates that the triangular wave signal (INT) has reached the reference threshold value (V z ), each of the first (TB) and the second (TA) switching half cycles ends, once the first switching half cycle (TB) starts, the low-side electronic switch (SW2) is turned off, and after a first delay (T d ), and once the second switching half cycle (TA) begins, the high-side electronic switch (SW1) is turned off, and after a second delay (T d) after closing the low-side electronic switch (SW2); wherein the triangular wave generator circuit (2300) is configured to generate the triangular wave signal (INT) in each of the first (TB) and the second (TA) switching half-cycles by: in a first interval (T starting at the moment when the corresponding half-cycle (TA, TB) starts and ending at the moment when the first control signal (S3) indicates that the resonant current (Is) has changed sign z ), the triangular wave signal (INT) is increased with a first slope (I2-I1), and the triangular wave signal (INT) is increased from the moment when the first control signal (S3) indicates that the resonant current (Is) has changed its sign and when the second control signal (S4) indicates that the triangular wave signal (INT) has reached a reference threshold value (V z ), in a second interval ending at the moment when the triangular wave signal (INT) is reduced with a second slope (-I1); wherein the first slope (I2-I1) has a positive value obtained by summing the negative first value (-I1) and the positive second value (I2), and the second slope (-I1) has a negative value corresponding to the first negative value (-I1), wherein the absolute value of the first value (I1) is smaller than the absolute value of the second value (I2), and the first value (I1) is proportional to the feedback signal (Ic).

[0240] The triangle wave generator circuit (2300; 2300a) may include an integrator circuit configured to generate a triangle wave signal (INT) by integrating: - during a first interval (T z ) period, the sum of the positive second value (I2) and the negative first value (I1), and during the second interval, the negative first value (I1).

[0241] The integrator circuit may include: an integrating capacitor (CT) connected to a node (N1); a first current source (2302) configured to sink a first current corresponding to the first value (-I1) from the node (N1); and a second current source (2306) configured to provide a second current corresponding to the second value (I2) to the node (N1), wherein the second current source (2306) may be connected to the node (N1) during the first interval (T z ) is enabled during the

[0242] The driver circuit may include a control circuit (2106) configured to: in response to determining that the second control signal (S4) indicates that the triangular wave signal (INT) reaches a reference threshold (V z) and assert a third control signal (S1); in response to determining that the first control signal (S3) indicates that the resonant current (Is) changes sign, de-asserting the third control signal (S1); wherein, when the third control signal (S1) is asserted, the second current source (2306) can be enabled.

[0243] The triangular wave generator circuit (2300) may include a bidirectional counter configured to: z ), during the first interval, the count value is increased at a rate proportional to the sum of the positive second value (I2) and the negative first value (I1), and during the second interval, the count value is decreased at a rate proportional to the negative first value (-I1).

[0244] Reference Threshold (V z ) can be a ramp with a positive slope that starts at the beginning of the first (TB) and second (TA) switching half cycles, or at a fixed delay (T d ) and the ramp can be reset at the end of the first (TB) and second (TA) switching half cycles.

[0245] Ramp reference threshold (V z ) may have a slope (P3) greater than the first slope (I2-I1); or a slope reference threshold (V z ) may have a first interval (T z ) during the first interval and a second slope during the second interval, wherein the second slope may be greater than the first slope, and wherein the ramp reference threshold (V z ) is the average of the first slope and the second slope (P avg ) can be greater than the first slope (I2-I1).

[0246] Ramp reference threshold (V z ) may be generated by a threshold generation circuit (30) configured to receive a second control signal (S4), and may include: a control block (302) configured to generate a control signal (S4) indicating a change in the reference signal; a third switch (SW3) connected between an output node and a ground node (GND3); a third current generator (304) coupled between the output node and the ground node (GND3) and configured to generate a third current (I x ); and a second capacitor (C coupled between the output node and the ground node (GND3) x, 306); wherein the control block (302) can be configured to: close the third switch (SW3) when the control signal indicates a change in the reference signal (S4); and open the third switch (SW3) when the control signal may not indicate a change in the reference signal (S4).

[0247] The third current (I x ) may be greater than the first value (I1), the second value (I2), the capacitance of the integrating capacitor (CT), and the capacitance of the second capacitor (C x , 306) and the threshold value obtained.

[0248] In one embodiment, an integrated circuit comprises a driver circuit (210), wherein first, second, third and fourth terminals of the driver circuit (210) are connected to respective pins of the integrated circuit.

[0249] In one embodiment, an electronic converter comprises positive (200a) and negative (200b) input terminals; two output terminals (202a, 202b) for providing an output voltage (Vout) or an output current (Iout); at least one half-bridge comprising a high-side (SW1) and a low-side (SW2) electronic switch connected in series between the positive (200a) and negative (200b) input terminals, wherein an intermediate node between the high-side (SW1) and the low-side (SW2) electronic switch represents a switch node (HB); a switching node (HB) connected between the switch node (HB) and the two output terminals (202a, 202b); , 202b) between the resonant tank, rectifier and filter circuit (204); a current sensor (222) configured to generate a signal (Vs) proportional to a resonant current (Is) flowing from the switching node (HB) to the resonant tank, rectifier and filter circuit (204); a feedback circuit (212-218) configured to generate a feedback signal (Ic), the feedback signal (Ic) being determined according to the output voltage (Vout) or the output current (Iout); and a driver circuit (210) according to any one of the preceding claims 1 to 10.

[0250] The resonant tank, rectifier and filter circuit (204) may include: a transformer (T) including a primary winding (T1) and a secondary winding (T2); a capacitor (Cr) and a first inductor (Ls) connected in series with the primary winding (T1) between the switch node (HB) and the positive (200a) or negative (200b) input terminal; a second inductor (Lp) connected in parallel with the primary winding (T1); and a rectifier circuit (D1, D2) connected between the secondary winding (T2) and the two output terminals (202a, 202b).

[0251] In one embodiment, a method of operating an electronic converter includes driving a high-side (SW1) and a low-side (SW2) electronic switch via a drive signal (HSGD, LSGD) during a first (TB) and a second (TA) consecutive switching half-cycle, wherein each of the first (TB) and the second (TA) switching half-cycle is terminated after a triangular wave signal (INT) has reached a reference threshold (V z ), once the first switching half cycle (TB) begins, the low-side electronic switch (SW2) is turned off, and after the first delay (T d ) and once the second switching half cycle (TA) begins, the high-side electronic switch (SW1) is turned off and after the second delay (T d ) after closing the low-side electronic switch (SW2); and generating the triangular wave signal (INT) in each of the first switching half-cycle (TB) and the second switching half-cycle (TA) by: in a first interval (T starting at the moment when the corresponding half-cycle (TA, TB) starts and ending at the moment when the resonant current (Is) has changed its sign z ), the triangular wave signal (INT) is increased with a first slope (I2-I1), and the triangular wave signal (INT) is increased from the moment when the resonant current (Is) has changed its sign and when the triangular wave signal (INT) has reached the reference threshold value (V z ), in a second interval ending at the moment when the triangular wave signal (INT) is reduced with a second slope (-I1); wherein the first slope (I2-I1) has a positive value obtained by summing the negative first value (-I1) and the positive second value (I2), and the second slope (-I1) has a negative value corresponding to the first negative value (-I1), wherein the absolute value of the first value (I1) is smaller than the absolute value of the second value (I2), and the first value (I1) is proportional to the feedback signal (Ic).

[0252] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are authorized. Therefore, the claims are not limited by this disclosure.

Claims

1. A driver circuit for a resonant converter, comprising: a first terminal configured to output a high-side gate drive signal to a high-side electronic switch of the resonant converter; a second terminal configured to output a low-side gate drive signal to a low-side electronic switch of the resonant converter; a third terminal configured to receive a signal proportional to a resonant current flowing in a primary side of the resonant converter; a fourth terminal configured to receive a feedback signal based on an output voltage or an output current of the resonant converter; an analog zero current comparator configured to generate a first control signal indicating when the resonant current changes sign based on a signal received at the third terminal, a triangle wave generator circuit configured to provide a triangle wave signal; as well as a comparison circuit configured to generate a second control signal, wherein the second control signal indicates whether the triangular wave signal reaches a reference threshold; The driver circuit is configured as follows: driving the high-side electronic switch and the low-side electronic switch via the high-side gate drive signal and the low-side gate drive signal during consecutive first and second switching half cycles, wherein each of the first and second switching half cycles ends when the comparison circuit indicates that the triangular wave signal has reached the reference threshold, opening the low-side electronic switch as soon as the first switching half-cycle begins and closing the high-side electronic switch after a first delay, and opening the high-side electronic switch as soon as the second switching half-cycle begins, and closing the low-side electronic switch after a second delay; The triangular wave generator circuit is configured to generate the triangular wave signal in each of the first switching half cycle and the second switching half cycle by: increasing the triangular wave signal with a first slope in a first interval starting from the time when the corresponding half cycle starts and ending at the time when the first control signal indicates that the resonant current has changed sign, and reducing the triangular wave signal with a second slope in a second interval starting from a time when the first control signal indicates that the resonant current has changed sign and ending at a time when the second control signal indicates that the triangular wave signal has reached the reference threshold; The first slope has a positive value obtained by summing a negative first value and a positive second value, and the second slope has a negative value corresponding to the first negative value, wherein an absolute value of the first value is smaller than an absolute value of the second value, and the first value is proportional to the feedback signal.

2. The driver circuit of claim 1 , wherein the triangular wave generator circuit comprises an integrator circuit configured to generate the triangular wave signal by integrating: during the first interval, the sum of the positive second value and the negative first value, and During the second interval, the negative first value.

3. The driver circuit of claim 2 , wherein the integrator circuit comprises: The integrated capacitor is connected to the node; a first current source configured to sink a first current corresponding to the first value from the node; as well as A second current source is configured to provide a second current corresponding to the second value to the node, wherein the second current source is enabled during the first interval.

4. The driver circuit according to claim 3, wherein the driver circuit comprises a control circuit, wherein the control circuit is configured to: asserting a third control signal in response to determining that the second control signal indicates that the triangle wave signal has reached a reference threshold; de-asserting the third control signal in response to determining that the first control signal indicates that the resonant current changes sign; Wherein the second current source is enabled when the third control signal is asserted.

5. The driver circuit of claim 2 , wherein the triangular wave generator circuit comprises a bidirectional counter configured to: During the first interval, the count value is increased at a rate proportional to the sum of the positive second value and the negative first value, and During the second interval, the count value is decreased at a rate proportional to the negative first value.

6. The driver circuit of claim 1 , wherein the reference threshold is a ramp having a positive slope, the ramp starting at the beginning of the first switching half cycle and the second switching half cycle, or starting after a fixed delay from the beginning of the first switching half cycle and the second switching half cycle, and wherein the ramp is reset at the end of the first switching half cycle and the second switching half cycle.

7. The driver circuit according to claim 6, wherein: The slope reference threshold has a slope greater than the first slope; or The ramp reference threshold has a first slope during the first interval and a second slope during the second interval, wherein the second slope is greater than the first slope, and wherein an average of the first slope and the second slope of the ramp reference threshold is greater than the first slope.

8. The driver circuit according to claim 6, wherein the ramp reference threshold is generated by a threshold generation circuit, the threshold generation circuit being configured to receive the second control signal and comprising: a control block configured to generate a control signal indicating a change in the reference signal; a third switch coupled between the output node and the ground node; a third current generator coupled between the output node and the ground node and configured to generate a third current; as well as a second capacitor coupled between the output node and the ground node; The control block is configured as follows: When the control signal indicates a change in the reference signal, closing the third switch; and When the control signal does not indicate a change in the reference signal, the third switch is turned off. 9 . The driver circuit according to claim 8 , wherein the third current is greater than a threshold value obtained from the first value, the second value, a capacitance of the integrating capacitor, and a capacitance of the second capacitor.

10. The driver circuit of claim 1, wherein the driver circuit is an integrated circuit, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal of the driver circuit are connected to corresponding pins of the integrated circuit.

11. An apparatus comprising: A driver circuit comprising: A first terminal configured to output a high-side gate drive signal; A second terminal configured to output a low-side gate drive signal; a third terminal configured to receive a resonant current signal indicative of a resonant current external to the driver circuit; a fourth terminal configured to receive a feedback signal based on an output signal external to the driver circuit; an integrator circuit that generates a triangular wave integrated signal based on the feedback signal; and The control circuit is configured to receive the integrated signal and the resonant current signal, and is configured to generate the high-side gate drive signal and the low-side gate drive signal based on the integrated signal and the resonant current signal.

12. The device according to claim 11, comprising an electronic converter, the electronic converter comprising: Positive input terminal and negative input terminal; Two output terminals, used for providing the output signal, wherein the output signal is either an output voltage or an output current; At least one half-bridge comprises a high-side electronic switch and a low-side electronic switch connected in series between the positive input terminal and the negative input terminal, wherein an intermediate node between the high-side electronic switch and the low-side electronic switch is a switching node, wherein the high-side electronic switch comprises a gate terminal receiving the high-side gate drive signal, and wherein the low-side electronic switch comprises a gate terminal receiving the low-side gate drive signal.

13. The apparatus of claim 12, wherein the electronic converter comprises: a resonant tank, a rectifier and a filter circuit connected between the switch node and the two output terminals, wherein the resonant current flows from the switch node to the resonant tank, the rectifier and the filter circuit; a current sensor configured to generate the resonant current signal proportional to the resonant current; The feedback circuit is configured to generate the feedback signal according to the output signal.

14. The apparatus of claim 13, wherein the resonant tank, the rectifier, and the filter circuit comprise: A transformer, including a primary winding and a secondary winding; a capacitor and a first inductor connected in series with the primary winding between the switch node and the positive input terminal or the negative input terminal; a second inductor connected in parallel with the primary winding; as well as The rectifier circuit D2 is connected between the secondary winding and the two output terminals.

15. The apparatus of claim 12, wherein the control circuit comprises: an analog zero current comparator configured to generate a first control signal indicating when the resonant current changes sign based on the signal received at the third terminal; as well as A comparison circuit is configured to generate a second control signal, wherein the second control signal indicates whether the triangular wave signal reaches a reference threshold, wherein the control circuit is configured to generate the high-side gate drive signal and the low-side gate drive signal based on the first control signal and the second control signal.

16. The apparatus of claim 14, wherein the driver circuit is configured to: driving the high-side electronic switch and the low-side electronic switch via the high-side gate drive signal and the low-side gate drive signal during consecutive first and second switching half cycles, wherein each of the first and second switching half cycles ends when the comparison circuit indicates that the triangular wave signal has reached the reference threshold; opening the low-side electronic switch once the first switching half-cycle begins, and closing the high-side electronic switch after a first delay; as well as Once the second switching half cycle begins, the high-side electronic switch is opened, and after a second delay the low-side electronic switch is closed.

17. The apparatus of claim 16, wherein the integrator circuit is configured to generate the triangular wave integrated signal in each of the first switching half-cycle and the second switching half-cycle by: increasing the triangular wave signal with a first slope in a first interval starting from the moment the corresponding half cycle begins and ending at the moment the first control signal indicates that the resonant current has changed sign; and reducing the triangular wave signal with a second slope in a second interval starting from a time when the first control signal indicates that the resonant current has changed sign and ending at a time when the second control signal indicates that the triangular wave signal has reached the reference threshold; The first slope has a positive value obtained by summing a negative first value and a positive second value, and the second slope has a negative value corresponding to the negative first value, wherein an absolute value of the first value is smaller than an absolute value of the second value, and the first value is proportional to the feedback signal.

18. A method comprising: Using a drive circuit of a resonant converter, driving a high-side switch of the resonant converter using a high-side gate drive signal; Using the driver circuit, driving a low-side switch of the resonant converter using a low-side gate drive signal; receiving, with the driver circuit, a resonant current signal indicative of a resonant current in a primary side of the resonant converter; receiving, with the driver circuit, a feedback signal based on an output signal of the resonant converter; generating a triangular wave integrated signal based on the feedback signal using an integrator circuit of the driver circuit; as well as The high-side gate driving signal and the low-side gate driving signal are generated based on the integrated signal and the resonant current signal using the driver circuit.

19. The method according to claim 18, comprising: driving the high-side electronic switch and the low-side electronic switch via the drive signal during consecutive first and second switching half cycles, wherein each of the first and second switching half cycles ends when the triangular wave integrated signal has reached a reference threshold; opening the low-side electronic switch once the first switching half-cycle begins, and closing the high-side electronic switch after a first delay; as well as Once the second switching half cycle begins, the high-side electronic switch is opened, and after a second delay the low-side electronic switch is closed.

20. The method according to claim 19, comprising: The triangular wave integral signal is generated in each of the first switching half cycle and the second switching half cycle by: In a first interval starting from the moment when the corresponding half cycle starts and ending at the moment when the resonant current changes its sign, increasing the triangular wave integrated signal with a first slope; as well as In a second interval starting from the moment when the resonant current changes its sign and ending at the moment when the triangular wave integrated signal reaches the reference threshold, reducing the triangular wave signal with a second slope; The first slope has a positive value obtained by summing a negative first value and a positive second value, and the second slope has a negative value corresponding to the negative first value, wherein an absolute value of the first value is smaller than an absolute value of the second value, and the first value is proportional to the feedback signal.

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