Power supply control circuit and method
By using single control signals and delay devices in the power control circuit, simplified control and stable management of the power circuit are achieved, and the resource occupation and complexity problems caused by multi-signal control are solved. It is suitable for cascading multi-device use, reducing the Cost and design difficulty.
Patent Information
- Application Number
- CN202411023451.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-29
- Publication Date
- 2024-12-17
AI Technical Summary
In the prior art, the use of multi-signal control power on and power down results in many system resources and complex control. Especially when multi-device or multi-load cascade use, the design difficulty increases, limiting the development of switching power supply circuits.
By setting a first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch and a second switch, the power-off of the power circuit is controlled by using a single control signal, and the power-off of the power supply circuit is realized. The controllable slow start of the power supply and the management of capacitor residual voltage will avoid short circuits and device damage.
It saves system resources, simplifies control logic, reduces costs, solves the resource occupation and complexity problems caused by multi-signal control, and ensures the stability and safety of the power supply when used in cascading multiple devices.
Smart Images
Figure CN119154656A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power supply circuits, and in particular to a power supply control circuit and method. Background Art
[0002] The switching power supply circuit is a relatively complex circuit. If the circuit problem is not handled properly, it is easy to cause a fire. The switching power supply uses electronic switching devices (such as transistors, field effect tubes, thyristors, etc.) to control the circuit to make the electronic switching devices "on" and "off" continuously, so that the electronic switching devices can adjust the input voltage by pulses, thereby realizing voltage conversion and adjustable and regulated output voltage. In the coordinated work of multiple devices in the switching power supply circuit, the power supply and power-off timing are required; the timing is set based on communication requirements, safety requirements, etc.; in terms of power supply and power-off discharge, the technical solution adopted in the prior art is: two or more control signals are led out by the processor or controller to control the power supply and power-off discharge of the power supply respectively, which leads to the need to program the delay control of two or more signals; and this method of using multiple control signals requires more system resources and complex design; for example, more control pins need to be set on the system chip, which increases the difficulty of chip design and layout; especially when multiple devices or multiple loads are used in cascade, the control is more complicated, which limits the development of the switching power supply circuit.
[0003] In view of this, a control solution with fewer system control signals and better design layout is needed to solve the problem that the prior art uses multiple signals to control power on and off, resulting in more system resources and complex control. Summary of the invention
[0004] The object of the present invention is to provide a power control circuit and method for solving the problem in the prior art that multiple signals are used to control power on and off, resulting in a large number of system resources required and complex control.
[0005] In order to achieve the above object, the present invention provides the following technical solutions:
[0006] In a first aspect, the present invention provides a power supply control circuit, which may include:
[0007] A first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch, and a second switch;
[0008] One end of the first level conversion device is connected to the control signal end, and the other end is connected to the first delay device; the other end of the first delay device is connected to the first end of the first switch, the second end of the first switch is connected to the positive electrode of the power supply, the third end of the first switch is connected to the first end of the load, and the second end of the load is connected to the negative electrode of the power supply; wherein the control signal end is used to input a control signal, and the control signal is a single control signal;
[0009] One end of the second level conversion device is connected to the control signal end, and the other end is connected to the second delay device; the other end of the second delay device is connected to the first end of the second switch, the second end of the second switch is connected to the positive electrode of the power supply, and the third end of the second switch is connected to the negative electrode of the power supply.
[0010] In a second aspect, the present invention provides a power control method, which is applied to a power control circuit, wherein the circuit at least includes a first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch, and a second switch; the method may include:
[0011] The first level conversion device and the second level conversion device respectively obtain a control signal; the control signal is a single control signal;
[0012] When the control signal is at a high level, the first switch is controlled to be turned on according to a first preset time, and the second switch is controlled to be turned off according to a second preset time; the first preset time is greater than the second preset time;
[0013] When the control signal is at a low level, the first switch is controlled to be closed according to the second preset time, and the second switch is controlled to be opened according to the first preset time.
[0014] Compared with the prior art, the present invention provides a power control circuit, which is provided by setting a first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch and a second switch. One end of the first level conversion device is connected to the control signal end, and the other end is connected to the first delay device, the other end of the first delay device is connected to the first end of the first switch, the second end of the first switch is connected to the positive pole of the power supply, the third end of the first switch is connected to the first end of the load, and the second end of the load is connected to the negative pole of the power supply; wherein the control signal end is used to input the control signal, and the control signal is a single control signal; further, one end of the second level conversion device is connected to the control signal end, and the other end is connected to the second delay device; the other end of the second delay device is connected to the first end of the second switch, the second end of the second switch is connected to the positive pole of the power supply, and the third end of the second switch is connected to the negative pole of the power supply; based on this, it is realized that a single control signal can be used to control the opening and power-off of the power supply circuit, which saves system resources and is simple to control, and solves the problem that the prior art needs to configure an additional processor to output multiple control signals and increase the number of chip control signal pins, resulting in more system resources and complex control. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0016] Figure 1 It is a schematic diagram of the structure of a dual control signal control circuit in the prior art;
[0017] Figure 2 A schematic diagram of the main framework structure of a power supply control circuit provided by the present invention;
[0018] Figure 3 A schematic diagram of a circuit structure corresponding to the main framework structure of a power supply control circuit provided by the present invention;
[0019] Figure 4 A first structural schematic diagram of a power supply control circuit provided by the present invention;
[0020] Figure 5 A schematic diagram of a power supply process of a power control circuit provided by the present invention;
[0021] Figure 6 A schematic diagram of a power-off process of a power control circuit provided by the present invention;
[0022] Figure 7 A power supply control circuit provided by the present invention is applied to a power supply of a nozzle and a waveform power supply of an inkjet printer;
[0023] Figure 8 A power supply control circuit provided by the present invention is applied to a power supply of a nozzle and a waveform power supply of an inkjet printer;
[0024] Fig. 9 A schematic diagram of the main flow of a power supply control method provided by the present invention.
[0025] Reference numerals: 100 - first level conversion device, 200 - second level conversion device, 300 - first delay device, 400 - second delay device, 500 - first switch, 600 - second switch, 700 - load, 800 - capacitor component. DETAILED DESCRIPTION
[0026] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.
[0027] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.
[0028] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.
[0029] In the power control circuit, multiple devices work together, requiring power supply and power-off timing; the timing is based on communication requirements, safety, etc. For power supply and power-off discharge, the existing technology solution is that the processor or controller leads to multiple control signals to control the power supply and power-off discharge respectively. Please refer to Figure 1 , Figure 1 It is a schematic diagram of the structure of a dual control signal control circuit in the prior art; Figure 1 This circuit not only needs programming to realize the delay control of multiple signals, but also needs to occupy the number of pins of the control chip in the circuit, which results in that the circuit designed using the technical solution of the prior art requires more system resources and is complex to control under multiple loads.
[0030] In view of this, the present invention provides a power supply control circuit and method, which adopts a single control signal to control the power supply and power-off discharge respectively, saving system resources and simplifying the control; it effectively solves the problem that the prior art uses multiple signals to control the power on and off, which requires a lot of system resources and complex control.
[0031] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:
[0032] See also Figure 2 , Figure 2 A schematic diagram of the main framework structure of a power supply control circuit provided by the present invention.
[0033] exist Figure 2 In the embodiment, the voltage control circuit may include:
[0034] A first level conversion device 100 , a second level conversion device 200 , a first delay device 300 , a second delay device 400 , a first switch 500 , a second switch 600 and a load 700 .
[0035] One end of the first level conversion device 100 is connected to the control signal end, and the other end is connected to the first delay device 300; the other end of the first delay device 300 is connected to the first end of the first switch 500, the second end of the first switch 500 is connected to the positive electrode of the power supply, the third end of the first switch 500 is connected to the first end of the load 700, and the second end of the load 700 is connected to the negative electrode of the power supply; wherein the control signal end is used to input a control signal, and the control signal is a single control signal.
[0036] One end of the second level conversion device 200 is connected to the control signal end, and the other end is connected to the second delay device 400; the other end of the second delay device 400 is connected to the first end of the second switch 600, the second end of the second switch 600 is connected to the positive electrode of the power supply, and the third end of the second switch 600 is connected to the negative electrode of the power supply.
[0037] Based on this, the present invention provides a power control circuit, which adopts a single control signal to control the start and power off of the power supply circuit, realizes controllable slow start-up power-on to reduce the impact of surge current on devices, protects devices, and prevents damage to devices caused by residual voltage of capacitors; especially when multiple devices are used in cascade, fewer control pins are used, the control is simple, system resources are saved, and costs are reduced; it effectively solves the problem in the prior art that an additional processor is required to output multiple control signals and the number of chip control signal pins is increased, resulting in more system resources and complex control.
[0038] As an example, see Figure 3 to Figure 4 , Figure 3 A schematic diagram of a circuit structure corresponding to the main framework structure of a power supply control circuit provided by the present invention, Figure 4 A first structural schematic diagram of a power supply control circuit provided by the present invention; Figure 4 The first structural diagram shown is Figure 3 It corresponds to the circuit structure schematic diagram shown in .
[0039] exist Figure 3 In the embodiment, the first switch 500 is a P-type field effect transistor Q1, and the second switch 600 is a first N-type field effect transistor Q2.
[0040] Specifically, the gate of the P-type field effect transistor Q1 can be connected to the first delay device 300 , the source of the P-type field effect transistor Q1 can be connected to the positive electrode of the power supply, and the drain of the P-type field effect transistor Q1 can be connected to the first end of the load.
[0041] The gate of the first N-type field effect transistor Q2 is further connected to the second delay device 400, the drain of the first N-type field effect transistor Q2 is connected to the positive electrode of the power supply, and the source of the first N-type field effect transistor Q2 is connected to the negative electrode of the power supply. Of course, one end of the third resistor R3 can also be connected to the drain of the first N-type field effect transistor Q2, and the other end is connected to the positive electrode of the power supply, so that the third resistor R3 can limit the current of the circuit where the drain of the first N-type field effect transistor Q2 is located; that is, the third resistor R3 is a current limiting resistor, and its function is to limit the current of the circuit corresponding to the first N-type field effect transistor Q2.
[0042] Furthermore, a power control circuit provided by the present invention may also include a third resistor R3 and a capacitor component 800; the capacitor component 800 may include a second capacitor C2 and a third capacitor C3. The second capacitor C2 and the third capacitor C3 are connected in the same manner in the circuit; one end of the second capacitor C2 is connected to the positive electrode of the power supply, and the other end is connected to the negative electrode of the power supply; that is, the capacitor component 800 and the load 700 are connected in parallel between the positive electrode and the negative electrode of the power supply.
[0043] Based on this, the present invention adopts the above method to connect the P-type field effect transistor Q1, the first N-type field effect transistor Q2, the first delay device 300, the second delay device 400, the third resistor R3 and the capacitor component 800, so as to achieve: the slow opening of the P-type field effect transistor Q1 switch can reduce the impact of surge current on the device; the slow opening of the first N-type field effect transistor Q2 switch can ensure the power-off sequence, and avoid the residual voltage of the capacitor affecting other circuits after the power is cut off; the power-on and power-off sequence can be controlled, the control signal is small, and the system resources are saved.
[0044] It should be noted that Figure 3 The working modes and functions of the main components in the circuit shown in are shown in Table 1.
[0045] Table 1 is a statistical table of the working modes and functions of the main components in a power control circuit provided by the present invention.
[0046]
[0047] Specifically, the working mode during the power supply process is:
[0048] When the control signal changes from low level to high level, the second switch is disconnected (closed) first, and the first switch is slowly opened (conducted). This sequence prevents the first switch and the second switch from being opened at the same time to cause a short circuit; after the capacitor is charged, it continues to supply power to the load.
[0049] The working mode during power failure is:
[0050] When the control signal changes from high level to low level, the first switch is disconnected first and the second switch is slowly turned on. This sequence also prevents the first switch and the second switch from being turned on at the same time to cause a short circuit; the capacitor voltage is discharged through the second switch, ensuring that the power-off time is controllable.
[0051] Preferably, the first level conversion device 100 may include a second N-type field effect transistor Q3, a first resistor R1, and a fifth resistor R5. The gate of the second N-type field effect transistor Q3 is connected to the control signal input terminal, the source of the second N-type field effect transistor Q3 is connected to the negative electrode of the power supply, the drain of the second N-type field effect transistor Q3 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the positive electrode of the power supply; wherein the first resistor R1 and the fifth resistor R5 function as voltage divider protection. Based on this, the first level conversion device 100 can be used to realize logic level conversion, thereby controlling the circuit where the first switch 500 is located.
[0052] Preferably, the first delay device 300 may include a first diode D1, a fourth resistor R4 and a first capacitor C1. The anode of the first diode D1 is connected to the end of the first resistor R1 that is not connected to the anode of the power supply, and the cathode of the first diode D1 is connected to the gate of the P-type field effect transistor Q1; one end of the first capacitor C1 is connected to the gate of the P-type field effect transistor Q1, and the other end is connected to the anode of the power supply; one end of the fourth resistor R4 is connected to the anode of the first diode D1, and the other end is connected to the gate of the P-type field effect transistor Q1; wherein the function of the fourth resistor R4 is to extend the opening time. Based on this, the first delay device 300 can be used to slowly open the first switch 500 and quickly close the first switch 500.
[0053] Preferably, the second level conversion device 200 may include a third N-type field effect transistor Q4 and a second resistor R2. The gate of the third N-type field effect transistor Q4 is connected to the control signal input terminal, and the source of the third N-type field effect transistor Q4 is connected to the negative electrode of the power supply; the drain of the third N-type field effect transistor Q4 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the positive electrode of the power supply; wherein the function of the second resistor R2 is voltage division protection. Based on this, the second level conversion device 200 can be used to realize logic level conversion, thereby controlling the circuit where the second switch 600 is located.
[0054] Preferably, the second delay device 400 may include: a second diode D2, a sixth resistor R6 and a fourth capacitor C4. The cathode of the second diode D2 is connected to the end of the second resistor R2 that is not connected to the positive electrode of the power supply, and the anode of the second diode D2 is connected to the gate of the first N-type field effect transistor Q2; one end of the sixth resistor R6 is connected to the cathode of the second diode D2, and the other end is connected to the anode of the second diode D2; one end of the fourth capacitor C4 is connected to the gate of the first N-type field effect transistor Q2, and the other end is connected to the source of the first N-type field effect transistor Q2; wherein the function of the sixth resistor R6 is to extend the opening time. Based on this, the second delay device 400 can be used to slowly open the second switch 600 and quickly close the second switch 600.
[0055] Preferably, a power control circuit provided by the present invention may also include a third diode D3, and the function of the third diode D3 is to stabilize the voltage; the positive electrode of the third diode D3 is connected to the source of the first N-type field effect transistor, and the negative electrode of the third diode D3 is connected to the drain of the third N-type field effect transistor; thereby, the second resistor R2 and the third diode D3 can be used to ensure that the first N-type field effect transistor Q2 can be turned on, so as to ensure the timing of the dropout and avoid damage to the device caused by the residual pressure of the capacitor component.
[0056] It should be noted that the time requirements for slow opening and fast closing can be adjusted according to the actual circuit, as long as the opening and closing times of the first switch and the second switch are staggered; in the present invention, the slow opening time can be set to be greater than 3ms, and the fast closing time can be set to 1ms.
[0057] The working principle of a power control circuit provided in an embodiment of the present invention is: when a single control signal is logic 0 at the beginning, at this time, Q1, Q2, and Q3 are all in a closed state.
[0058] When the control power circuit is turned on and powered on: the single control signal becomes logic 1, and the two NMOSs Q3 and Q4 are turned on at the same time. After Q4 is turned on, D2 quickly locks Q2, and Q2 is in the off state. Among them, after Q3 is turned on, the voltage division of resistors R1 and R5 ensures that Q1 is turned on. Due to the existence of R4 and C1, Q1 is slowly turned on and charges capacitors C2 and C3. After that, each device maintains the current state and continues to operate.
[0059] When the control power circuit is disconnected and powered off: the single control signal becomes logic 0, and the two NMOS tubes Q3 and Q4 are turned off at the same time; after Q3 is turned off, D1 makes Q1 turn off quickly; after Q4 is turned off, capacitors C2 and C3 still have voltage, R2 and D3 ensure that Q2 can be turned on, R6 and C4 make Q2 turn on slowly, and the voltage in C2 and C3 is discharged through R3 and Q2, ensuring the shutdown timing and avoiding damage to the device caused by the residual pressure of C2 and C3.
[0060] It should be noted that the first switch Q1 is PMOS, the second switch Q2 is NMOS, and Q3 and Q4 are also NMOS; the NMOS conduction condition is that VGS is greater than or equal to VGS(th), and the PMOS conduction condition is that VGS is less than or equal to VGS(th); in the figure, the VGS(th) of Q2, Q3, and Q4 is 1V~2V, and the VGS(th) of Q1 is -2V~-4V; logic 0: control signal = 0V, logic 1: control signal = 3.3V; generally, the control signal is sent by the main control unit, and the level is 3.3V or 5V; the power supply voltage range is relatively wide, generally 5-110VDC.
[0061] For example, the single control signal S1 is logic 0 at the beginning. At this time, VGS of Q3 and Q4 = 0V, so Q3 and Q4 are in the off state. Q3 is turned off, so Q1's VGS = 0V, so it is also turned off.
[0062] When powered on, the single control signal S1 becomes logic 1, and the VGS of Q3 and Q4 is 3.3V, so Q3 and Q4 meet the conduction conditions and the two tubes are turned on at the same time; after Q4 is turned on, D2 makes the VGS of Q2 = 0V, causing Q2 to be turned off; after Q3 is turned on, the voltage is divided by resistors R1 and R5, so that C1 is slowly discharged through R4, so that the VGS of Q1 is slowly reduced and Q1 is turned on, and the capacitors C2 and C3 are charged, and then each device maintains the current state and continues to operate.
[0063] When the power is off, the single control signal S1 becomes logic 0, and Q3 and Q4 are turned off at the same time; after Q3 is turned off, D1 makes Q1's VGS quickly become 0V, so Q1 is turned off; after Q4 is turned off, capacitors C2 and C3 still have voltage, and R2 and D3 (D3 is a voltage regulator) divide the voltage to ensure that Q2 can be turned on. Since C4 needs to be charged through R6, Q2's VGS rises slowly, so Q2 turns on slowly; the voltage in C2 and C3 is discharged through R3 and Q2, ensuring the shutdown timing and avoiding device damage caused by residual voltage of C2 and C3.
[0064] For details, please refer to Figures 5 and 6 , Figure 5 A schematic diagram of a power supply process of a power control circuit provided by the present invention; Figure 6 A schematic diagram of a power-off process of a power control circuit provided by the present invention.
[0065] like Figure 5 The power supply process of the circuit shown: when the control signal changes from low level to high level, switch 2 is disconnected first, and switch 1 is slowly opened. This sequence prevents switch 1 and switch 2 from being opened at the same time and causing a short circuit; after the capacitor is charged, it continues to supply power to the load, and the arrow indicates the direction of the current.
[0066] like Figure 6 The power-off process of the circuit shown: when the control signal changes from high level to low level, switch 1 is disconnected first and switch 2 is slowly opened. This sequence also prevents switch 1 and switch 2 from being opened at the same time and causing a short circuit; the capacitor voltage is discharged through switch 2 to ensure that the power-off time is controllable; the arrow indicates the direction of the discharge current.
[0067] In summary, the power control circuit provided by the present invention can at least achieve:
[0068] 1. Connecting in series in the circuit can realize multi-level power supply.
[0069] 2. It can be used in circuits that require fast power on and off, with a power on and off time interval of 1s or even shorter.
[0070] 3. It can avoid the residual voltage in the circuit before power-on, which may cause the main control chip to be unable to reset and cause abnormal operation.
[0071] Based on this, the present invention realizes the use of a single control signal to control the start and power off of the power supply circuit, saving system resources and simplifying control, solving the problem in the prior art that an additional processor is required to output multiple control signals and the number of chip control signal pins is increased, resulting in a large number of system resources and complex control; at the same time, it can also be connected in series in the circuit to realize multi-level power supply, and can be used in circuits that require fast power on and off, with a power on and off time interval of 1s or even shorter, and can also avoid the existence of residual pressure in the circuit before power-on, which causes the main control chip to be unable to be reset and abnormal operation to occur.
[0072] As a more specific example: A power control circuit provided by the present invention can be applied to an inkjet printer, and a single control signal is used to control the opening and power-off of the power circuit, so that when the inkjet printer nozzle is powered on, the logic signal power supply is supplied before the waveform drive power supply; when the power is off, the logic signal power supply lags behind the waveform drive power supply.
[0073] A power control circuit provided by the present invention is applied to the nozzle board of an inkjet printer, the positive pole of the logic signal power supply is connected to VCC, and the negative pole is grounded, so as to provide a suitable power supply for the nozzle board of the printer and power the processing unit of the nozzle; the waveform driving power supply is further connected in parallel with the load end; based on this, the power control circuit provided by the present invention can realize the power-on timing set for the nozzle of the inkjet printer. For example, during the power-on process: the nozzle power supply (nozzle logic signal power supply) can be powered on first, and after the interval preset power-on timing, the waveform power supply can be powered on; during the power-off process: the waveform power supply can be powered off first, and after the interval preset power-off timing, the nozzle power supply can be powered off; wherein, the interval preset power-on timing and the interval preset power-off timing can both be greater than or equal to 20 microseconds, and the timing during the power-off and power-on process is greater than or equal to 0 microseconds.
[0074] Based on this, a power control circuit provided by the present invention is applied to an inkjet printer. When power is turned on, the first switch is slowly opened, and the nozzle power supply is powered on before the waveform power supply, thereby avoiding the impact of surge current that may exist when the nozzle plate powers on the nozzle on the components in the nozzle, reducing the risk of damage to the components in the nozzle; when power is turned off, the second switch is slowly opened, and the waveform power supply is powered off before the nozzle power supply, thereby utilizing the first N-type field effect transistor to eliminate the residual pressure in the capacitor of the nozzle plate, avoiding the risk of damage to the nozzle caused by the residual pressure of the capacitor after the waveform power supply is powered off first; thereby meeting the timing requirements of the inkjet printer nozzle for power supply.
[0075] As an example, see Figures 7 and 8 , Figure 7 A power supply control circuit provided by the present invention is applied to the power supply of the nozzle and the waveform power supply of the inkjet printer. Figure 8 A power control circuit provided by the present invention is applied to a power failure timing diagram of a nozzle power supply and a waveform power supply of an inkjet printer.
[0076] exist Figure 7 In the graph, the horizontal axis represents time in microseconds, and the vertical axis represents voltage in V. The curve represents the change timing curve of the nozzle power supply. Represents the changing timing curve of the waveform power supply; Figure 7 It can be obtained that the power-on timing of the nozzle power supply and the waveform power supply differs by 20 microseconds. For example, if the nozzle power supply is fully powered on at the 20th microsecond, the waveform power supply starts to power on slowly at the 40th microsecond. The time for the nozzle power supply and the waveform power supply to rise from 0V to the working voltage is greater than or equal to 0 microseconds.
[0077] exist Figure 8 In the graph, the horizontal axis represents time in microseconds, and the vertical axis represents voltage in V. The curve represents the change timing curve of the nozzle power supply. Represents the changing timing curve of the waveform power supply; Figure 8 It can be obtained that the power-off timing of the nozzle power supply and the waveform power supply differs by 20 microseconds. For example, if the waveform power supply is completely disconnected at the 30th microsecond, the nozzle power supply starts to disconnect slowly at the 50th microsecond. The time for the nozzle power supply and the waveform power supply to drop from the operating voltage to 0V is greater than or equal to 0 microsecond.
[0078] It should be noted that the correspondence between the working voltage levels of the nozzle power supply and the waveform power supply can be set according to the printer in which the power supply control circuit is actually applied, and can be a correspondence greater than or equal to n times; the power-off timing of the nozzle power supply and the waveform power supply can also be set according to the printer in which the power supply control circuit is actually applied, and can be an interval timing greater than or equal to 20 microseconds; the present invention is not limited to the above specific numerical values.
[0079] In a second aspect, the present invention provides a power supply control method, see Fig. 9 , Fig. 9 A schematic diagram of the main flow of a power supply control method provided by the present invention.
[0080] exist Fig. 9In the method, the method can be applied to a power control circuit disclosed in the first aspect of the embodiment of the present invention; the power control circuit includes at least a first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch, and a second switch.
[0081] Methods may include:
[0082] Step 910: Utilize the first level conversion device and the second level conversion device to respectively obtain control signals; the control signal is a single control signal.
[0083] Step 920: When the control signal is at a high level, based on the first level conversion device and the first delay device, the first switch is controlled to be delayed to be turned on according to the first preset time, and based on the second level conversion device and the second delay device, the second switch is controlled to be delayed to be turned off according to the second preset time; the first preset time is greater than the second preset time.
[0084] Step 930: When the control signal is at a low level, based on the first level conversion device and the first delay device, the first switch is controlled to be delayed closed according to the second preset time, and based on the second level conversion device and the second delay device, the second switch is controlled to be delayed opened according to the first preset time.
[0085] In step 910 to step 930, the first level conversion device and the second level conversion device both obtain a single control signal sent by the control unit. Based on the single control signal, when the control signal is at a high level, the first switch can be controlled to be delayed to open according to the first preset time, and the second switch can be controlled to be delayed to close according to the second preset time; since the first preset time is greater than the second preset time, the first switch can be slowly opened and the second switch can be quickly closed; when the control signal is at a low level, the first switch is controlled to be delayed to close according to the second preset time, and the second switch is controlled to be delayed to open according to the first preset time; wherein, the corresponding operation time of fast and slow can be the time described in the first aspect, the time of slow opening is greater than 3ms, and the time of fast closing is less than 1ms; thereby staggering the opening and closing operations of the first switch and the second switch to avoid short circuit.
[0086] Preferably, the first switch is a P-type field effect transistor, and the P-type field effect transistor is used to control the turning on and off of the power supply.
[0087] Preferably, the second switch is a first N-type field effect transistor, and the first N-type field effect transistor is used to discharge the residual voltage of the capacitor after the circuit is turned off, control the power-off timing, and protect the components in the circuit.
[0088] Specifically, the technical means for controlling the first switch to be slowly turned on and quickly turned off, and the technical means for controlling the second switch to be slowly turned on and quickly turned off are the same as the technical means described in the first aspect, and will not be repeated here.
[0089] Based on this, the present invention proposes a power control method, which can be applied to a power control circuit, the circuit at least comprising a first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch, and a second switch; the method obtains a single control signal by using the first level conversion device and the second level conversion device respectively; when the control signal is at a high level, based on the first level conversion device and the first delay device, the first switch is controlled to be delayed to be turned on according to a first preset time, and based on the second level conversion device and the second delay device, the second switch is controlled to be delayed to be turned off according to a second preset time; the first preset time is greater than the second preset time; when the control signal is at a low level, based on the first level conversion device and the first delay device, the first switch is controlled to be delayed to be turned off according to the second preset time, and based on the second level conversion device and the second delay device, the second switch is controlled to be delayed to be turned on according to the first preset time; thereby, a single control signal can be used to control the start and power-off of the power circuit, saving system resources and simplifying the control, and solving the problem in the prior art that an additional processor needs to be configured to output multiple control signals and the number of chip control signal pins is increased, resulting in a large number of system resources and complex control.
[0090] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0091] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.
Claims
1. A power control circuit, characterized in that: include: A first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch, and a second switch; One end of the first level conversion device is connected to the control signal end, and the other end is connected to the first delay device; the other end of the first delay device is connected to the first end of the first switch, the second end of the first switch is connected to the positive electrode of the power supply, the third end of the first switch is connected to the first end of the load, and the second end of the load is connected to the negative electrode of the power supply; wherein the control signal end is used to input a control signal, and the control signal is a single control signal; One end of the second level conversion device is connected to the control signal end, and the other end is connected to the second delay device; the other end of the second delay device is connected to the first end of the second switch, the second end of the second switch is connected to the positive electrode of the power supply, and the third end of the second switch is connected to the negative electrode of the power supply.
2. The circuit according to claim 1, characterized in that The first switch is a P-type field effect transistor, and the second switch is a first N-type field effect transistor; The gate of the P-type field effect transistor is connected to the first delay device, the source of the P-type field effect transistor is connected to the positive electrode of the power supply, and the drain of the P-type field effect transistor is connected to the first end of the load; The gate of the first N-type field effect transistor is connected to the second delay device, the drain of the first N-type field effect transistor is connected to the positive electrode of the power supply, and the source of the first N-type field effect transistor is connected to the negative electrode of the power supply.
3. The circuit according to claim 2, characterized in that The first level conversion device includes a second N-type field effect transistor, a first resistor and a fifth resistor; The gate of the second N-type field effect transistor is connected to the control signal input end, the source of the second N-type field effect transistor is connected to the negative electrode of the power supply, the drain of the second N-type field effect transistor is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the positive electrode of the power supply.
4. The circuit according to claim 3, characterized in that The first delay device includes a first diode, a fourth resistor and a first capacitor; The anode of the first diode is connected to the end of the first resistor that is not connected to the positive electrode of the power supply, and the cathode of the first diode is connected to the gate of the P-type field effect transistor; one end of the first capacitor is connected to the gate of the P-type field effect transistor, and the other end is connected to the positive electrode of the power supply; one end of the fourth resistor is connected to the anode of the first diode, and the other end is connected to the gate of the P-type field effect transistor.
5. The circuit according to claim 2, characterized in that The second level conversion device includes a third N-type field effect transistor and a second resistor; The gate of the third N-type field effect transistor is connected to the control signal input end, and the source of the third N-type field effect transistor is connected to the negative electrode of the power supply; the drain of the third N-type field effect transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the positive electrode of the power supply.
6. The circuit according to claim 5, characterized in that The second delay device includes: a second diode, a sixth resistor and a fourth capacitor; The cathode of the second diode is connected to the end of the second resistor that is not connected to the positive electrode of the power supply, and the anode of the second diode is connected to the gate of the first N-type field effect transistor; one end of the sixth resistor is connected to the cathode of the second diode, and the other end is connected to the anode of the second diode; one end of the fourth capacitor is connected to the gate of the first N-type field effect transistor, and the other end is connected to the source of the first N-type field effect transistor.
7. The circuit according to claim 2, characterized in that The circuit also includes a third resistor and a capacitor component; One end of the third resistor is connected to the drain of the first N-type field effect transistor, and the other end is connected to the positive electrode of the power supply; The capacitor assembly includes a second capacitor and a third capacitor, and the second capacitor and the third capacitor are connected in the same manner in the circuit; One end of the second capacitor is connected to the positive electrode of the power supply, and the other end is connected to the negative electrode of the power supply.
8. A power supply control method, characterized in that: The method is applied to a power supply control circuit, the circuit at least comprising a first level conversion device, a second level conversion device, a first delay device, a second delay device, a first switch, and a second switch; the method comprises: The first level conversion device and the second level conversion device are used to obtain control signals respectively; the control signal is a single control signal; When the control signal is at a high level, the first switch is controlled to be turned on with a delay according to a first preset time based on the first level conversion device and the first delay device, and the second switch is controlled to be turned off with a delay according to a second preset time based on the second level conversion device and the second delay device; the first preset time is greater than the second preset time; When the control signal is at a low level, based on the first level conversion device and the first delay device, the first switch is controlled to delay closing according to the second preset time, and based on the second level conversion device and the second delay device, the second switch is controlled to delay opening according to the first preset time.
9. The method according to claim 8, characterized in that The first switch is a P-type field effect transistor, and the P-type field effect transistor is used to control the on and off of the power supply.
10. The method according to claim 8, characterized in that The second switch is a first N-type field effect transistor, and the first N-type field effect transistor is used to discharge the residual voltage of the capacitor after the circuit is turned off, control the power-off timing, and protect the components in the circuit.