Phase difference detection method and device for sampled data
By determining the phase difference between the source synchronization interface clock and data in the FPGA chip and performing phase adjustment, the reception failure caused by the phase difference between the clock and the sampled data is solved, and the success rate of data reception is improved.
Patent Information
- Application Number
- CN202411131611.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2024-12-17
AI Technical Summary
In the field programmable logic gate array (FPGA) chip, during the time sequence convergence verification of the source synchronization interface, there is an error in the phase difference between the clock and the sampled data, resulting in the problem of failure to receive data.
By determining the first phase difference between the source synchronization interface clock and the local preset phase clock and the second phase difference between the source synchronization interface data and the local preset phase clock, the target phase difference is calculated and the phase of the receiving phase lock loop is adjusted according to the phase difference. , to achieve phase synchronization of clock and data.
Improves the success rate of data received by the source synchronization interface, ensuring accurate synchronization and reception of clocks and data.
Smart Images
Figure CN119154870A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of integrated circuits, and in particular, relates to a method and device for detecting a phase difference in sampled data. Background Art
[0002] At present, when performing source synchronous interface timing closure verification inside a Field Programmable Gate Array (FPGA) chip, there is a phenomenon that the phase difference between the clock and sampled data of the source synchronous interface in the timing report calculated by the timing analysis model is different from the phase difference between the clock and sampled data of the actual source synchronous interface, so that even if the source synchronous interface timing converges, the source synchronous interface may fail to receive data.
[0003] Therefore, there is an urgent need to provide a technical solution for detecting the phase difference between the clock and sampled data of a source synchronous interface, so as to adjust the phase of the source synchronous interface receiving phase locked loop (PLL) according to the phase difference between the clock and sampled data of the source synchronous interface, so as to improve the success rate of data reception by the source synchronous interface. Summary of the invention
[0004] In view of this, an embodiment of the present application provides a phase difference detection method and device for sampling data to overcome the above problems of the prior art.
[0005] In a first aspect, an embodiment of the present application provides a phase difference detection method for sampling data, including: determining a first phase difference between a source synchronous interface clock input by a source synchronous interface and a local preset phase clock; determining a second phase difference between a source synchronous interface data input by the source synchronous interface and the local preset phase clock; and determining a target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference.
[0006] Among them, in some optional embodiments, determining the first phase difference between the source synchronous interface clock input by the source synchronous interface and the local preset phase clock includes: sampling the local clock counter based on the source synchronous interface clock to obtain a first sampling value; and determining the first phase difference between the source synchronous interface clock and the local preset phase clock based on the first sampling value.
[0007] Among them, in some optional embodiments, determining the first phase difference between the source synchronous interface clock and the local preset phase clock based on the first sampling value includes: processing the first sampling value across the clock domain to the clock domain of the local preset phase clock to obtain a second sampling value; searching the first local clock phase difference table according to the second sampling value to obtain the first phase difference, and the first local clock phase difference table is used to characterize the corresponding relationship between the second sampling value and the phase difference of the source synchronous interface clock associated with the second sampling value relative to the local preset phase clock.
[0008] Among them, in some optional embodiments, sampling the local clock counter based on the source synchronous interface clock to obtain a first sampling value includes: driving the local clock counter to count based on the local clock to obtain a count value; sampling the count value based on the source synchronous interface clock to obtain the first sampling value.
[0009] Among them, in some optional embodiments, determining the second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock includes: sampling the source synchronous interface data based on the local clock to obtain a third sampling value; and determining the second phase difference between the source synchronous interface data and the local preset phase clock based on the third sampling value.
[0010] Among them, in some optional embodiments, determining the second phase difference between the source synchronous interface data and the local preset phase clock based on the third sampling value includes: processing the third sampling value across clock domains to the clock domain of the local preset phase clock to obtain a fourth sampling value; searching a second local clock phase difference table based on the fourth sampling value to obtain the second phase difference, wherein the second local clock phase difference table is used to characterize the correspondence between the fourth sampling value and the phase difference of the source synchronous interface data associated with the fourth sampling value relative to the local preset phase clock.
[0011] Among them, in some optional embodiments, the phase difference detection method also includes: determining the compensation phase of the source synchronous interface receiving phase-locked loop according to the target phase difference; sending the compensation phase to the source synchronous interface receiving phase-locked loop, so that the source synchronous interface receiving phase-locked loop performs phase compensation on the source synchronous interface receiving clock according to the compensation phase.
[0012] In a second aspect, an embodiment of the present application provides a phase difference detection device for sampling data, the phase difference detection device comprising a first determination module, a second determination module and a third determination module. The first determination module is used to determine a first phase difference between a source synchronous interface clock input by a source synchronous interface and a local preset phase clock; the second determination module is used to determine a second phase difference between source synchronous interface data input by the source synchronous interface and the local preset phase clock; the third determination module is used to determine a target phase difference between the source synchronous interface clock and the source synchronous interface data according to the first phase difference and the second phase difference.
[0013] In a third aspect, an embodiment of the present application provides an FPGA chip, comprising a memory; one or more processors coupled to the memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the phase difference detection method for sampling data provided in the first aspect above.
[0014] In some optional embodiments, the FPGA chip also includes a memory, and the memory is connected to the processor via a circuit or wire.
[0015] In some optional embodiments, the FPGA chip also includes a communication interface.
[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a memory, an FPGA chip, and a computer program stored in the memory and executable on the FPGA chip. When the FPGA chip executes the computer program, the electronic device executes the phase difference detection method for sampling data provided in the first aspect above.
[0017] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a program code is stored. The program code can be called by a processor to execute the phase difference detection method of sampling data provided in the first aspect above.
[0018] In a sixth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on a computer device, the computer device executes the phase difference detection method for sampling data provided in the first aspect above.
[0019] The solution provided by the present application realizes synchronizing the phases of the source synchronous interface clock and the source synchronous interface data to the local clock phase by determining a first phase difference between a source synchronous interface clock input by the source synchronous interface and a local preset phase clock, and determining a second phase difference between a source synchronous interface data input by the source synchronous interface and the local preset phase clock, and determining a target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference, thereby determining the phase difference between the source synchronous interface clock and the source synchronous interface data based on the synchronized phase, so as to adjust the phase of the source synchronous interface receiving phase-locked loop according to the phase difference between the source synchronous interface clock and the source synchronous interface data, which is beneficial to improving the success rate of the source synchronous interface receiving data. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 A schematic flow chart of a phase difference detection method for sampling data provided in an embodiment of the present application is shown.
[0022] Figure 2 A structural schematic diagram of an FPGA chip in the phase difference detection method for sampling data provided in an embodiment of the present application is shown.
[0023] Figure 3 A schematic diagram of a scenario of a sampling timing diagram in a phase difference detection method for sampling data provided in an embodiment of the present application is shown.
[0024] Figure 4 Another schematic flow chart of a phase difference detection method for sampling data provided in an embodiment of the present application is shown.
[0025] Figure 5 A structural block diagram of a phase difference detection device for sampling data provided in an embodiment of the present application is shown.
[0026] Figure 6 A functional block diagram of the FPGA chip provided in an embodiment of the present application is shown.
[0027] Figure 7 A computer-readable storage medium provided in an embodiment of the present application for storing or carrying a program code for implementing a phase difference detection method for sampling data provided in an embodiment of the present application is shown.
[0028] Figure 8A computer program product provided in an embodiment of the present application and used for storing or carrying program codes for implementing a phase difference detection method for sampling data provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0029] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described below are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0030] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.
[0031] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.
[0032] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0033] As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.
[0034] In addition, in the description of the present application, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0035] At present, when performing source synchronous interface timing closure verification inside a Field Programmable Gate Array (FPGA) chip, there is a phenomenon that the phase difference between the clock and sampled data of the source synchronous interface in the timing report calculated by the timing analysis model is different from the phase difference between the clock and sampled data of the actual source synchronous interface, so that even if the source synchronous interface timing converges, the source synchronous interface may fail to receive data.
[0036] Therefore, there is an urgent need to provide a technical solution for detecting the phase difference between the clock and sampled data of a source synchronous interface, so as to adjust the phase of the source synchronous interface receiving phase locked loop (PLL) according to the phase difference between the clock and sampled data of the source synchronous interface, so as to improve the success rate of data reception by the source synchronous interface.
[0037] In response to the above problems, the phase difference detection method and device for sampling data provided in the embodiments of the present application realizes synchronization of the phases of the source synchronous interface clock and the source synchronous interface data to the local clock phase by determining the first phase difference between the source synchronous interface clock input by the source synchronous interface and the local preset phase clock, and determining the second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock, and determining the target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference, thereby determining the phase difference between the source synchronous interface clock and the source synchronous interface data based on the synchronized phase, so as to adjust the phase of the source synchronous interface receiving phase-locked loop according to the phase difference between the source synchronous interface clock and the source synchronous interface data, which is beneficial to improving the success rate of the source synchronous interface receiving data.
[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0039] See also Figure 1 , which shows a flow chart of a phase difference detection method for sampling data provided by an embodiment of the present application. In a specific embodiment, the phase difference detection method for sampling data can be applied to an FPGA chip. Figure 1 The process shown in FIG. 1 is described in detail. The phase difference detection method for sampling data may include the following steps S110 to S130.
[0040] Step S110: Determine a first phase difference between a source synchronous interface clock input by a source synchronous interface and a local preset phase clock.
[0041] In an embodiment of the present application, when the FPGA chip receives data through a source synchronous interface, a first phase difference between a source synchronous interface clock input by the source synchronous interface and a local preset phase clock can be determined.
[0042] Among them, the source synchronous interface input includes a source synchronous interface clock and a source synchronous interface data, etc. The preset phase of the local preset phase clock can be any phase between 0 phase and 360 phase. For example, the local preset phase clock can be any one of a local 0 phase clock, a local 45-degree phase clock, a local 90-degree phase clock, a local 135-degree phase clock, a local 180-degree phase clock, a local 225-degree phase clock, a local 270-degree phase clock, or a local 315-degree phase clock, etc. The type of the local preset phase clock is not limited here, and can be set according to actual needs.
[0043] The local preset phase clock may be a phase clock preset by a user, or a phase clock automatically generated by an FPGA chip according to a process of receiving data multiple times, etc., which is not limited here.
[0044] Specifically, when the FPGA chip receives data through a source synchronous interface, it can sample the local clock counter based on the source synchronous interface clock to obtain a first sampling value, and determine the first phase difference between the source synchronous interface clock and the local preset phase clock based on the first sampling value.
[0045] Regarding the process in which the above-mentioned FPGA chip samples the local clock counter based on the source synchronous interface clock to obtain a first sampling value, in some embodiments, the FPGA chip can drive the local clock counter to count based on the local clock to obtain a count value, and sample the count value based on the source synchronous interface clock to obtain a first sampling value.
[0046] The FPGA chip includes an internal PLL, the local clock can be generated based on the internal PLL, and the FPGA chip has a local clock counter pre-built in.
[0047] Regarding the process in which the above-mentioned FPGA chip determines the first phase difference between the source synchronous interface clock and the local preset phase clock based on the first sampling value, in some embodiments, the FPGA chip can process the first sampling value across the clock domain to the clock domain of the local preset phase clock to obtain the second sampling value, and search the first local clock phase difference table based on the second sampling value to obtain the first phase difference.
[0048] Among them, the FPGA chip can process the first sampling value across clock domains to the clock domain of the local preset phase clock based on an asynchronous first-in first-out queue (First Input First Output, FIFO) to obtain a second sampling value.
[0049] The first local clock phase difference table may be used to characterize the corresponding relationship between the second sampling value and the phase difference of the source synchronous interface clock associated with the second sampling value relative to the local preset phase clock.
[0050] For example, the local preset phase clock can be a local 0-phase clock, and the correspondence between the second sampling value and the phase difference of the source synchronous interface clock associated with the second sampling value relative to the local 0-phase clock can be as shown in Table 1, that is, the first local clock phase difference table, which shows the phase difference of the source synchronous interface clock associated with the second sampling value corresponding to different second sampling values relative to the local 0-phase clock.
[0051] Table 1
[0052]
[0053] It should be noted that, in Table 1, if the second sampling value is 8'b1111_1111, the first phase difference is 0 to 45 degrees, and if the second sampling value is 8'b1111_1110, the first phase difference is 315 to 360 degrees. The corresponding relationship between the second sampling value and the phase difference of the source synchronous interface clock associated with the second sampling value relative to the local 0-phase clock is not limited to that shown in Table 1.
[0054] In one application scenario, the local preset phase clock is a local 0-phase clock, and the FPGA chip has 8 built-in counters with a bit width of 1 bit. The internal PLL of the FPGA chip generates 8 local clocks with a frequency of 125 MHz and a phase interval of 45 degrees.
[0055] The FPGA chip can drive a local clock counter based on each local clock, so that each local clock counter counts continuously according to the switching rule of 0, 1, 0, 1... to obtain a clock count value. The FPGA chip samples each clock count value based on the source synchronous interface clock, and splices the values obtained by sampling the 8 clock count values into data with a bit width of 8 bits to obtain the first sampling value.
[0056] Based on the asynchronous FIFO, the 8-bit first sampling value is processed across the clock domain to the clock domain of the local 0-phase clock to obtain the second sampling value, and according to the second sampling value, the first local clock phase difference table shown in Table 1 is searched to obtain the first phase difference between the source synchronous interface clock and the local 0-phase clock.
[0057] Step S120: Determine a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock.
[0058] In an embodiment of the present application, the FPGA chip can sample the source synchronous interface data based on the local clock to obtain a third sampling value, and determine the second phase difference between the source synchronous interface data and the local preset phase clock based on the third sampling value.
[0059] Among them, a sampling register is set inside the FPGA chip. The FPGA chip samples the source synchronous interface data based on the local clock, locks the sampled data into the sampling register, and generates a third sampling value based on the sampling register.
[0060] Regarding the process in which the above-mentioned FPGA chip determines the second phase difference between the source synchronous interface data and the local preset phase clock based on the third sampling value, in some embodiments, the FPGA chip can process the third sampling value across the clock domain to the clock domain of the local preset phase clock to obtain a fourth sampling value, and search the second local clock phase difference table based on the fourth sampling value to obtain the second phase difference.
[0061] Among them, the FPGA chip can process the third sampling value across clock domains to the clock domain of the local preset phase clock based on the FIFO to obtain the fourth sampling value.
[0062] The second local clock phase difference table can be used for the correspondence between the fourth sampling value and the phase difference of the source synchronous interface data associated with the fourth sampling value relative to the local preset phase clock. For example, the local preset phase clock can be a local 0-phase clock, and the correspondence between the fourth sampling value and the phase difference of the source synchronous interface data associated with the fourth sampling value relative to the local 0-phase clock can be as shown in Table 2, that is, the second local clock phase difference table, which shows the phase difference of the source synchronous interface data associated with the fourth sampling value corresponding to different fourth sampling values relative to the local 0-phase clock.
[0063] Table 2
[0064]
[0065] It should be noted that, in Table 2, if the fourth sampling value is 8'b1000_0000, the second phase difference is 90 to 135 degrees, and if the fourth sampling value is 8'b0000_0111, the second phase difference is 225 to 270 degrees. The corresponding relationship between the fourth sampling value and the phase difference of the source synchronous interface data associated with the fourth sampling value relative to the local 0-phase clock is not limited to that shown in Table 2.
[0066] It should be noted that in the embodiment of the present application, there is no order between step S110 and step S120. The FPGA chip can also determine the first phase difference between the source synchronous interface clock input by the source synchronous interface and the local preset phase clock after determining the second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock. It will not be repeated here.
[0067] In one application scenario, such as Figure 2 As shown, the FPGA chip includes an internal PLL, a local clock counter group, a sampling data splicing module, a first sampling data clock domain synchronization module, a clock phase calculation module, a source synchronous data sampling register group, a second sampling data clock domain synchronization module and a data phase calculation module.
[0068] The internal PLL generates 8 local clocks with a frequency of 125MHz and a phase interval of 45 degrees according to the input clock signal clk, which are respectively recorded as clk125_0, clk125_45, clk125_90, clk125_135, clk125_180, clk125_225, clk125_270 and clk125_315.
[0069] The local clock counter group includes a first local clock counter (cnt0), a second local clock counter (cnt1), a third local clock counter (cnt2), a fourth local clock counter (cnt3), a fifth local clock counter (cnt4), a sixth local clock counter (cnt5), a seventh local clock counter (cnt6) and an eighth local clock counter (cnt7).
[0070] cnt0 is driven by clk125_0 and generates a first clock count value (cnt0_value). cnt1 is driven by clk125_45 and generates a second clock count value (cnt1_value). cnt2 is driven by clk125_90 and generates a third clock count value (cnt2_value). cnt3 is driven by clk125_135 and generates a fourth clock count value (cnt3_value). cnt4 is driven by clk125_180 and generates a fifth clock count value (cnt4_value). cnt5 is driven by clk125_225 and generates a sixth clock count value (cnt5_value). cnt6 is driven by clk125_270 and generates a seventh clock count value (cnt6_value). cnt7 is driven by clk125_315 and generates an eighth clock count value (cnt7_value).
[0071] The source synchronous interface clock (pi_clk) samples cnt0_value, cnt1_value, cnt2_value, cnt3_value, cnt4_value, cnt5_value, cnt6_value and cnt7_value respectively, and inputs the sampling results to the sampling data splicing module, so that the sampling data splicing module splices the sampling results into the first sampling value (pi_clk_sample[7:0]).
[0072] The first sampling data clock domain synchronization module processes pi_clk_sample[7:0] across clock domains to the clock domain of clk125_0 to obtain a second sampling value (pi_clk_sample_sync[7:0]).
[0073] The clock phase calculation module searches the first local clock phase difference table according to pi_clk_sample_sync[7:0] to obtain the first phase difference.
[0074] The source synchronous data sampling register group includes 8 sampling registers, which are recorded as reg0, reg1, reg2, reg3, reg4, reg5, reg6 and reg7. reg0, reg1, reg2, reg3, reg4, reg5, reg6 and reg7 are composed of a D flip-flop with a bit width of 1 bit. The D port of each flip-flop is used to receive the source synchronous interface data (pi_data) input by the source synchronous reception.
[0075] clk125_0 drives reg0, and performs data sampling on the source synchronous interface data received by reg0 to obtain a first data count value (reg0_value). clk125_45 drives reg1, and performs data sampling on the source synchronous interface data received by reg1 to obtain a second data count value (reg1_value). clk125_90 drives reg2, and performs data sampling on the source synchronous interface data received by reg2 to obtain a third data count value (reg2_value). clk125_135 drives reg3, and performs data sampling on the source synchronous interface data received by reg3 to obtain a fourth data count value (reg3_value). clk125_180 drives reg4, and performs data sampling on the source synchronous interface data received by reg4 to obtain a fifth data count value (reg4_value). clk125_225 drives reg5, and performs data sampling on the source synchronous interface data received by reg5 to obtain a sixth data count value (reg5_value). clk125_270 drives reg6 and samples the source synchronous interface data received by reg6 to obtain a seventh data count value (reg6_value). clk125_315 drives reg7 and samples the source synchronous interface data received by reg7 to obtain an eighth data count value (reg7_value).
[0076] The second sampling data clock domain synchronization module splices reg0_value, reg1_value, reg2_value, reg3_value, reg4_value, reg5_value, reg6_value and reg7_value into an 8-bit spliced data to obtain a third sampling value (pi_data_sample_sync[7:0]), and processes the third sampling value across the clock domain to the clock domain of clk125_0 to obtain a fourth sampling value (pi_date_sample_sync[7:0]).
[0077] The data phase calculation module searches the second local clock phase difference table according to pi_date_sample_sync[7:0] to obtain the second phase difference.
[0078] Among them, the timing diagram of the process of the source synchronous interface clock sampling the local clock, and the timing diagram of the process of the local clock sampling the source synchronous interface data, such as Figure 3 shown.
[0079] Step S130: Determine a target phase difference between the source synchronous interface clock and the source synchronous interface data according to the first phase difference and the second phase difference.
[0080] In an embodiment of the present application, the FPGA chip can calculate the target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference, thereby realizing the phase synchronization of the source synchronous interface clock and the source synchronous interface data to the local clock phase, and determining the phase difference between the source synchronous interface clock and the source synchronous interface data based on the synchronized phase, so as to adjust the phase of the source synchronous interface receiving phase-locked loop according to the phase difference between the source synchronous interface clock and the source synchronous interface data, which is beneficial to improving the success rate of the source synchronous interface receiving data.
[0081] The FPGA chip can calculate the phase difference between the first phase difference and the second phase difference to obtain the target phase difference. The upper limit of the target phase difference = the upper limit of the first phase difference - the upper limit of the second phase difference, and the lower limit of the target phase difference = the lower limit of the first phase difference - the lower limit of the second phase difference.
[0082] In one application scenario, the first phase difference can be 135 to 175 degrees, the second phase difference can be 55 to 80 degrees, 135 degrees - 55 degrees = 80 degrees can be calculated, and 80 degrees is used as the lower limit of the target phase difference, 175 degrees - 80 degrees = 95 degrees is calculated, and 95 degrees is used as the upper limit of the target phase difference, and the target phase difference is 80 to 95 degrees. The specific values of the first phase difference, the second phase difference and the target phase difference are not limited here, and can be set according to actual needs.
[0083] The solution provided in this embodiment synchronizes the phases of the source synchronous interface clock and the source synchronous interface data to the local clock phase by determining a first phase difference between the source synchronous interface clock input by the source synchronous interface and the local preset phase clock, and determining a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock, and determining a target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference, thereby achieving phase synchronization of the source synchronous interface clock and the source synchronous interface data to the local clock phase, and determining the phase difference between the source synchronous interface clock and the source synchronous interface data based on the synchronized phase, so as to adjust the phase of the source synchronous interface receiving phase-locked loop according to the phase difference between the source synchronous interface clock and the source synchronous interface data, which is beneficial to improving the success rate of the source synchronous interface receiving data.
[0084] See also Figure 4 , which shows a flow chart of a phase difference detection method for sampling data provided by another embodiment of the present application. In a specific embodiment, the phase difference detection method for sampling data can be applied to an FPGA chip. Figure 4 The process shown in FIG. 1 is described in detail, and the phase difference detection method for sampling data may include the following steps S210 to S250.
[0085] Step S210: Determine a first phase difference between a source synchronous interface clock input by a source synchronous interface and a local preset phase clock.
[0086] Step S220: Determine a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock.
[0087] Step S230: Determine a target phase difference between the source synchronous interface clock and the source synchronous interface data according to the first phase difference and the second phase difference.
[0088] In this embodiment, step S210, step S220 and step S230 may refer to the contents of the corresponding steps in the aforementioned embodiments, which will not be described in detail here.
[0089] Step S240: Determine the compensation phase of the source synchronous interface receiving phase-locked loop according to the target phase difference.
[0090] In this embodiment, after the FPGA chip determines the target phase difference between the source synchronous interface clock and the source synchronous interface data according to the first phase difference and the second phase difference, it can determine the compensation phase of the source synchronous interface receiving PLL according to the target phase difference.
[0091] Step S250: sending the compensation phase to the source synchronous interface receiving phase-locked loop, so that the source synchronous interface receiving phase-locked loop performs phase compensation on the source synchronous interface receiving clock according to the compensation phase.
[0092] In this embodiment, after the FPGA chip determines the compensation phase of the source synchronous interface receiving PLL according to the target phase difference, it can send the compensation phase to the source synchronous interface receiving PLL. The source synchronous interface receiving PLL receives and responds to the compensation phase, and performs phase compensation on the source synchronous interface receiving clock according to the compensation phase, thereby realizing phase compensation of the source synchronous interface receiving PLL according to the phase difference between the source synchronous interface clock and the source synchronous interface data, thereby improving the success rate of the source synchronous interface receiving data.
[0093] The solution provided in this embodiment determines a first phase difference between a source synchronous interface clock input by the source synchronous interface and a local preset phase clock, determines a second phase difference between a source synchronous interface data input by the source synchronous interface and the local preset phase clock, and determines a target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference, thereby compensating the phase of the source synchronous interface receiving PLL based on the phase difference between the source synchronous interface clock and the source synchronous interface data, thereby improving the success rate of the source synchronous interface receiving data.
[0094] See also Figure 5, which shows a phase difference detection device 300 for sampling data provided by an embodiment of the present application. The phase difference detection device 300 for sampling data can be applied to FPGA chips. The following takes FPGA chips as an example. Figure 5 The phase difference detection device 300 for sampling data shown in FIG. 3 is described in detail. The phase difference detection device 300 for sampling data may include a first determination module 310 , a second determination module 320 and a third determination module 330 .
[0095] The first determination module 310 can be used to determine the first phase difference between the source synchronous interface clock input by the source synchronous interface and the local preset phase clock; the second determination module 320 can be used to determine the second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock; the third determination module 330 can be used to determine the target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference.
[0096] In some implementations, the first determining module 310 may include a first sampling unit and a first determining unit.
[0097] The first sampling unit can be used to sample the local clock counter based on the source synchronous interface clock to obtain a first sampling value; the first determining unit can be used to determine a first phase difference between the source synchronous interface clock and the local preset phase clock according to the first sampling value.
[0098] In some implementations, the first determining unit may include a first processing subunit and a first searching subunit.
[0099] The first processing sub-unit can be used to process the first sampling value across the clock domain to the clock domain of the local preset phase clock to obtain a second sampling value; the first search sub-unit can be used to search the first local clock phase difference table according to the second sampling value to obtain a first phase difference, and the first local clock phase difference table can be used to characterize the corresponding relationship between the second sampling value and the phase difference of the source synchronous interface clock associated with the second sampling value relative to the local preset phase clock.
[0100] In some implementations, the first sampling unit may include a driving subunit and a sampling subunit.
[0101] The driving subunit can be used to drive the local clock counter to count based on the local clock to obtain a count value; the sampling subunit can be used to sample the count value based on the source synchronous interface clock to obtain a first sampling value.
[0102] In some implementations, the second determining module 320 may include a second sampling unit and a second determining unit.
[0103] The second sampling unit can be used to sample the source synchronous interface data based on the local clock to obtain a third sampling value; the second determination unit can be used to determine the second phase difference between the source synchronous interface data and the local preset phase clock according to the third sampling value.
[0104] In some implementations, the second determining unit may include a second processing subunit and a second searching subunit.
[0105] The second processing sub-unit can be used to process the third sampling value across the clock domain to the clock domain of the local preset phase clock to obtain a fourth sampling value; the second search sub-unit can be used to search the second local clock phase difference table according to the fourth sampling value to obtain a second phase difference, and the second local clock phase difference table can be used to characterize the correspondence between the fourth sampling value and the phase difference of the source synchronous interface data associated with the fourth sampling value relative to the local preset phase clock.
[0106] In some implementations, the phase difference detection device 300 for sampling data may further include a fourth determining module and a sending module.
[0107] The fourth determination module can be used to determine the compensation phase of the source synchronous interface receiving phase-locked loop according to the target phase difference; the sending module can be used to send the compensation phase to the source synchronous interface receiving phase-locked loop, so that the source synchronous interface receiving phase-locked loop performs phase compensation on the source synchronous interface receiving clock according to the compensation phase.
[0108] The solution provided in this embodiment synchronizes the phases of the source synchronous interface clock and the source synchronous interface data to the local clock phase by determining a first phase difference between the source synchronous interface clock input by the source synchronous interface and the local preset phase clock, and determining a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock, and determining a target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference, thereby achieving phase synchronization of the source synchronous interface clock and the source synchronous interface data to the local clock phase, and determining the phase difference between the source synchronous interface clock and the source synchronous interface data based on the synchronized phase, so as to adjust the phase of the source synchronous interface receiving phase-locked loop according to the phase difference between the source synchronous interface clock and the source synchronous interface data, which is beneficial to improving the success rate of the source synchronous interface receiving data.
[0109] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. Any processing method described in the method embodiment can be implemented by the corresponding processing module in the device embodiment, and will not be repeated one by one in the device embodiment.
[0110] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.
[0111] See also Figure 6 , which shows a functional block diagram of an FPGA chip 500 provided by an embodiment of the present application. The FPGA chip 500 may include one or more of the following components: a memory 510, a processor 520, and one or more applications, wherein the one or more applications may be stored in the memory 510 and configured to be executed by the one or more processors 520, and the one or more applications are configured to execute the method described in the aforementioned method embodiment.
[0112] The memory 510 may include a random access memory (RAM) or a read-only memory (Read-Only Memory). The memory 510 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 510 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as determining a first phase difference, determining a second phase difference, determining a target phase difference, sampling a local clock counter, obtaining a first sampling value, cross-clock domain processing, obtaining a second sampling value, searching a first local clock phase difference table, obtaining a first phase difference, driving a local clock counter, counting, obtaining a count value, sampling a count value, sampling source synchronous interface data, obtaining a third sampling value, obtaining a fourth sampling value, searching a second local clock phase difference table, determining a compensation phase, sending a compensation phase and phase compensation, etc.), instructions for implementing the following various method embodiments, etc. The storage data area can also store data created by the FPGA chip 500 during use (such as source synchronous interface input, source synchronous interface clock, local preset phase clock, first phase difference, source synchronous interface data, second phase difference, target phase difference, local clock counter, first sampling value, clock domain, second sampling value, first local clock phase difference table, correspondence, local clock, count value, third sampling value, fourth sampling value, source synchronous interface receiving phase-locked loop and compensation phase), etc.
[0113] The processor 520 may include one or more processing cores. The processor 520 uses various interfaces and lines to connect various parts of the entire FPGA chip 500, and executes various functions and processes data of the FPGA chip 500 by running or executing instructions, programs, code sets or instruction sets stored in the memory 510, and calling data stored in the memory 510. Optionally, the processor 520 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), programmable logic array (PLA), etc. The processor 520 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 520, but may be implemented separately through a communication chip.
[0114] Please refer to Figure 7 , which shows a structural block diagram of a computer-readable storage medium provided in an embodiment of the present application. The computer-readable storage medium 600 stores a program code 610, which can be called by a processor to execute the method described in the above method embodiment.
[0115] The computer readable storage medium 600 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer readable storage medium 600 includes a non-transitory computer-readable storage medium. The computer readable storage medium 600 has storage space for program code 610 that performs any method steps in the above method. These program codes can be read from or written to one or more computer program products. The program code 610 can be compressed, for example, in an appropriate form.
[0116] Please refer to Figure 8, which shows a structural block diagram of a computer program product 700 provided in an embodiment of the present application. The computer program product 700 includes a computer program / instruction 710, and the computer program / instruction 710 is stored in a computer-readable storage medium of a computer device. When the computer program product 700 is run on a computer device, a processor of the computer device reads the computer program / instruction 710 from the computer-readable storage medium, and the processor executes the computer program / instruction 710, so that the computer device performs the method described in the above method embodiment.
[0117] The solution provided in this embodiment synchronizes the phases of the source synchronous interface clock and the source synchronous interface data to the local clock phase by determining a first phase difference between the source synchronous interface clock input by the source synchronous interface and the local preset phase clock, and determining a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock, and determining a target phase difference between the source synchronous interface clock and the source synchronous interface data based on the first phase difference and the second phase difference, thereby achieving phase synchronization of the source synchronous interface clock and the source synchronous interface data to the local clock phase, and determining the phase difference between the source synchronous interface clock and the source synchronous interface data based on the synchronized phase, so as to adjust the phase of the source synchronous interface receiving phase-locked loop according to the phase difference between the source synchronous interface clock and the source synchronous interface data, which is beneficial to improving the success rate of the source synchronous interface receiving data.
[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A phase difference detection method for sampling data, characterized in that: include: Determine a first phase difference between a source synchronous interface clock input by the source synchronous interface and a local preset phase clock; Determine a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock; A target phase difference between the source synchronous interface clock and the source synchronous interface data is determined according to the first phase difference and the second phase difference.
2. The phase difference detection method according to claim 1, characterized in that: The step of determining a first phase difference between a source synchronous interface clock input by the source synchronous interface and a local preset phase clock comprises: Sampling a local clock counter based on the source synchronous interface clock to obtain a first sampling value; The first phase difference between the source synchronous interface clock and the local preset phase clock is determined according to the first sampling value.
3. The phase difference detection method according to claim 2, characterized in that: The determining, according to the first sampling value, the first phase difference between the source synchronous interface clock and the local preset phase clock includes: Processing the first sampling value across clock domains to the clock domain of the local preset phase clock to obtain a second sampling value; The first phase difference is obtained by searching the first local clock phase difference table according to the second sampling value, wherein the first local clock phase difference table is used to characterize the corresponding relationship between the second sampling value and the phase difference of the source synchronous interface clock associated with the second sampling value relative to the local preset phase clock.
4. The phase difference detection method according to claim 2, characterized in that: The sampling of the local clock counter based on the source synchronous interface clock to obtain a first sampling value includes: Driving the local clock counter to count based on the local clock to obtain a count value; The count value is sampled based on the source synchronous interface clock to obtain the first sampled value.
5. The phase difference detection method according to claim 1, characterized in that: The determining a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock includes: Sampling the source synchronous interface data based on the local clock to obtain a third sampling value; The second phase difference between the source synchronous interface data and the local preset phase clock is determined according to the third sampling value.
6. The phase difference detection method according to claim 5, characterized in that: The determining, according to the third sampling value, the second phase difference between the source synchronous interface data and the local preset phase clock comprises: Processing the third sampling value across clock domains to the clock domain of the local preset phase clock to obtain a fourth sampling value; The second phase difference is obtained by searching the second local clock phase difference table according to the fourth sampling value, wherein the second local clock phase difference table is used to characterize the corresponding relationship between the fourth sampling value and the phase difference of the source synchronous interface data associated with the fourth sampling value relative to the local preset phase clock.
7. The phase difference detection method according to any one of claims 1 to 6, characterized in that: Also includes: Determining a compensation phase of a source synchronous interface receiving phase-locked loop according to the target phase difference; The compensation phase is sent to the source synchronous interface receiving phase-locked loop, so that the source synchronous interface receiving phase-locked loop performs phase compensation on the source synchronous interface receiving clock according to the compensation phase.
8. A phase difference detection device for sampling data, characterized in that: include: A first determining module, used to determine a first phase difference between a source synchronous interface clock input by the source synchronous interface and a local preset phase clock; A second determining module, configured to determine a second phase difference between the source synchronous interface data input by the source synchronous interface and the local preset phase clock; The third determination module is used to determine a target phase difference between the source synchronous interface clock and the source synchronous interface data according to the first phase difference and the second phase difference.
9. An FPGA chip, characterized in that: include: Memory; One or more processors coupled to the memory; One or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute the phase difference detection method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, and the program codes can be called by a processor to execute the phase difference detection method according to any one of claims 1 to 7.