Analog-to-digital converter with high bridging capacitor matching degree and analog-to-digital converter circuit

Abstract

The invention relates to the technical field of integrated circuits, in particular to an analog-to-digital converter with high bridging capacitor matching degree and an analog-to-digital converter circuit, the analog-to-digital converter circuit comprises a high-order capacitor array, a low-order capacitor array, a bridging unit, a comparison latch unit and a digital unit; the high-order capacitor array is used for quantizing high-order data in the analog-to-digital converter; the low-order capacitor array is used for quantizing low-order data in the analog-to-digital converter; the bridging unit is used for bridging between the high-order capacitor array and the low-order capacitor array; the comparison latch unit is used for comparing and latching the quantized voltage of the high-order capacitor array and the low-order capacitor array with an external common-mode voltage; and the digital unit is used for converting the analog signal output by the comparison latch unit into a digital signal through successive approximation logic. By adopting the scheme, the ratio of the bridging capacitor to the unit capacitor can be in an integral multiple relationship, so that the matching degree of the bridging capacitor is improved, and more accurate charge redistribution is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an analog-to-digital converter with high bridge capacitance matching and an analog-to-digital converter circuit. Background Art

[0002] The analog-to-digital converter (ADC) is an indispensable component in modern electronic systems. It is responsible for converting continuous analog signals into discrete digital forms. This process is crucial for fields such as data acquisition, control systems, and communication technology. Therefore, the ADC has become a key interface between analog circuits and digital circuits. Among the many types of ADCs, the successive approximation analog-to-digital converter (SAR ADC) is widely favored due to its simple circuit design and low power consumption, and has been widely used in fields such as communications, medical treatment, and sensors.

[0003] The core working principle of SAR ADC is to gradually approximate the value of the original signal by comparing the input analog signal with the internally generated reference voltage, and finally output the corresponding digital code. To achieve this process, SAR ADC relies on a capacitor array called DAC (digital-to-analog converter), which is responsible for generating the required reference voltage. However, with the continuous advancement of integrated circuit technology, higher requirements are placed on the size, speed and power consumption of ADC.

[0004] To solve these problems, modern SAR ADC designs usually use segmented capacitor arrays, which divide the capacitor array into two parts: the MSB (most significant bit) capacitor array and the LSB (least significant bit) capacitor array. These two parts are connected by a bridge capacitor to reduce the chip area occupied by the overall DAC capacitor array. The advantage of this structure is that it can significantly reduce the physical size of the ADC while maintaining high conversion speed and low power consumption.

[0005] However, there is a major problem with the traditional SAR ADC bridge solution: the ratio between the bridge capacitance and the unit capacitance is often not an integer multiple. This non-integer multiple relationship will lead to a loss of conversion accuracy, forcing designers to use additional trimming solutions to compensate for this error. Such trimming is not only time-consuming and labor-intensive, but also difficult to guarantee the trimming results. Therefore, there is an urgent need to provide an analog-to-digital converter circuit with high bridge capacitance matching, which can make the ratio between the bridge capacitance and the unit capacitance an integer multiple relationship, thereby improving the matching of the bridge capacitance and achieving more accurate charge redistribution. Summary of the invention

[0006] The present invention provides an analog-to-digital converter and an analog-to-digital converter circuit with high bridge capacitance matching, which can make the ratio between the bridge capacitance and the unit capacitance an integer multiple, thereby improving the matching degree of the bridge capacitance and achieving more accurate charge redistribution.

[0007] The present invention provides a basic solution 1:

[0008] An analog-to-digital converter circuit with high bridge capacitance matching includes a high-order capacitance array, a low-order capacitance array, a bridge unit, a comparison latch unit and a digital unit;

[0009] The input ports INO, IN1, IN2 and IN3 in the high-order capacitor array are respectively connected to the external common-mode voltage port Vcom, the reference ground port GND, the reference voltage port VREF and the analog input signal port Vin, and the output port OUT0 in the high-order capacitor array is connected to the output port OUT0 in the bridge unit and the input port IP in the comparison latch unit;

[0010] The input ports IN1 and IN2 in the low-position capacitor array are connected to the reference ground port GND and the reference voltage port VREF respectively, and the output port OUT0 in the low-position capacitor array is connected to the input port IN0 in the bridge unit;

[0011] The bridge unit includes a bridge capacitor C6, a bridge capacitor C7, a switch SW1 and a common source operational amplifier A0; the input end of the common source operational amplifier A0 is connected to the input port IN0 in the bridge unit, the output end is connected to one end of the bridge capacitor C7, the other end of the bridge capacitor C7 is connected to the output port OUT0 in the bridge unit, and the output port OUT0 in the bridge unit is connected to the input port IP in the comparison latch unit; the bridge capacitor C6 and the switch SW1 are both connected in parallel with the common source operational amplifier A0;

[0012] The input port IN of the comparison latch unit is connected to the external common mode voltage port Vcom; the output port Vout of the comparison latch unit is connected to the input port INO of the digital unit; the input port INO of the comparison latch unit is connected to the output port OUT0 of the digital unit;

[0013] The digital unit is used for converting the analog signal output by the comparison latch unit into a digital signal through successive approximation logic.

[0014] Furthermore, the high-order capacitor array includes a high-order redundant capacitor with a unit capacitance value and a plurality of high-order sampling capacitors based on the unit capacitance and arranged in an ascending binary weight manner to form a weighted capacitor array;

[0015] The upper plates of the high-order redundant capacitor and each high-order sampling capacitor are connected to each other and connected to the external common-mode voltage port Vcom through a switch SWT; the lower plates of the high-order redundant capacitor and each high-order sampling capacitor are respectively connected to the analog input signal port Vin through a single-pole single-throw switch; the lower plate of the high-order redundant capacitor is also connected to the reference ground port GND through a normally closed switch; the lower plate of each high-order sampling capacitor is also connected to the reference voltage port VREF through a high-order voltage on-off switch, and is also connected to the reference ground port GND through a high-order reference ground on-off switch.

[0016] Furthermore, the low-bit capacitor array includes two low-bit redundant capacitors with unit capacitance values ​​and a plurality of low-bit sampling capacitors based on the unit capacitance and arranged in an ascending binary weight manner to form a weighted capacitor array;

[0017] The upper plates of the low-bit redundant capacitors and each low-bit sampling capacitor are connected and connected to the input port IN0 in the bridge unit; the lower plates of each low-bit redundant capacitor and low-bit sampling capacitor are connected to the reference voltage port VREF through a low-bit voltage on-off switch, and are also connected to the reference voltage port VREF through a low-bit reference ground on-off switch.

[0018] Furthermore, the digital unit is connected to both the high-order capacitor array and the low-order capacitor array, and controls the on and off of each single-pole single-throw switch, each normally closed switch, each high-order voltage on-off switch, each high-order reference ground on-off switch, switch SWT in the high-order capacitor array and each low-order voltage on-off switch and each low-order reference ground on-off switch in the low-order capacitor array through a multi-bit bus output.

[0019] Further, the common source operational amplifier A0 includes a current source, a PMOS tube PM0, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an NMOS tube NM0, an NMOS tube NM1 and an NMOS tube NM2;

[0020] The sources of the PMOS tube PM0, the PMOS tube PM2 and the PMOS tube PM4 are all connected; the gate of the PMOS tube PM0 is connected to the gate of the PMOS tube PM2 and the gate of the PMOS tube PM4, and the drain is connected to the source of the PMOS tube PM1; the drain of the PMOS tube PM2 is connected to the source of the PMOS tube PM3; the gate of the PMOS tube PM1 is connected to the gate of the PMOS tube PM3 and the gate of the PMOS tube PM5; the drain of the PMOS tube PM4 is connected to the source of the PMOS tube PM5;

[0021] The drain of the PMOS tube PM1 is connected to the current source; the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM0; the drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM1 and the output end of the common source operational amplifier A0; the gate of the NMOS tube NM0 is connected to the gate of the NMOS tube NM1; the source of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2; the gate of the NMOS tube NM2 is connected to the input end of the common source operational amplifier A0; the current source, the source of the NMOS tube NM0 and the source of the NMOS tube NM2 are all connected and grounded.

[0022] Furthermore, the input tube of the common-source operational amplifier A0 operates in a subthreshold region.

[0023] Further, the comparison latch unit includes a first-stage comparator, a second-stage comparator, a third-stage comparator, a latch, an SR trigger, a switch SCOO, a switch SCO1, a switch SCO2, a switch SCO3, a switch SCO4, a switch SCO5 and a switch SCO6;

[0024] The input port +IP in the first-stage comparator is connected to the input port IP of the comparison latch unit, the input port -IN is connected to the input port IN of the comparison latch unit, and a switch SCO0 is connected between the input port +IP and the input port -IN; the output port +OUTP in the first-stage comparator is connected to the input port +IP in the second-stage comparator through the calibration capacitor CO1, and the calibration capacitor CO1 and the input port +IP in the second-stage comparator are both connected to the switch SCO1; the output port -OUTN in the first-stage comparator is connected to the input port -IN in the second-stage comparator through the calibration capacitor CO2, and the calibration capacitor CO2 and the input port -IN in the second-stage comparator are both connected to the switch SCO2;

[0025] The output port +OUTP of the second-stage comparator is connected to the input port +IP of the third-stage comparator through the calibration capacitor CO3, and the calibration capacitor CO3 and the input port +IP of the third-stage comparator are both connected to the switch SCO3; the output port -OUTN of the second-stage comparator is connected to the input port -IN of the third-stage comparator through the calibration capacitor CO4, and the calibration capacitor CO4 and the input port -IN of the third-stage comparator are both connected to the switch SCO4;

[0026] The output port +OUTP in the third-stage comparator is connected to the input port +IP in the latch through the calibration capacitor CO5, and the calibration capacitor CO5 and the input port +IP in the latch are both connected to the switch SCO5; the output port -OUTN in the third-stage comparator is connected to the input port -IN in the latch through the calibration capacitor CO6, and the calibration capacitor CO6 and the input port -IN in the latch are both connected to the switch SCO6;

[0027] The other ends of the switches SCO1, SCO2, SCO3, SCO4, SCO5 and SCO6 are all connected to an external common mode voltage port Vcom;

[0028] The comparator is connected to the input port INO in the comparison latch unit and is also connected to the input end of the SR trigger; the output end of the SR trigger is connected to the output port Vout in the comparison latch unit.

[0029] Further, the SR trigger includes a NAND gate X13 and a NAND gate X14;

[0030] One input of the NAND gate X14 is connected to the output port +OUTP in the latch, and the other input is connected to the output of the NAND gate X13; one input of the NAND gate 13 is connected to the output port -OUTN in the latch, and the other input is connected to the output of the NAND gate X14; the output of the NAND gate 13 is also connected to the output port Vout in the comparison latch unit.

[0031] The present invention provides a second basic solution:

[0032] An analog-to-digital converter with high bridge capacitance matching adopts the above analog-to-digital converter circuit with high bridge capacitance matching.

[0033] The principles and advantages of the present invention are:

[0034] 1. A common source op amp whose input tube works at a subthreshold is connected to the bridge unit between the high-order capacitor array and the low-order capacitor array. First, the subthreshold operation enables the input tube of the common source op amp to work at an extremely low current level, which is conducive to reducing power consumption while maintaining a high gain. Secondly, by utilizing the high gain characteristics of the common source op amp, it can be ensured that the potential of the input port of the common source op amp remains approximately unchanged during each switch in the low-order capacitor array, so that the ratio between the bridge capacitance and the unit capacitance of the bridge unit between the high-order capacitor array and the low-order capacitor array is an integer multiple, thereby improving the matching degree of the bridge capacitance and achieving more accurate charge redistribution.

[0035] 2. In the common source operational amplifier A0, PMOS tubes PM0, PM1, PM2 and PM3 form a current mirror, and PMOS tubes PM0, PM1, PM4 and PM5 form a current mirror. If the current source provides the reference current Ibisa, the two current mirrors provide bias currents of Ibisa and 10 times of Ibisa to NMOS tubes NM0 and NMOS tubes NM2 respectively. NMOS tube NM2 acts as a diode load to provide a bias voltage to NMOS tube NM1. When the input and output of the common source operational amplifier are short-circuited, the input and output voltages of the common source operational amplifier are equal. The size of NMOS tube NM2 can be adjusted to make the threshold voltage of NMOS tube NM2 equal to the input and output voltages of the common source operational amplifier. At this time, NMOS tube NM2 works in the subthreshold region, and the overall gain of the common source operational amplifier A0 can reach more than 58dB. When the input and output of the common source operational amplifier are disconnected, the input and output remain unchanged due to the high gain of the common source operational amplifier A0 and the internal bridge capacitor C6 of the bridge unit.

[0036] 3. The digital unit provides successive approximation logic for the high-order capacitor array and the low-order capacitor array, converts the analog signal output by the comparison latch unit into a digital signal through the successive approximation logic, and then controls the conduction and disconnection of each single-pole single-throw switch, each normally closed switch, each high-order voltage on-off switch, each high-order reference ground on-off switch, switch SWT in the high-order capacitor array and each low-order voltage on-off switch and each low-order reference ground on-off switch in the low-order capacitor array through a multi-bit bus output, so as to achieve the purpose of analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The figure is a schematic diagram of the overall circuit structure of an analog-to-digital converter circuit embodiment of the present invention with high bridge capacitance matching.

[0038] Figure 2 The present invention is a schematic diagram of the circuit structure of a common source operational amplifier in an analog-to-digital converter circuit embodiment with high bridge capacitance matching.

[0039] Figure 3 The schematic diagram of the circuit structure of the comparison latch unit in an analog-to-digital converter circuit embodiment of the present invention has a high bridge capacitance matching degree.

[0040] Figure 4 The present invention is a schematic diagram of the circuit structure of a first-stage comparator in an analog-to-digital converter circuit embodiment with high bridge capacitance matching.

[0041] Figure 5 The present invention is a schematic diagram of the circuit structure of a second-stage comparator in an analog-to-digital converter circuit embodiment with high bridge capacitance matching.

[0042] Figure 6 The present invention is a schematic diagram of the circuit structure of a latch in an analog-to-digital converter circuit embodiment with high bridge capacitance matching.

[0043] Figure 7 The schematic diagram of the circuit structure of a NAND gate in an analog-to-digital converter circuit embodiment of the present invention has a high bridge capacitance matching degree.

[0044] Figure 8 The figure is a schematic diagram of the circuit structure of each switch in an analog-to-digital converter circuit embodiment of the present invention with high bridge capacitance matching.

[0045] Fig. 9 The figure is a schematic structural diagram of a digital unit in an analog-to-digital converter circuit embodiment of the present invention with high bridge capacitance matching. DETAILED DESCRIPTION

[0046] The following is further described in detail through specific implementation methods:

[0047] Embodiment 1:

[0048] Embodiment 1 is basically as attached Figure 1 As shown:

[0049] An analog-to-digital converter circuit with high bridge capacitance matching, such as Figure 1 As shown, it includes a high-order capacitor array, a low-order capacitor array, a bridge unit, a comparison latch unit and a digital unit.

[0050] The high-bit capacitor array is used to quantize the high-bit data in the analog-to-digital converter. Figure 1 As shown, the input ports INO, IN1, IN2 and IN3 in the high-order capacitor array are respectively connected to the external common-mode voltage port Vcom, the reference ground port GND, the reference voltage port VREF and the analog input signal port Vin, and the output port OUT0 in the high-order capacitor array is connected to the output port OUT0 in the bridge unit and the input port IP in the comparison latch unit. Among them, the voltage input range of the analog input signal port Vin is 0V to VREF.

[0051] Specifically, the sampling method of the high-order capacitor array is lower plate sampling, including a high-order redundant capacitor CO0 with a unit capacitance value and a plurality of high-order sampling capacitors (corresponding to the high M-bit data conversion capacitors of the digital-to-analog converter) based on the unit capacitance and arranged in an ascending manner according to binary weights to form a weighted capacitor array. In this embodiment, M high-order sampling capacitors are included, namely CO1, CO2, CO3...CO M-1 , CO M The capacitance value of the high-order redundant capacitor CO0 is C; the capacitance value of the high-order sampling capacitor CO1 is 2 0C. The capacitance value of the high-order sampling capacitor CO2 is 2 1 C. The capacitance value of the high-bit sampling capacitor CO3 is 2 2 C…High sampling capacitor CO M-1 The capacitance value is 2 M-2 C. High-bit sampling capacitor CO M The capacitance value is 2 M-1 C, the total capacitance of the high-order redundant capacitor and each high-order sampling capacitor is 2 M C.

[0052] The upper plates of the high-order redundant capacitor and each high-order sampling capacitor are connected to each other and connected to the external common-mode voltage port Vcom through a switch SWT; the lower plates of the high-order redundant capacitor and each high-order sampling capacitor are respectively connected to the analog input signal port Vin through a single-pole single-throw switch; the lower plate of the high-order redundant capacitor is also connected to the reference ground port GND through a normally closed switch; the lower plate of each high-order sampling capacitor is also connected to the reference voltage port VREF through a high-order voltage on-off switch, and is also connected to the reference ground port GND through a high-order reference ground on-off switch.

[0053] Specifically, the lower plate of the high-order redundant capacitor CO0 is connected to the single-pole single-throw switch SP and the normally closed switch SN; the high-order sampling capacitors CO1, CO2, CO3, ... CO M-1 , CO M The lower plates are connected to the single-pole single-throw switches SP1, SP2, SP3...SP M-1 , SP M Connect to the high voltage on / off switch SWP0 <1> 、SWP0 <2> 、SWP0 <3> …SWP0 <m-1>、SWP0 <m>Connect to the high reference ground on-off switch SWN0 <1> SWN0 <2> SWN0 <3> …SWN0 <m-1>、SOUND0 <m>connect.

[0054] The low-bit capacitor array is used to quantize the low-bit data in the analog-to-digital converter. Figure 1 As shown, the input ports IN1 and IN2 of the low-order capacitor array are connected to the reference ground port GND and the reference voltage port VREF respectively, and the output port OUT0 in the low-order capacitor array is connected to the input port IN0 in the bridge unit. In this embodiment, the voltage of the reference voltage port VREF is 2.5V.

[0055] Specifically, the low-bit capacitor array includes two low-bit redundant capacitors with unit capacitance values ​​and a plurality of low-bit sampling capacitors based on the unit capacitance and arranged in a binary weighted ascending manner to form a weighted capacitor array. In this embodiment, N low-bit sampling capacitors are included, namely C11, C12, C13...C1 N-1 、C1 N . Low-level redundant capacitor C1 N0 and C1 N1 The capacitance value of the low-bit sampling capacitor C11 is 2 0 C. The capacitance value of the low-bit sampling capacitor C12 is 2 1 C. The capacitance value of the low-bit sampling capacitor C13 is 2 2 C…Low-bit sampling capacitor C1 N-1 The capacitance value is 2 N-2 C. Low-bit sampling capacitor C1 N The capacitance value is 2 N-1 C.

[0056] The upper plates of the low-bit redundant capacitors and each low-bit sampling capacitor are connected and connected to the input port IN0 in the bridge unit; the lower plates of each low-bit redundant capacitor and low-bit sampling capacitor are connected to the reference voltage port VREF through a low-bit voltage on-off switch, and are also connected to the reference voltage port VREF through a low-bit reference ground on-off switch.

[0057] Specifically, the low-level redundant capacitor C1 N0 、C1 N1 The lower plate is connected to the low voltage on-off switch SCP1 <0> 、SCP1 <1> Connect to the low reference ground on-off switch SCN1 <0> 、SCN1 <1> Connection; low sampling capacitors C11, C12, C13…C1 N-1 、C1 N The lower plate is connected to the low voltage on-off switch SWP1 <1> 、SWP1 <2> 、SWP1 <3> …SWP1 <n-1>、SWP1 <n>Connect to the low reference ground on-off switch SWN1 <1> SWN1 <2> SWN1 <3> …SWN1 <n-1>、SWN1 <n>connect.

[0058] The bridge unit is used for bridging between the high-order capacitor array and the low-order capacitor array, and includes a bridge capacitor C6, a bridge capacitor C7, a switch SW1, and a common source amplifier A0; the input end of the common source amplifier A0 is connected to the input port IN0 in the bridge unit, and the output end is connected to one end of the bridge capacitor C7, the other end of the bridge capacitor C7 is connected to the output port OUT0 in the bridge unit, and the output port OUT0 in the bridge unit is connected to the input port IP in the comparison latch unit; the bridge capacitor C6 and the switch SW1 are both connected in parallel with the common source amplifier A0. In this embodiment, the capacitance values ​​of the bridge capacitor C6 and the bridge capacitor C7 are TC and IC, respectively, where T and I are both constants.

[0059] The input tube of the common source operational amplifier A0 operates in the subthreshold region. Figure 2 As shown, the common source operational amplifier A0 includes a current source, a PMOS tube PM0, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an NMOS tube NM0, an NMOS tube NM1 and an NMOS tube NM2; Ibisa is a reference current provided by an external current reference. NM2 is an input tube, PM4 and PM5 are current source loads, and NM1 is a bias tube. When working, the potential of the input and output ends of the common source operational amplifier A0 is equal, and it plays an operational role.

[0060] The sources of the PMOS tube PM0, the PMOS tube PM2 and the PMOS tube PM4 are all connected; the gate of the PMOS tube PM0 is connected to the gate of the PMOS tube PM2 and the gate of the PMOS tube PM4, and the drain is connected to the source of the PMOS tube PM1; the drain of the PMOS tube PM2 is connected to the source of the PMOS tube PM3; the gate of the PMOS tube PM1 is connected to the gate of the PMOS tube PM3 and the gate of the PMOS tube PM5; the drain of the PMOS tube PM4 is connected to the source of the PMOS tube PM5.

[0061] The drain of the PMOS tube PM1 is connected to the current source; the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM0; the drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM1 and the output end of the common source operational amplifier A0; the gate of the NMOS tube NM0 is connected to the gate of the NMOS tube NM1; the source of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2; the gate of the NMOS tube NM2 is connected to the input end of the common source operational amplifier A0; the current source, the source of the NMOS tube NM0 and the source of the NMOS tube NM2 are all connected and grounded.

[0062] Among them, the PMOS tube PM0, PMOS tube PM1, PMOS tube PM2 and PMOS tube PM3 form a current mirror, and the PMOS tube PM0, PMOS tube PM1, PMOS tube PM4 and PMOS tube PM5 form a current mirror. Since the current source provides a reference current of Ibisa, the two current mirrors provide bias currents of Ibisa and 10 times of Ibisa to the NMOS tube NM0 and the NMOS tube NM2 respectively.

[0063] NMOS tube NM2 acts as a diode load to provide a bias voltage for NMOS tube NM1. When the input and output of the common source op amp are short-circuited, the voltages of the input and output of the common source op amp are equal. The size of NMOS tube NM2 can be adjusted to make the threshold voltage of NMOS tube NM2 equal to the voltages of the input and output of the common source op amp. At this time, NMOS tube NM2 works in the subthreshold region, and the overall gain of the common source op amp A0 can reach more than 58dB. When the input and output of the common source op amp are disconnected, the input and output will remain unchanged under the combined effect of the high gain of the common source op amp A0 and the internal bridge capacitor C6 of the bridge unit.

[0064] The comparison latch unit with offset calibration is used to compare and latch the quantized voltage of the high-order capacitor array and the low-order capacitor array with the common mode voltage Vcom. In this embodiment, the Vcom port voltage is 1.25 V. The input port IN in the comparison latch unit is connected to the external common mode voltage port Vcom; the output port Vout in the comparison latch unit is connected to the input port INO in the digital unit; the input port INO in the comparison latch unit is connected to the output port OUT0 in the digital unit.

[0065] The comparison latch unit includes a first-stage comparator, a second-stage comparator, a third-stage comparator, a latch, an SR trigger, a switch SCOO, a switch SCO1, a switch SCO2, a switch SCO3, a switch SCO4, a switch SCO5 and a switch SCO6. Figure 4 As shown, the first-stage comparator is a NMOS cross-coupled pair load structure. Figure 5 FIG. 1 is a circuit structure of the second-stage comparator. In this embodiment, the second-stage comparator and the third-stage comparator adopt the same circuit structure and use a PMOS cross-coupled pair as a load. The specific circuit structure of the latch is as follows: Figure 6 As shown, the specific circuit structure of the SR trigger is as follows Figure 7 shown.

[0066] like Figure 3 As shown, the input port +IP in the first-stage comparator is connected to the input port IP of the comparison latch unit, the input port -IN is connected to the input port IN of the comparison latch unit, and a switch SCO0 is connected between the input port +IP and the input port -IN; the output port +OUTP in the first-stage comparator is connected to the input port +IP in the second-stage comparator through the calibration capacitor CO1, and the calibration capacitor CO1 and the input port +IP in the second-stage comparator are both connected to the switch SCO1; the output port -OUTN in the first-stage comparator is connected to the input port -IN in the second-stage comparator through the calibration capacitor CO2, and the calibration capacitor CO2 and the input port -IN in the second-stage comparator are both connected to the switch SCO2.

[0067] The output port +OUTP in the second-stage comparator is connected to the input port +IP in the third-stage comparator through the calibration capacitor CO3, and the calibration capacitor CO3 and the input port +IP in the third-stage comparator are both connected to the switch SCO3; the output port -OUTN in the second-stage comparator is connected to the input port -IN in the third-stage comparator through the calibration capacitor CO4, and the calibration capacitor CO4 and the input port -IN in the third-stage comparator are both connected to the switch SCO4.

[0068] The output port +OUTP in the third-level comparator is connected to the input port +IP in the latch through the calibration capacitor CO5, and the calibration capacitor CO5 and the input port +IP in the latch are both connected to the switch SCO5; the output port -OUTN in the third-level comparator is connected to the input port -IN in the latch through the calibration capacitor CO6, and the calibration capacitor CO6 and the input port -IN in the latch are both connected to the switch SCO6.

[0069] The other ends of the switches SCO1 , SCO2 , SCO3 , SCO4 , SCO5 and SCO6 are all connected to the external common mode voltage port Vcom.

[0070] In the working state, the first-level comparator, the second-level comparator and the third-level comparator compare the input data of their respective input ports +IP and -IN, and the final result is transmitted to the latch for latching, and sent to the digital unit for successive approximation logic, thereby obtaining the M+N-bit data output of the analog-to-digital converter. The above three-level comparators all use the output offset calibration method to calibrate the offset voltage of the comparator. When the digital unit controls the input of IN0 to be low level, the switches SCOO, SCO1, SCO2, SCO3, SCO4, SCO5 and SCO6 are all closed, and the input ports +IP and -IN of the three-level comparator are short-circuited together through the external Vcom voltage. At this time, the offset voltage of each comparator will be respectively stored on the capacitors CO1, CO2, CO3, CO4, CO5 and CO6; when the digital unit controls the input of IN0 to be high level, the output of each comparator will subtract the offset voltage of the capacitor to obtain the correct comparison result for latching.

[0071] The comparator is connected to the input port INO in the comparison latch unit and is also connected to the input end of the SR trigger; the output end of the SR trigger is connected to the output port Vout in the comparison latch unit.

[0072] The SR trigger includes a NAND gate X13 and a NAND gate X14; one input of the NAND gate X14 is connected to the output port +OUTP in the latch, and the other input is connected to the output of the NAND gate X13; one input of the NAND gate 13 is connected to the output port -OUTN in the latch, and the other input is connected to the output of the NAND gate X14; the output of the NAND gate 13 is also connected to the output port Vout in the comparison latch unit. When the differential output end of the latch latches the output of the comparator, the output Vout of the SR trigger will send the output to the digital unit for successive approximation logic.

[0073] like Fig. 9 As shown, the digital unit is used to convert the analog signal output by the comparison latch unit into a digital signal through successive approximation logic. The digital unit is connected to both the high-order capacitor array and the low-order capacitor array, and controls the circuit structure through a multi-bit bus output. Figure 8 The single-pole single-throw switches, normally closed switches, high-voltage on-off switches, high-reference ground on-off switches, switch SWT in the high-level capacitor array shown, and the on-and-off of low-level voltage on-off switches and low-level reference ground on-off switches in the low-level capacitor array are shown.

[0074] Specifically, the digital unit is designed at the behavioral level using Verilog, and then a gate-level netlist is synthesized based on Verilog. Finally, the gate-level netlist is used for layout and routing to form the final layout. All gate-level circuits in the layout are designed using standard units, and a successive approximation algorithm is embedded. The digital unit sends a signal through its internal output terminal OUT0 to latch the input Vout of the comparison latch module with offset calibration to control the conduction and shutdown of each switch, thereby realizing the successive approximation algorithm.

[0075] In the sampling phase, the digital unit controls the low voltage on and off switch SCP1 <0> 、SCP1 <1> , low voltage on-off switch SWP1 <1> 、SWP1 <2> 、SWP1 <3> …SWP1 <n-1>、SWP1 <n>, the low redundant capacitor C1 N0 、C1 N1 , low-bit sampling capacitors C11, C12, C13…C1 N-1 、C1 N The lower plate is connected to the reference voltage port VREF; by controlling the low reference ground on-off switch SCN1 <0> 、SCN1 <1> , low reference ground on-off switch SWN1 <1> SWN1 <2> SWN1 <3> …SWN1 <n-1>、SWN1 <n>Open, switch SW1 is closed, so that Figure 1 The potential of the midpoint VX is equal to the potential of the point VY and VX=VY=Vt (Vt is the static bias point voltage of the common source op amp A0); by controlling the switch SWT to close, VP=Vcom, and the digital unit controls the single-pole single-throw switches SP1, SP2, SP3...SP M-1 , SP M , the high redundant capacitor CO0, high sampling capacitor CO1, CO2, CO3...CO M-1 , CO M The lower plate is connected to the analog input signal port Vin, and the high voltage on-off switch SWP0 <1> 、SWP0 <2> 、SWP0 <3> …SWP0 <m-1>、SWP0 <m>, high reference ground on-off switch SWN0 <1> SWN0 <2> SWN0 <3> …SWN0 <m-1>、SOUND0 <m>Disconnected, at this time, the high redundant capacitor CO0, high sampling capacitor CO1, CO2, CO3...CO M-1 , CO M The charge on the upper plate is:

[0076] Q1=(Vcom-VY)I*C+(Vcom-Vin)2 M C

[0077] In the formula, I (I is an integer) indicates that the capacitance of the bridge capacitor C7 is I times the unit capacitance (C), Vcom is the common mode voltage of the external input, VY is the voltage at point VY, C is the unit capacitance, Vin is the voltage to be sampled from the external input, 2 M C is C00~C0 M The sum of all capacitor values ​​(where M is an integer, which is the capacitor number of the high-order capacitor array).

[0078] After the sampling phase is over, the switch conversion of the high-order capacitor array is performed. When the high-order capacitor array performs the first successive approximation, the switch SW1, the switch SWT, the single-pole single-throw switches SP1, SP2, SP3…SP M-1 , SP M Both are disconnected, the high sampling capacitor CO M The lower plate of the switch SWP0 is turned on and off by a high voltage <m>Connect to the reference voltage port VREF, and the rest of the switch states remain unchanged with the sampling stage. At this time, the high redundant capacitor CO0, the high sampling capacitors CO1, CO2, CO3...CO m-1 , CO M The charge on the upper plate is:

[0079] Q2=(VP-VY)I*C+(VP-VREF)2 M-1 C+VP*2 M-1 C

[0080] Since charge is conserved, we have:

[0081] Q1=Q2

[0082] From this we can get:

[0083]

[0084] Since the input port IN in the comparison latch unit with offset calibration is connected to the external common mode voltage port Vcom, if:

[0085]

[0086] At this time there are:

[0087]

[0088] At this time, the Vout value latched by the comparison latch unit is 1, and the digital unit will high sampling capacitor CO M The corresponding high voltage on-off switch SWP0 <m>Turn off and turn on / off switch SWN0 <m>At the same time, the digital unit writes "0" on the M+Nth bit output register of the digital-to-analog converter to complete the quantization of the highest bit (i.e., the M+Nth bit) of the digital-to-analog converter; conversely, if the Vout value latched by the comparison latch unit is 0, the digital unit will M The corresponding high voltage on-off switch SWP0 <m>Keep the current open state and turn on and off the high reference ground switch SWN0 <m>Keep the current off state, and at the same time, the digital unit writes "1" to the M+Nth bit output register of the digital-to-analog converter to complete the quantization of the highest bit (i.e., the M+Nth bit) of the digital-to-analog converter. Similarly, the other switches of the high-order capacitor array (the high-order voltage on-off switch SWP0 <1> 、SWP0 <2> 、SWP0 <3> …SWP0 <m-1>and SWN0<1>, SWN0<2>, SWN0<3>…SWN0 <m-1>) transformation is also analyzed according to the above method. After VIN undergoes M switching transformations and is compared with Vcom, Figure 1 The voltage at point VP is shown as After M comparisons are completed, the quantization of the high M bits of data of the digital-to-analog converter is completed.

[0089] After the switch conversion in the high-order capacitor array is completed, the switch conversion of the low-order capacitor array is performed. The capacitance of the low-order capacitor array is N+2 bits in total, of which the last two bits are redundant bits. When the digital-to-analog converter is quantized, the last two bits will not be latched as data, and only the first N bits will be latched. To simplify the analysis, when making comparisons, it is assumed that the high-order redundant capacitor CO0 and the high-order sampling capacitors (CO1, CO2, CO3…CO M-1 , CO M ) are connected to the reference ground port GND through the high-order reference ground on-off switch (the high-order capacitor array has completed the quantization of the high M-bit data at this time. In fact, the high-order redundant capacitor and the high-order sampling capacitor can be connected to the reference ground port GND and the reference voltage port VREF, which will not affect the analysis).

[0090] Low sampling capacitor C1 N The lower plate of the switch is switched from VREF to 0 (low voltage on-off switch SWP1). <n>Shutdown, SWN1 <n>Open), due to the high gain characteristics of the input tube working in the subthreshold common source amplifier A0 (the gain of A0 is greater than 58dB), the input port of the common source amplifier still holds VX=Vt during the low-order capacitor array switch conversion process. In this process, the low-order redundant capacitor C1 N0 、C1 N1 , low-bit sampling capacitors C11, C12, C13…C1 N-1 、C1 N The charge on the upper plate does not involve exchange, so the charge is conserved. By analyzing the low-order redundant capacitor C1 in the sampling phase N0 、C1 N1 , low-bit sampling capacitors C11, C12, C13…c1 N-1 、c1 N The charge on the upper plate is:

[0091] Q VX0 =(VX-VREF)(2 N+1 )C+(VX-VY)T*C

[0092] In the formula, Q VX0 C1 is the low-level redundant capacitor in the sampling phase N0 、C1 N1 , low-bit sampling capacitors C11, C12, C13…C1 N-1 、C1 N The charge on the upper plate of the sampling stage is VX and VY are shorted by SW1 to the static operating point of the common source op amp A0, so VX = VY. Combining the above formula, we get:

[0093] Q VX0 =(VX-VREF)(2 N +1)C

[0094] When the low sampling capacitor C1 of the low capacitor array N Transfer from VREF to GND (low voltage on-off switch SWP1 <n>Disconnect, low reference ground on-off switch SWN1 <n>When closed, the low redundant capacitor c1 N0 、C1 N1 , low-bit sampling capacitors C11, C12, C13…C1 N-1 、C1 N The charge on the upper plate is:

[0095] Q VX1 =(VX′-VREF)(2 N-1 +1)C+VX′*(2 N-1 )C+(VX′-VY′)T*C

[0096] Where VX′ and VY′ represent the low-order sampling capacitor C1 when the low-order capacitor array is converted. N The potentials of VX and VY during switching need to be distinguished from those of VX and VY during sampling. As mentioned earlier, due to the high gain of the common-source op amp A0, VX = VX′ = VY = Vt. Combining the above formula, we can get:

[0097] Q VX1 =(VX-VREF)(2 N-1 +1)C+VX*(2 N-1 )C+(VY-VY′)T*C

[0098] During this process, the low-level redundant capacitor C1 N0 、C1 N1 , low-bit sampling capacitors C11, C12, C13…C1 N-1 、C1 N The charge on the upper plate does not involve exchange, so the charge is conserved, that is, Q VX0 =Q VX1 , we can get:

[0099]

[0100] That is:

[0101]

[0102] It can be seen that when the low-order capacitor array is converted, the low-order sampling capacitor C1 N During the conversion process, the low-bit sampling capacitor C1 N Before and after the corresponding switch is transferred from VREF to GND, the potential of VY increases compared to the sampling stage. The potential change of point VP is analyzed below. As described in the sampling stage, during the sampling stage, the high redundant capacitor CO0 and the high sampling capacitors CO1, CO2, CO3…CO M-1 , CO M The charge on the upper plate is:

[0103] Q1=(Vcom-VY)I*C+(Vcom-Vin)2 M C

[0104] When the low-order capacitor array is converted, the low-order sampling capacitor C1 N In the process of the corresponding switch being transferred from VREF to GND, the high redundant capacitor CO0 and the high sampling capacitors CO1, CO2, CO3…CO M-1 , CO M The charge on the upper plate is:

[0105] Q2=(VP-VY′)I*C+(VP)2 M C

[0106] According to the charge conservation law Q1 = Q2, we can get:

[0107]

[0108] Since the input port IN in the comparison latch unit is connected to the external common mode voltage port Vcom, if:

[0109]

[0110] Then we have:

[0111]

[0112] That is:

[0113]

[0114] make:

[0115]

[0116] Then we have:

[0117]

[0118] At this time, the Vout value latched by the comparison latch unit is 1, and the digital unit will connect the low-bit sampling capacitor C1 N The corresponding low voltage on-off switch SWP1 <n>Keep the current shutdown state, and the low reference ground turns on and off switch SWN1 <n>Keep the current open state (the existence of the common source op amp A0 causes the points VX and VY to be in opposite phase). At the same time, the digital unit writes "0" to the M+1th bit output register of the digital-to-analog converter to complete the quantization of the M+1th bit data of the digital-to-analog converter; conversely, if the Vout value latched by the comparison latch unit is 0, the digital unit will compare the low-bit sampling capacitor C1. N The corresponding low voltage on-off switch SWP1 <n>Open, the low reference ground on-off switch SWN1 <n>At the same time, the digital unit writes "1" to the M+1th bit output register of the digital-to-analog converter to complete the quantization of the M+1th bit data of the digital-to-analog converter. Similarly, the other switches of the low-order capacitor array (low-order voltage on-off switch SCP1 <0> 、SCP1 <1> , low reference ground on-off switch SCN1 <0> 、SCN1 <1> , low voltage on-off switch SWP1 <1> 、SWP1 <2> 、SWP1 <3> …SWP1 <n-1>, low reference ground on-off switch SWN1 <1> SWN1 <2> SWN1 <3> …SWN1 <n-1>) transformation is also analyzed according to the above method. However, due to C1 N0 and C1 N1 For low-level redundant capacitors, low-level voltage on-off switch SCP1 <0> 、SCP1 <1> , low reference ground on-off switch SCN1 <0> 、SCN1 <1> The state of VIN will not be written into the register by the digital unit. After VIN undergoes N+2 switching changes and is compared with Vcom, Figure 1 The voltage at point VP is shown as After N+2 comparisons, the digital unit will only use the low-bit sampling capacitors C11, C12, C13…C1 N-1 、C1 N The state of each switch connected to the lower plate writes the N-bit low-order LSB data to the register, thereby completing the quantization of the low-order N-bit data of the digital-to-analog converter. Therefore, by utilizing the high-gain characteristics of the common-source op amp A0 (the gain of A0 is greater than 58dB) whose input tube works at the subthreshold, the potential of the input port of the common-source op amp remains approximately unchanged when the low-order capacitor array switch is changed, so that the number of bridge capacitors C6 and C7 is an integer multiple of the unit capacitor (T times and I times, respectively, and meets ), so there is no need to introduce additional adjustment solutions, which makes it easier to match during layout design.

[0119] like Figure 2 As shown, in the common source operational amplifier A0, PMOS tubes PM0, PMOS tubes PM1, PMOS tubes PM2 and PMOS tubes PM3 form a current mirror, and PMOS tubes PM0, PMOS tubes PM1, PMOS tubes PM4 and PMOS tubes PM5 form a current mirror. Assuming that the current source provides a reference current Ibisa, the two current mirrors provide bias currents of Ibisa and 10 times of Ibisa to NMOS tubes NM0 and NMOS tubes NM2, respectively. NMOS tube NM2 acts as a diode load to provide a bias voltage to NMOS tube NM1. When the input terminal and the output terminal of the common source operational amplifier are short-circuited, the input terminal and the output terminal voltage of the common source operational amplifier are equal. The size of NMOS tube NM2 can be adjusted to make the threshold voltage of NMOS tube NM2 equal to the input terminal and the output terminal voltage of the common source operational amplifier. At this time, NMOS tube NM2 works in the subthreshold region, and the overall gain of the common source operational amplifier A0 can reach more than 58dB. When the input and output of the common source operational amplifier are disconnected, the input and output remain unchanged due to the high gain of the common source operational amplifier A0 and the internal bridge capacitor C6 of the bridge unit.

[0120] like Figure 3 As shown, in the working state, the first-level comparator, the second-level comparator and the third-level comparator compare the input data of their respective input ports +IP and -IN, and the final result is transmitted to the latch for latching, and sent to the digital unit for successive approximation logic, thereby obtaining the M+N-bit data output of the analog-to-digital converter. The above three-level comparators all use the output offset calibration method to calibrate the offset voltage of the comparator. When the digital unit controls the input of IN0 to be low level, the switches SCOO, SCO1, SCO2, SCO3, SCO4, SCO5 and SCO6 are all closed, and the input ports +IP and -IN of the three-level comparator are short-circuited together through the external Vcom voltage. At this time, the offset voltage of each comparator will be respectively stored on the capacitors CO1, CO2, CO3, CO4, CO5 and CO6; when the digital unit controls the input of IN0 to be high level, the output of each comparator will subtract the offset voltage of the capacitor to obtain the correct comparison result for latching. The latch is followed by an SR trigger composed of a NAND gate X13 and a NAND gate X14. When the differential output end of the latch latches the output of the comparator, the output Vout of the SR trigger will send the output to the digital unit for successive approximation logic.

[0121] Specifically, Figure 4 The figure shows the circuit structure of the first-stage comparator, Ibias is the reference bias current provided by the external current reference, PM0' to PM3' are current mirror structures composed of PMOS tubes, which provide long-tail bias current for the first-stage comparator, IP and IN in the first-stage comparator are the same-direction input terminal and the reverse input terminal of the first-stage comparator, OUTP and OUTP in the first-stage comparator are the same-direction output terminal and the reverse output terminal of the first-stage comparator, PM4' and PM5' are differential pair tubes composed of PMSO tubes, NM0' to NM3' are loads composed of NMOS tubes, among which NM1' and NM2' are cross-coupled structures, and NM0' and NM3' are diode structures.

[0122] Figure 5 The circuit structure of the second-stage comparator is shown in the figure, which is similar to the circuit structure of the first-stage comparator, but the load is a PMSO tube. Among them, Ibias is the reference bias current provided by the external current reference, NM2'' to NM5'' are current mirror structures composed of NMOS tubes, providing long-tail bias current for the comparator, IP and IN in the second-stage comparator are the same-direction input terminal and reverse input terminal of the second-stage comparator, OUTP and OUTP in the second-stage comparator are the same-direction output terminal and reverse output terminal of the second-stage comparator, NM0'' and NM1'' are differential pair tubes composed of NMSO tubes, PM0'' to PM3'' are loads composed of PMOS tubes, among which PM1'' and PM2'' are cross-coupling structures, and PM0'' and PM3'' are diode structures.

[0123] Figure 6 The figure shows the circuit structure of a latch with offset calibration, wherein Ibias is the reference bias current provided by an external current reference, NM'0 to NM'3 are current mirror bias structures composed of NMOS tubes, providing long-tail bias currents for NM'4 and NM'5 tubes of the latch; PM'0 to PM'1 are current mirror bias structures composed of PMOS tubes, providing load bias currents for PM'2 to PM'5 tubes of the latch; NM'8 and NM'9 are input differential pair tubes of the latch, NM'6, NM'7 and PM'7, PM'8 are cross-coupled loads composed of NMOS tubes and PMOS tubes respectively, IP and IN in the latch are the same-direction input terminal and the reverse input terminal of the latch, and OUTP and OUTP in the latch are the same-direction output terminal and the reverse output terminal of the latch.

[0124] Figure 7 The figure shows the circuit structure of the NAND gate in the trigger SR, where PM <0> and PM <1> For PMOS tube, NM <0> and NM <1> It is an NMOS tube, A and B are the inputs of the NAND gate, and OUT is the output of the NAND gate.

[0125] Figure 8 The circuit structure of all mode switches in this scheme is shown as follows, where PM[0] and NM[O] form an inverter structure, NM[1] and PM[1] form a transmission gate structure, CT is the control pin of the switch, IN is the switch input pin, and OUT is the switch output pin. When the digital unit controls CT to a high level, CTN is a low level, and both NM[1] and PM[1] are turned on. The entire switch will be turned on to transmit signals from IN to OUT. Conversely, when the digital unit CT is a low level, CTN is a high level, and both NM[1] and PM[1] are turned off. The entire switch will be turned off and unable to transmit signals from IN to OUT, presenting a high impedance state.

[0126] Fig. 9 This is a module diagram of a digital unit. The digital unit is designed at the behavioral level using Verilog, and then a gate-level netlist is synthesized based on Verilog. Finally, the gate-level netlist is used for layout and routing to form the final layout. All gate-level circuits in the layout are designed using standard units, with a built-in successive approximation algorithm. The digital unit sends a signal through its internal output terminal OUT0 to latch the input Vout of the comparison latch module with offset calibration to control the on and off of each switch, thereby realizing the successive approximation algorithm.

[0127] An analog-to-digital converter with high bridge capacitance matching adopts the above analog-to-digital converter circuit with high bridge capacitance matching.

[0128] The above are only embodiments of the present invention. Common knowledge such as the known specific structures and characteristics in the scheme is not described in detail here. Ordinary technicians in the relevant field know all the common technical knowledge in the technical field to which the invention belongs before the application date or priority date, can obtain all the existing technologies in the field, and have the ability to apply conventional experimental means before that date. Ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the enlightenment given by this application. Some typical known structures or known methods should not become obstacles for ordinary technicians in the relevant field to implement this application. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, which should also be regarded as the scope of protection of the present invention, and these will not affect the effect of the implementation of the present invention and the practicality of the patent. The scope of protection required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to interpret the content of the claims. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / m> < / m>

Claims

1. An analog-to-digital converter circuit with high bridge capacitance matching, Features: It includes a high-position capacitor array, a low-position capacitor array, a bridge unit, a comparison latch unit and a digital unit; The input ports INO, IN1, IN2 and IN3 in the high-order capacitor array are respectively connected to the external common-mode voltage port Vcom, the reference ground port GND, the reference voltage port VREF and the analog input signal port Vin, and the output port OUT0 in the high-order capacitor array is connected to the output port OUT0 in the bridge unit and the input port IP in the comparison latch unit; The input ports IN1 and IN2 in the low-position capacitor array are connected to the reference ground port GND and the reference voltage port VREF respectively, and the output port OUT0 in the low-position capacitor array is connected to the input port IN0 in the bridge unit; The bridge unit includes a bridge capacitor C6, a bridge capacitor C7, a switch SW1 and a common source operational amplifier A0; The input end of the common source operational amplifier A0 is connected to the input port IN0 in the bridge unit, and the output end is connected to one end of the bridge capacitor C7. The other end of the bridge capacitor C7 is connected to the output port OUT0 in the bridge unit. The output port OUT0 in the bridge unit is connected to the input port IP in the comparison latch unit. The bridge capacitor C6 and the switch SW1 are both connected in parallel with the common source operational amplifier A0. The input port IN of the comparison latch unit is connected to the external common mode voltage port Vcom; the output port Vout of the comparison latch unit is connected to the input port INO of the digital unit; the input port INO of the comparison latch unit is connected to the output port OUT0 of the digital unit; The digital unit is used to convert the analog signal output by the comparison latch unit into a digital signal through successive approximation logic.

2. The analog-to-digital converter circuit with high bridge capacitance matching according to claim 1, Features: The high-order capacitor array includes a high-order redundant capacitor with a unit capacitance value and a plurality of high-order sampling capacitors based on the unit capacitance and arranged in an increasing binary weight manner to form a weighted capacitor array; The upper plates of the high-order redundant capacitor and each high-order sampling capacitor are connected to each other and connected to the external common-mode voltage port Vcom through a switch SWT; the lower plates of the high-order redundant capacitor and each high-order sampling capacitor are respectively connected to the analog input signal port Vin through a single-pole single-throw switch; the lower plate of the high-order redundant capacitor is also connected to the reference ground port GND through a normally closed switch; the lower plate of each high-order sampling capacitor is also connected to the reference voltage port VREF through a high-order voltage on-off switch, and is also connected to the reference ground port GND through a high-order reference ground on-off switch.

3. The analog-to-digital converter circuit with high bridge capacitance matching according to claim 2, Features: The low-bit capacitor array includes two low-bit redundant capacitors with unit capacitance values ​​and a plurality of low-bit sampling capacitors based on the unit capacitance and arranged in an increasing binary weight manner to form a weighted capacitor array; The upper plates of the low-bit redundant capacitors and each low-bit sampling capacitor are connected and connected to the input port IN0 in the bridge unit; the lower plates of each low-bit redundant capacitor and low-bit sampling capacitor are connected to the reference voltage port VREF through a low-bit voltage on-off switch, and are also connected to the reference voltage port VREF through a low-bit reference ground on-off switch.

4. The analog-to-digital converter circuit with high bridge capacitance matching according to claim 3, Features: The digital unit is connected to both the high-order capacitor array and the low-order capacitor array, and controls the on and off of each single-pole single-throw switch, each normally closed switch, each high-order voltage on-off switch, each high-order reference ground on-off switch, switch SWT in the high-order capacitor array and each low-order voltage on-off switch and each low-order reference ground on-off switch in the low-order capacitor array through a multi-bit bus output.

5. The analog-to-digital converter circuit with high bridge capacitance matching according to claim 1, Features: The common source operational amplifier A0 includes a current source, a PMOS tube PM0, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an NMOS tube NM0, an NMOS tube NM1 and an NMOS tube NM2; The sources of the PMOS tube PM0, the PMOS tube PM2 and the PMOS tube PM4 are all connected; the gate of the PMOS tube PM0 is connected to the gate of the PMOS tube PM2 and the gate of the PMOS tube PM4, and the drain is connected to the source of the PMOS tube PM1; the drain of the PMOS tube PM2 is connected to the source of the PMOS tube PM3; the gate of the PMOS tube PM1 is connected to the gate of the PMOS tube PM3 and the gate of the PMOS tube PM5; the drain of the PMOS tube PM4 is connected to the source of the PMOS tube PM5; The drain of the PMOS tube PM1 is connected to the current source; the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM0; the drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM1 and the output end of the common source operational amplifier A0; the gate of the NMOS tube NM0 is connected to the gate of the NMOS tube NM1; the source of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2; the gate of the NMOS tube NM2 is connected to the input end of the common source operational amplifier A0; the current source, the source of the NMOS tube NM0 and the source of the NMOS tube NM2 are all connected and grounded.

6. The analog-to-digital converter circuit with high bridge capacitance matching according to claim 1, Features: The input tube of the common-source operational amplifier A0 operates in the subthreshold region.

7. The analog-to-digital converter circuit with high bridge capacitance matching according to claim 1, Features: The comparison latch unit includes a first-stage comparator, a second-stage comparator, a third-stage comparator, a latch, an SR trigger, a switch SCOO, a switch SCO1, a switch SCO2, a switch SCO3, a switch SCO4, a switch SCO5 and a switch SCO6; The input port +IP in the first-stage comparator is connected to the input port IP of the comparison latch unit, the input port -IN is connected to the input port IN of the comparison latch unit, and a switch SCO0 is connected between the input port +IP and the input port -IN; the output port +OUTP in the first-stage comparator is connected to the input port +IP in the second-stage comparator through the calibration capacitor CO1, and the calibration capacitor CO1 and the input port +IP in the second-stage comparator are both connected to the switch SCO1; the output port -OUTN in the first-stage comparator is connected to the input port -IN in the second-stage comparator through the calibration capacitor CO2, and the calibration capacitor CO2 and the input port -IN in the second-stage comparator are both connected to the switch SCO2; The output port +OUTP of the second-stage comparator is connected to the input port +IP of the third-stage comparator through the calibration capacitor CO3, and the calibration capacitor CO3 and the input port +IP of the third-stage comparator are both connected to the switch SCO3; the output port -OUTN of the second-stage comparator is connected to the input port -IN of the third-stage comparator through the calibration capacitor CO4, and the calibration capacitor CO4 and the input port -IN of the third-stage comparator are both connected to the switch SCO4; The output port +OUTP in the third-stage comparator is connected to the input port +IP in the latch through the calibration capacitor CO5, and the calibration capacitor CO5 and the input port +IP in the latch are both connected to the switch SCO5; the output port -OUTN in the third-stage comparator is connected to the input port -IN in the latch through the calibration capacitor CO6, and the calibration capacitor CO6 and the input port -IN in the latch are both connected to the switch SCO6; The other ends of the switches SCO1, SCO2, SCO3, SCO4, SCO5 and SCO6 are all connected to an external common mode voltage port Vcom; The comparator is connected to the input port INO in the comparison latch unit and is also connected to the input end of the SR trigger; the output end of the SR trigger is connected to the output port Vout in the comparison latch unit.

8. The analog-to-digital converter circuit with high bridge capacitance matching according to claim 7, Features: The SR trigger includes a NAND gate X13 and a NAND gate X14; One input of the NAND gate X14 is connected to the output port +OUTP in the latch, and the other input is connected to the output of the NAND gate X13; one input of the NAND gate 13 is connected to the output port -OUTN in the latch, and the other input is connected to the output of the NAND gate X14; the output of the NAND gate 13 is also connected to the output port Vout in the comparison latch unit.

9. An analog-to-digital converter with high bridge capacitance matching, Features: An analog-to-digital converter circuit with high bridge capacitance matching according to any one of claims 1 to 8 is adopted.

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