Semiconductor structure and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a memory and electronic equipment. The semiconductor structure comprises a first channel layer, a second channel layer, a first gate dielectric layer, a second bottom gate dielectric layer, a second top gate dielectric layer, a first electrode, a second electrode, a third electrode, a fourth electrode and a fifth electrode, the first electrode is arranged on the substrate, the first gate dielectric layer and the first channel layer are sequentially stacked on the first electrode, and the second electrode and the third electrode are electrically connected to the first channel layer; the second bottom gate dielectric layer, the second channel layer and the second top gate dielectric layer are sequentially stacked on the third electrode, the fourth electrode is arranged on the second top gate dielectric layer, and the second electrode and the fifth electrode are electrically connected to the second channel layer. According to the semiconductor structure, one bit line can be reduced, so that the space required by one bit line and the related preparation process can be saved, the design density of the transistor can be further improved, and meanwhile, the preparation process can be simplified.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, a memory and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a common component in current electronic products such as computers and mobile terminals. The common dynamic random access memory currently uses a 1T1C (1Transistor 1Capacitor) structure, that is, a storage unit contains a transistor and a capacitor, where the capacitor is used to store data. When reading data, the charge of the capacitor is consumed, and the capacitor itself also leaks electricity, so the charge in the capacitor needs to be constantly refreshed, which results in high power consumption.

[0003] 2T0C (2Transistor 0Capacitor) is a capacitor-free storage structure in which a storage unit contains two transistors, and the gate capacitance of one transistor is used to store information. This structure has begun to attract attention because it can avoid the problems caused by capacitors in traditional technologies. However, the density of devices based on this structure still needs to be further improved. Summary of the invention

[0004] Based on this, in order to improve the density of the semiconductor device, it is necessary to provide a semiconductor structure. Furthermore, a method for preparing the semiconductor structure, a memory and an electronic device are provided.

[0005] According to some embodiments of the present disclosure, there is provided a semiconductor structure comprising: a first channel layer, a second channel layer, a first gate dielectric layer, a second bottom gate dielectric layer, a second top gate dielectric layer, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode;

[0006] The first electrode is disposed on the substrate, the first gate dielectric layer and the first channel layer are sequentially stacked on the first electrode, the second electrode and the third electrode are both electrically connected to the first channel layer, and the second electrode and the third electrode are laterally spaced apart;

[0007] The second bottom gate dielectric layer, the second channel layer and the second top gate dielectric layer are sequentially stacked on the third electrode, the fourth electrode is disposed on the second top gate dielectric layer, and the second electrode and the fifth electrode are electrically connected to different regions of the second channel layer and are spaced apart.

[0008] In some embodiments of the present disclosure, the second electrode and the third electrode are both disposed on a side of the first channel layer away from the substrate, and the second channel layer is disposed between the second electrode and the fifth electrode.

[0009] In some embodiments of the present disclosure, the third electrode, the fourth electrode, the fifth electrode and the second channel layer form a group of functional components, the semiconductor structure includes a plurality of groups of the functional components arranged at intervals, the second electrode is arranged between two adjacent groups of the functional components, and the second electrode is electrically connected to two of the second channel layers in the two groups of the functional components.

[0010] In some embodiments of the present disclosure, the two third electrodes located on both sides of the second electrode are arranged on the same first channel layer, and there are also two first electrodes, the two first electrodes are arranged at intervals, and the first channel layer is arranged on the side of the two first electrodes away from the substrate.

[0011] In some embodiments of the present disclosure, the semiconductor structure further includes a first dielectric layer, the first dielectric layer is disposed between the substrate and the first gate dielectric layer, and the first electrode is located in a recessed region of the first dielectric layer on a side away from the substrate.

[0012] In some embodiments of the present disclosure, the second electrode includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are sequentially stacked on the first channel layer, the bottom surface of the second conductive layer is lower than the bottom surface of the second channel layer, the top surface of the second conductive layer is higher than the top surface of the second channel layer, and both sides of the second conductive layer protrude from both sides of the first conductive layer.

[0013] In some embodiments of the present disclosure, the semiconductor structure further includes a bit line conductive layer, wherein the bit line conductive layer is disposed on the second electrode and electrically connected to the second electrode.

[0014] In some embodiments of the present disclosure, the material of the first channel layer and / or the material of the second channel layer includes a metal oxide semiconductor material with a band gap greater than 2 eV.

[0015] Furthermore, the present disclosure also provides a method for preparing the semiconductor structure as described in the above embodiment, which comprises the following steps:

[0016] preparing the first electrode on the substrate;

[0017] sequentially forming the first gate dielectric layer and the first channel layer on the first electrode;

[0018] preparing a first conductive layer and the third electrode on the first channel layer;

[0019] The second bottom gate dielectric layer, the second channel layer, the second top gate dielectric layer and the fourth electrode are sequentially formed on the third electrode, wherein the first conductive layer is exposed on a side of the second channel layer;

[0020] A second conductive layer is formed on the first conductive layer, and the fifth electrode is formed on a side of the second channel layer away from the second conductive layer. The second electrode includes the first conductive layer and the second conductive layer.

[0021] In some embodiments of the present disclosure, in the step of preparing the first conductive layer and the third electrode on the first channel layer, two third electrodes are prepared and are respectively disposed on both sides of the first conductive layer;

[0022] The step of sequentially preparing the second bottom gate dielectric layer, the second channel layer, the second top gate dielectric layer and the fourth electrode on the third electrode comprises:

[0023] Sequentially preparing a bottom gate dielectric material layer, a second channel material layer and a top gate dielectric material layer on the first conductive layer and the two third electrodes;

[0024] preparing two fourth electrodes spaced apart from each other on the top gate dielectric material layer; and,

[0025] The top gate dielectric material layer, the second channel material layer and the bottom gate dielectric material layer located above the first conductive layer are etched in sequence to form an electrode opening exposing the first conductive layer, and two second top gate dielectric layers, two second channel layers and two second top gate dielectric layers are formed on both sides of the electrode opening, respectively, and the two fourth electrodes are respectively arranged on the two second top gate dielectric layers.

[0026] In some embodiments of the present disclosure, the second conductive layer is prepared in the electrode opening, and two sides of the second conductive layer protrude from two sides of the first conductive layer.

[0027] In some embodiments of the present disclosure, the step of preparing the first electrode on the substrate includes: preparing two first electrodes spaced apart from each other on the substrate; and covering the two first electrodes with the first gate dielectric layer and the first channel layer.

[0028] In some embodiments of the present disclosure, the step of preparing the first conductive layer and the third electrode on the first channel layer includes:

[0029] preparing a patterned second dielectric layer on the first channel layer;

[0030] Based on the pattern of the second dielectric layer, depositing the material of the first conductive layer and the material of the third electrode on the first channel layer to form the first conductive layer and the third electrode respectively;

[0031] A top surface of the second dielectric layer, a top surface of the first conductive layer, and a top surface of the third electrode are flushed so that the top surface of the second dielectric layer, the top surface of the first conductive layer, and a top surface of the third electrode are flushed.

[0032] Furthermore, the present disclosure also provides a memory, which includes the semiconductor structure according to any of the above embodiments.

[0033] Furthermore, the present disclosure also provides an electronic device, which includes the memory according to any of the above embodiments.

[0034] The semiconductor structure includes a storage unit, and the storage unit includes two transistors. For ease of explanation, the present disclosure uses a first transistor and a second transistor as an illustration. The first channel layer serves as the channel of the first transistor, the first electrode serves as the gate of the first transistor, and the second electrode and the third electrode serve as the source and drain of the first transistor. The second channel layer serves as the channel of the second transistor, and the second transistor includes two gates, the third electrode and the fourth electrode serve as the two gates of the second transistor, and the second electrode and the fifth electrode serve as the source and drain of the second transistor. In the semiconductor structure, the third electrode serves as the gate of the second transistor, and can therefore serve as a storage node in the semiconductor structure.

[0035] What is significantly different from the conventional technology is that the semiconductor structure provided by the present disclosure designs the second transistor as a dual-gate structure, so that the second electrode can simultaneously serve as the source and drain of the first transistor and the second transistor. Therefore, the second electrode can participate in both writing and reading, which requires only one bit line connected to the second electrode in the semiconductor structure to simultaneously realize the functions of writing and reading. Compared with the conventional technology, the semiconductor structure can reduce one bit line, thereby saving the space and related preparation process required for one bit line, thereby further improving the design density of the transistor and simplifying the preparation process. Furthermore, the use of two gates to control the second transistor can also make the reading operation of the semiconductor structure more flexible.

[0036] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0038] Figure 1 is a schematic diagram of a cross-sectional structure of a semiconductor structure disclosed in the present invention;

[0039] Figure 2 A schematic diagram of the steps of a method for preparing a semiconductor structure disclosed in the present invention;

[0040] Figure 3A Schematic diagram of the top view of the structure of preparing the first electrode on the substrate. Figure 3B for Figure 3A Schematic diagram of the cross-sectional structure at the middle line AA';

[0041] Figure 4A For Figure 3A A schematic diagram of a top view of the structure of the first dielectric layer prepared on the basis of the structure shown in FIG. Figure 4B for Figure 4A Schematic diagram of the cross-sectional structure at the middle line AA';

[0042] Figure 5A For Figure 4A A schematic diagram of a top view of a structure in which a first gate dielectric layer and a first channel layer are prepared based on the structure shown in FIG. Figure 5B for Figure 5A Schematic diagram of the cross-sectional structure at the middle line AA';

[0043] Fig. 6A For Figure 5A A schematic diagram of a top view of the structure of the second dielectric layer prepared on the basis of the structure shown in FIG. Figure 6B for Fig. 6A Schematic diagram of the cross-sectional structure at the middle line AA';

[0044] Fig. 7A For Fig. 6A A schematic diagram of a top view of a structure of preparing a first conductive layer and a third electrode based on the structure shown in FIG. Figure 7B for Fig. 7A Schematic diagram of the cross-sectional structure at the middle line AA';

[0045] Fig. 8A For Fig. 7A A schematic diagram of a top view of the structure of preparing a bottom gate dielectric material layer, a second channel material layer and a top gate dielectric material layer based on the structure shown in FIG. Figure 8B for Fig. 8A Schematic diagram of the cross-sectional structure at the middle line AA';

[0046] Fig.9A For Fig. 8A A schematic diagram of a top view structure of a fourth electrode prepared on the basis of the structure shown, Fig. 9B for Fig.9A Schematic diagram of the cross-sectional structure at the middle line AA';

[0047] Fig. 10A For Fig.9A A schematic diagram of a top view of the structure of the third dielectric layer prepared on the basis of the structure shown in FIG. Fig. 10B for Fig. 10A Schematic diagram of the cross-sectional structure at the middle line AA';

[0048] Fig.11A For Fig. 10A A schematic diagram of a top view structure after patterning the third dielectric layer and etching the top gate dielectric material layer, the second channel material layer and the bottom gate dielectric material layer on the basis of the structure shown in FIG. Fig. 11B for Fig.11A Schematic diagram of the cross-sectional structure at the middle line AA';

[0049] Fig. 12A For Fig.11A A schematic diagram of a top view of a second conductive layer and a fifth electrode prepared on the basis of the structure shown in FIG. Fig. 12B for Fig. 12A Schematic diagram of the cross-sectional structure at the middle line AA';

[0050] Fig.13A For Fig. 12A A schematic diagram of a top view of the structure of the fourth dielectric layer prepared on the basis of the structure shown in FIG. Fig. 13B for Fig.13A Schematic diagram of the cross-sectional structure at the middle line AA';

[0051] Fig.14A For Fig.13A A schematic diagram of a top view of the structure of the bit line conductive layer prepared on the basis of the structure shown in FIG. Fig. 14B for Fig.14A Schematic diagram of the cross-sectional structure at the middle line AA';

[0052] The reference numerals and their meanings are as follows:

[0053] 10. substrate; 11. semiconductor substrate; 12. isolation layer; 100. first channel layer; 110. first gate dielectric layer; 120. electrode contact; 200. second channel layer; 201. second channel material layer; 210. second bottom gate dielectric layer; 211. bottom gate dielectric material layer; 220. second top gate dielectric layer; 221. top gate dielectric material layer; 310. first electrode; 320. second electrode; 321. first conductive layer; 322. second conductive layer; 330. third electrode; 340. fourth electrode; 350. fifth electrode; 360. bit line conductive layer; 410. first dielectric layer; 420. second dielectric layer; 430. third dielectric layer; 440. fourth dielectric layer; 450. protective layer. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0056] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0057] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] The "source and drain" mentioned in this article is a general term for the source and drain of a transistor, and the source and drain usually do not need to be specifically distinguished. When an electrode is used as the source and drain of a transistor, it can be used as both the source and drain of the transistor.

[0060] In conventional technology, a memory cell of a 2T0C structure generally includes two transistors, namely a write transistor and a read transistor. The gate of the write transistor is connected to a write word line (WWL), one source and drain of the write transistor is connected to a write bit line (WBL), and the other source and drain of the write transistor is connected to the gate of the read transistor for writing data to the read transistor. The two sources and drains of the read transistor are connected to a read word line (RWL) and a read bit line (RBL), respectively.

[0061] Figure 1 A semiconductor structure provided by the present disclosure is shown. Figure 1 As shown, the semiconductor structure includes: a first channel layer 100, a second channel layer 200, a first gate dielectric layer 110, a second bottom gate dielectric layer 210, a second top gate dielectric layer 220, a first electrode 310, a second electrode 320, a third electrode 330, a fourth electrode 340 and a fifth electrode 350.

[0062] Among them, the first electrode 310 is disposed on the substrate 10, the first gate dielectric layer 110 and the first channel layer 100 are sequentially stacked on the first electrode 310, the second electrode 320 and the third electrode 330 are both electrically connected to the first channel layer 100, and the second electrode 320 and the third electrode 330 are laterally spaced apart. The second bottom gate dielectric layer 210, the second channel layer 200 and the second top gate dielectric layer 220 are sequentially stacked on the third electrode 330, the fourth electrode 340 is disposed on the second top gate dielectric layer 220, and the second electrode 320 and the fifth electrode 350 are both electrically connected to different regions of the second channel layer 200 and spaced apart.

[0063] It can be understood that the semiconductor structure includes a storage unit, and the storage unit includes two transistors. The first channel layer 100 serves as the channel of the first transistor, the first electrode 310 serves as the gate of the first transistor, and the second electrode 320 and the third electrode 330 serve as the source and drain of the first transistor. The second channel layer 200 serves as the channel of the second transistor, and the second transistor includes two gates, the third electrode 330 and the fourth electrode 340 serve as the two gates of the second transistor, and the second electrode 320 and the fifth electrode 350 serve as the source and drain of the second transistor. In the semiconductor structure, the third electrode 330 serves as the gate of the second transistor, and can therefore serve as a storage node in the semiconductor structure.

[0064] What is significantly different from the conventional technology is that the semiconductor structure provided by the present disclosure designs the second transistor as a dual-gate structure, so that the second electrode 320 can simultaneously serve as the source and drain of the first transistor and the second transistor. Therefore, the second electrode 320 can participate in both writing and reading, which requires only one bit line connected to the second electrode 320 in the semiconductor structure to simultaneously realize the functions of writing and reading. Compared with the conventional technology, the semiconductor structure can reduce one bit line, thus saving the space and related preparation process required for one bit line, thereby further improving the design density of the transistor and simplifying the preparation process. Furthermore, the use of two gates to control the second transistor can also make the reading operation of the semiconductor structure more flexible.

[0065] Reference Figure 1 As shown, in some examples of this embodiment, the second electrode 320 and the third electrode 330 are both disposed on a side of the first channel layer 100 away from the substrate 10, and the second channel layer 200 is disposed between the second electrode 320 and the fifth electrode 350. Further, the second electrode 320 and the fifth electrode 350 may be disposed on both sides of the second channel layer 200. Figure 1, the x-direction and the z-direction perpendicular to each other are shown to assist in understanding the device structure. The second channel layer 200 has a top and a bottom in the z-direction, wherein the end close to the second bottom gate dielectric layer 210 is the bottom, and the end close to the second top gate dielectric layer 220 is the top. The second channel layer 200 also has two side edges between the top and the bottom in the x-direction, and the two side edges of the second channel layer 200 in the x-direction are respectively close to the second electrode 320 and the fifth electrode 350. By setting the positions of the second electrode 320, the third electrode 330, and the fifth electrode 350, the semiconductor structure of the present disclosure can be made easier to be prepared in an integrated preparation process.

[0066] Reference Figure 1 As shown, in some examples of this embodiment, the third electrode 330, the fourth electrode 340, the fifth electrode 350 and the second channel layer 200 form a group of functional components, and the semiconductor structure includes multiple groups of functional components arranged at intervals, the second electrode 320 is arranged between two adjacent groups of functional components, and the second electrode 320 is electrically connected to the two second channel layers 200 in the two groups of functional components. It can be understood that the second electrode 320 has a top and a bottom relative to each other in the z direction, the bottom end of which is arranged close to the substrate 10, and the top end is arranged away from the substrate 10. There are two side edges located in the x direction between the top and the bottom of the second electrode 320, the second electrode 320 is located between the two groups of functional components, and the two sides of the second electrode 320 are respectively close to a group of functional components. In addition, a group of functional components is arranged on both sides of the second electrode 320, which means that the third electrode 330, the fourth electrode 340, the fifth electrode 350 and the second channel layer 200 are arranged on both sides of the second electrode 320.

[0067] It can be understood that the functional component represents a combination of components that participate in forming the second transistor, and the third electrode 330, the fourth electrode 340, the fifth electrode 350, the second channel layer 200 and the second electrode 320 together form the second transistor. The second electrode 320 is disposed between two functional components, and the second electrode 320 can form two second transistors with the two functional components respectively, and the second electrode 320 can control two second channel layers 200 at the same time, that is, the two second transistors can share one second electrode 320, which can further improve the device density in the semiconductor structure.

[0068] Reference Figure 1As shown, the first channel layer 100 is located below the second electrode 320. In some examples of this embodiment, the two third electrodes 330 located on both sides of the second electrode 320 are arranged on the same first channel layer 100 and are electrically connected to the first channel layer 100, and there are also two first electrodes 310, the two first electrodes 310 are arranged at intervals, and the first channel layer 100 is arranged on the side of the two first electrodes 310 away from the substrate 10. It can be understood that the first electrode 310, the second electrode 320, the third electrode 330 and the first channel layer 100 together constitute a first transistor, and the first channel layer 100 is arranged on the two first electrodes 310, and the two third electrodes 330 are arranged on the first channel layer 100, then the two first transistors share one first channel layer 100 and the second electrode 320, which can further improve the device density in the semiconductor structure.

[0069] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure further includes a first dielectric layer 410, the first dielectric layer 410 is disposed between the substrate 10 and the first gate dielectric layer 110, and the first electrode 310 is located in a recessed region of the first dielectric layer 410 away from the substrate 10. Further, the top surface of the first dielectric layer 410 may be flush with the top surface of the first electrode 310. The first dielectric layer 410 is flush with the top surface of the first electrode 310, which enables the first gate dielectric layer 110 and the first channel layer 100 located above to have higher quality. The "top surface" refers to the surface of the side away from the substrate 10.

[0070] Reference Figure 1 As shown, in some examples of this embodiment, the second electrode 320 includes a first conductive layer 321 and a second conductive layer 322. The first conductive layer 321 and the second conductive layer 322 may both include a conductive material, such as a metal. The first conductive layer 321 and the second conductive layer 322 may be divided only in terms of region, which does not mean that there must be a clear boundary between the two layers. The first conductive layer 321 and the second conductive layer 322 are sequentially stacked on the first channel layer 100, the bottom surface of the second conductive layer 322 may be lower than the bottom surface of the second channel layer 200, the top surface of the second conductive layer 322 may be higher than the top surface of the second channel layer 200, and both sides of the second conductive layer 322 protrude from both sides of the first conductive layer 321.

[0071] It can be understood that the two sides of the second conductive layer 322 protrude from the two sides of the first conductive layer 321, and the spacing between the two sides of the second conductive layer 322 is wider than the spacing between the two sides of the first conductive layer 321. Among them, the first conductive layer 321 is arranged on the first channel layer 100, and is used as the source and drain of the first transistor. The second channel layer 200 is arranged on the side of the second conductive layer 322, so the second conductive layer 322 is used as the source and drain of the second transistor. In addition, the second conductive layer 322 is also used to conduct the current entering the first conductive layer 321, so the second conductive layer 322 can be designed to be wider to have better electrical performance.

[0072] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure further includes a second dielectric layer 420, and the second dielectric layer 420 is disposed between the first conductive layer 321 and the third electrode 330. Further, the top surface of the second dielectric layer 420, the top surface of the first conductive layer 321 and the top surface of the third electrode 330 are flush. The second dielectric layer 420 is used to insulate and space the third electrode 330 from the first conductive layer 321. And the second dielectric layer 420 can also fill the gap between the third electrode 330 and the first conductive layer 321, so as to prepare the second bottom gate dielectric layer 210 on the third electrode 330, and prepare the second conductive layer 322 on the first conductive layer 321. The second conductive layer 322 may also have a portion disposed on the second dielectric layer 420.

[0073] In addition, refer to Figure 1 As shown, the second dielectric layer 420 may also be disposed on a side of the third electrode 330 away from the first conductive layer 321 to support the fifth electrode 350 that is subsequently prepared.

[0074] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure further includes a bit line conductive layer 360 , which is disposed on a side of the second electrode 320 away from the substrate 10 and is electrically connected to the second electrode 320 .

[0075] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure further includes a third dielectric layer 430, which is disposed on the second top gate dielectric layer 220 and between the bit line conductive layer 360 and the fourth electrode 340 and between the second electrode 320 and the fourth electrode 340. The third dielectric layer 430 insulates and separates the fourth electrode 340 from the second electrode 320 and the fourth electrode 340 from the bit line conductive layer 360. Further, the third dielectric layer 430 may be coated on the side and top surface of the fourth electrode 340 to protect the fourth electrode 340 and insulate and separate the fourth electrode 340 from the second electrode 320.

[0076] In some examples of this embodiment, the third dielectric layer 430 may have the same pattern as the second top gate dielectric layer 220. In the actual manufacturing process, the third dielectric layer 430 may be used as a mask to etch the patterns of the second top gate dielectric layer 220, the second channel layer 200 and the second bottom gate dielectric layer 210.

[0077] In some examples of this embodiment, the top surface of the third dielectric layer 430 may be flush with the top surface of the second conductive layer 322 .

[0078] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure further includes a fourth dielectric layer 440, which is disposed between the bit line conductive layer 360 and the fifth electrode 350, and the fourth dielectric layer 440 insulates and separates the fifth electrode 350 from the bit line conductive layer 360. Further, the fourth dielectric layer 440 is disposed on a side of the third dielectric layer 430 away from the second electrode 320. The top surface of the fourth dielectric layer 440 is flush with the top surface of the third dielectric layer 430.

[0079] Reference Figure 1 As shown, in some examples of this embodiment, the bottom surface of the fifth electrode 350 is flush with the bottom surface of the second conductive layer 322, and the top surface of the fifth electrode 350 is lower than the top surface of the second conductive layer 322, so that there is a gap between the bit line conductive layer 360 and the fifth electrode 350, and the fourth dielectric layer 440 can be set in the gap.

[0080] Reference Figure 1 As shown, in some examples of this embodiment, a protective layer 450 is further included. The protective layer 450 is disposed on the bit line conductive layer 360. Further, the protective layer 450 may also be disposed on other components that are not shielded by the bit line conductive layer 360, for example, the protective layer 450 may be located on the second dielectric layer 420, the third dielectric layer 430, and the fourth dielectric layer 440.

[0081] Reference Figure 1 As shown, in some examples of this embodiment, the substrate 10 includes a semiconductor substrate 11 and an isolation layer 12 disposed on the semiconductor substrate 11, and the first electrode 310 is disposed on a side of the isolation layer 12 away from the semiconductor substrate 11. It can be understood that the semiconductor substrate 11 may include a logic circuit, or the semiconductor substrate 11 may be used to prepare a logic circuit in a subsequent process. The isolation layer 12 is used to insulate the isolation layer 12 and the semiconductor substrate 11.

[0082] In some examples of this embodiment, the material of the semiconductor substrate 11 may be a semiconductor material, for example, the material of the semiconductor substrate 11 may be one or more of silicon, gallium arsenide, silicon carbide, and germanium.

[0083] In some examples of this embodiment, the material of the isolation layer 12 may be an insulating material. For example, the material of the isolation layer 12 is selected from one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0084] In some examples of this embodiment, the thickness of the isolation layer 12 may be 80 nm to 200 nm. For example, the thickness of the isolation layer 12 may be 80 nm, 100 nm, 120 nm, 150 nm, 200 nm, or the thickness of the isolation layer 12 may be in the range between any two of the above thicknesses.

[0085] In some examples of this embodiment, the material of the protective layer 450 may be selected from insulating materials. For example, the material of the protective layer 450 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the protective layer 450 may be selected from silicon nitride.

[0086] In some examples of this embodiment, the thickness of the protective layer 450 may be 20 nm to 80 nm. For example, the thickness of the protective layer 450 may be 20 nm, 30 nm, 50 nm, 60 nm, or 80 nm, or the thickness of the protective layer 450 may be in the range between any two of the above thicknesses.

[0087] In some examples of this embodiment, the materials of the first dielectric layer 410, the second dielectric layer 420, the third dielectric layer 430 and the fourth dielectric layer 440 can be independently selected from low dielectric constant (low K) materials, and the low dielectric constant materials include one or more of silicon nitride, silicon oxide and silicon oxynitride. In this embodiment, the materials of the first dielectric layer 410, the second dielectric layer 420, the third dielectric layer 430 and the fourth dielectric layer 440 are the same, which are silicon oxide.

[0088] In some examples of this embodiment, the materials of the first channel layer 100 and the second channel layer 200 can be independently selected from semiconductor materials. The semiconductor material can be a silicon material with a band gap less than 2 eV, or a metal oxide semiconductor material with a band gap greater than 2 eV.

[0089] In some examples of this embodiment, the materials of the first channel layer 100 and the second channel layer 200 may include a metal oxide semiconductor material. The metal oxide semiconductor material has a wider band gap and thus has a lower leakage current.

[0090] In some examples of this embodiment, the metal element in the metal oxide semiconductor material may include one or more of indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, and hafnium. For example, the metal oxide semiconductor material may include indium gallium zinc (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InO), and indium zinc oxide (InGaZnSnO). One or more of WO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO) and zirconium zinc tin oxide (ZrZnSnO). In actual use, it is sufficient to ensure that the leakage current performance of the transistor meets the device requirements. In addition, the metal oxide semiconductor material may also contain other doping elements.

[0091] Furthermore, the material of the first channel layer 100 and / or the second channel layer 200 includes indium gallium zinc oxide. Using indium gallium zinc oxide as the material of the channel layer can reduce the leakage current of the channel, thereby further improving the working performance of the transistor.

[0092] In some examples of this embodiment, the thickness of the first channel layer 100 may be 3 nm to 15 nm.

[0093] In some examples of this embodiment, the thickness of the second channel layer 200 may be 3 nm to 20 nm.

[0094] In some examples of this embodiment, the thickness of the first gate dielectric layer 110 may be 3 nm to 10 nm.

[0095] In some examples of this embodiment, the thickness of the second bottom gate dielectric layer 210 may be 3 nm to 10 nm.

[0096] In some examples of this embodiment, the thickness of the second top gate dielectric layer 220 may be 3 nm to 10 nm.

[0097] In some examples of this embodiment, the materials of the first gate dielectric layer 110, the second bottom gate dielectric layer 210, and the second top gate dielectric layer 220 can be independently selected from insulating materials. Further, the materials of the first gate dielectric layer 110, the second bottom gate dielectric layer 210, and the second top gate dielectric layer 220 can be high dielectric constant (high K) materials. The materials of the first gate dielectric layer 110, the second bottom gate dielectric layer 210, and the second top gate dielectric layer 220 can be the same, for example, the first gate dielectric layer 110, the second bottom gate dielectric layer 210, and the second top gate dielectric layer 220 can all be hafnium oxide.

[0098] In some examples of this embodiment, the thickness of the first electrode 310 may be 10 nm to 20 nm. For example, the thickness of the first electrode 310 may be 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, or the thickness of the first electrode 310 may be in the range between any two of the above thicknesses.

[0099] In some examples of this embodiment, the thickness of the first conductive layer 321 and / or the third electrode 330 may be 30 nm to 150 nm. Further, the thickness of the first conductive layer 321 and / or the third electrode 330 may be 30 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, or the thickness of the first conductive layer 321 and / or the third electrode 330 may also be in the range between any two of the above thicknesses.

[0100] In some examples of this embodiment, the thickness of the fourth electrode 340 may be 10 nm to 20 nm. For example, the thickness of the fourth electrode 340 may be 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, or the thickness of the fourth electrode 340 may be in the range between any two of the above thicknesses.

[0101] In some examples of this embodiment, the thickness of the second conductive layer 322 may be 50 nm to 100 nm. For example, the thickness of the second conductive layer 322 may be 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, or the thickness of the second conductive layer 322 may be in the range between any two of the above thicknesses.

[0102] In some examples of this embodiment, the thickness of the fifth electrode 350 is 10nm to 50nm. For example, the thickness of the fifth electrode 350 can be 10nm, 20nm, 30nm, 40nm, 50nm, or the thickness of the fifth electrode 350 can also be in the range between any two of the above thicknesses. Further, the top surface of the fifth electrode 350 protrudes from the top surface of the second channel layer 200 to ensure normal conduction of the channel.

[0103] It can be understood that the materials of the first electrode 310, the second electrode 320, the third electrode 330, the fourth electrode 340 and the fifth electrode 350 are conductive materials. In some examples of this embodiment, the materials of the first electrode 310, the second electrode 320, the third electrode 330, the fourth electrode 340 and the fifth electrode 350 can be independently selected from metals or heavily doped semiconductor materials. In this embodiment, the materials of the first electrode 310, the second electrode 320, the third electrode 330, the fourth electrode 340 and the fifth electrode 350 are metals. For example, the materials of the first electrode 310, the second electrode 320, the third electrode 330, the fourth electrode 340 and the fifth electrode 350 can include one or more of platinum, gold, tungsten and copper.

[0104] In some examples of this embodiment, the semiconductor structure may further include an electrode contact 120. The electrode contact 120 may be disposed on the first channel layer 100, for example, the electrode contact 120 may be disposed between the first channel layer 100 and the second electrode 320, or between the first channel layer 100 and the third electrode 330. The electrode contact 120 may effectively reduce the contact resistance between the first channel layer 100 and the electrode located thereon.

[0105] In some examples of this embodiment, the material of the electrode contact 120 may include a metal oxide semiconductor. For example, the material of the electrode contact 120 may be indium tin oxide.

[0106] In some examples of this embodiment, the thickness of the electrode contact 120 may be 1 nm to 5 nm.

[0107] It is understandable that Figure 1 The semiconductor structure shown contains two second transistors and two first transistors, and the two second transistors and the two first transistors can share the same second electrode 320 and the first channel layer 100. Figure 1 The semiconductor structure shown contains two memory cells, and the two memory cells can be controlled by the same bit line.

[0108] Furthermore, the present disclosure also provides a memory, which includes the semiconductor structure provided by the present disclosure. In some embodiments, the semiconductor structure provided by the present disclosure can constitute a repeating unit of the memory, and the memory can be integrated with multiple repeating units. Generally, a repeating unit can contain one storage unit. Figure 1 In the semiconductor structure shown, one repeating unit may contain two memory cells.

[0109] Furthermore, the present disclosure also provides an electronic device, which may include the above-mentioned memory. Furthermore, the electronic device may be, but is not limited to, a mobile phone and a computer.

[0110] Figure 2 A method for preparing a semiconductor structure disclosed in the present invention is shown, which includes steps S1 to S5, as follows.

[0111] Step S1 : preparing a first electrode 310 on a substrate 10 .

[0112] Figure 3A FIG. 1 is a schematic diagram of a top view of a structure of preparing a first electrode 310 on a substrate 10. Figure 3B for Figure 3A Schematic diagram of the cross-sectional structure at the middle line AA'. In order to facilitate the understanding of the relative position relationship of each component, Figure 3A The x and y directions are marked in Figure 3B The x-direction and the z-direction are marked, and the three directions x, y, and z are perpendicular to each other. In this embodiment, the bit line is along the x-direction, and the write word line and the read word line are along the y-direction. For ease of understanding, the "side" in this article refers to the relative position relationship in the x-direction, and the "upper", "lower", "top" and "bottom" in this article refer to the position relationship in the z-direction.

[0113] In some examples of this embodiment, preparing the first electrode 310 on the substrate 10 may include the following steps: providing a substrate 10 including a semiconductor substrate 11 and an isolation layer 12, and preparing the first electrode 310 on a side of the isolation layer 12 away from the semiconductor substrate 11. It can be understood that the semiconductor substrate 11 may include a logic circuit, or the semiconductor substrate 11 may be used to prepare a logic circuit in a subsequent process. The isolation layer 12 is used to insulate the isolation layer 12 and the semiconductor substrate 11.

[0114] Reference Figure 3A and Figure 3B As shown, in some examples of this embodiment, the substrate 10 may include a semiconductor substrate 11 and an isolation layer 12 disposed on the semiconductor substrate 11. The material of the semiconductor substrate 11 may be a semiconductor material, for example, the material of the semiconductor substrate 11 may be one or more of silicon, gallium arsenide, silicon carbide and germanium.

[0115] In some examples of this embodiment, the material of the isolation layer 12 may be an insulating material. For example, the material of the isolation layer 12 is selected from one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0116] In some examples of this embodiment, the material of the semiconductor substrate 11 may be silicon, and the material of the isolation layer 12 may be silicon oxide. Further, the isolation layer 12 may be prepared by oxidizing the surface of the semiconductor substrate 11, or the isolation layer 12 may be prepared on the surface of the semiconductor substrate 11 by deposition.

[0117] In some examples of this embodiment, before preparing the isolation layer 12 , a step of cleaning the semiconductor substrate 11 may be further included to remove impurities and dust on the surface of the semiconductor substrate 11 .

[0118] In some examples of this embodiment, the thickness of the isolation layer 12 may be 80 nm to 200 nm.

[0119] In some examples of this embodiment, the material of the first electrode 310 may be a metal or a heavily doped semiconductor material. In this embodiment, the material of the first electrode 310 is a metal. For example, the material of the first electrode 310 may include one or more of platinum, gold, tungsten, and copper.

[0120] In some examples of this embodiment, preparing the first electrode 310 may include: preparing two first electrodes 310 spaced apart on the substrate 10. Further, in order to prepare the first electrodes 310 spaced apart, preparing the first electrode 310 may include: depositing a first electrode 310 material layer on the substrate 10, and patterning the deposited first electrode 310 material layer to form a patterned first electrode 310. It can be understood that by patterning the first electrode 310 material layer, not only the position of the first electrode 310 can be defined, but also a plurality of first electrodes 310 can be formed simultaneously on the surface of the substrate 10.

[0121] Reference Figure 3A As shown, in some examples of this embodiment, the extension direction of the first electrode 310 is along the y direction, and the plurality of first electrodes 310 are arranged in sequence in the x direction. It can be understood that in this step, the prepared first electrode 310 can be used as a write word line, or the first electrode 310 can be electrically connected to the write word line.

[0122] In some examples of this embodiment, the step of patterning the first electrode 310 material layer may include: preparing a photoresist layer on the first electrode 310 material layer, performing exposure and development processing on the photoresist layer, and then etching the first electrode 310 material layer based on the photoresist layer, so that the remaining part of the first electrode 310 material layer serves as the first electrode 310. When etching the first electrode 310 material layer, the isolation layer 12 may be used as an etching stop layer.

[0123] In some examples of this embodiment, the thickness of the first electrode 310 may be 10 nm to 20 nm.

[0124] Figure 4A For Figure 3A A schematic diagram of a top view of a first dielectric layer 410 is prepared based on the structure shown in FIG. Figure 4B for Figure 4A Schematic diagram of the cross-sectional structure at the middle line AA'. Figure 4A and Figure 4B As shown, in some examples of this embodiment, after preparing the first electrode 310 , the method further includes: preparing a first dielectric layer 410 flush with the top surface of the first electrode 310 on the substrate 10 .

[0125] In order to make the top surface of the first dielectric layer 410 flush with the top surface of the first electrode 310, a step of flattening the surface of the first dielectric layer 410 and the first electrode 310 may be included. The flattening method may be chemical mechanical flattening (CMP). By providing the first dielectric layer 410, the vacancies between the plurality of first electrodes 310 can be filled, and the first dielectric layer 410 and the first electrode 310 as a whole have a flat surface. In addition, the first dielectric layer 410 can also insulate and space adjacent first electrodes 310.

[0126] In some examples of this embodiment, the material of the first dielectric layer 410 may be selected from low dielectric constant (low K) materials, for example, the material of the first dielectric layer 410 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the first dielectric layer 410 may be silicon oxide.

[0127] In some examples of this embodiment, the first dielectric layer 410 may be prepared to be thicker than the first electrode 310 , and then, during the chemical mechanical polishing process, the thickness of the first dielectric layer 410 is made the same as that of the first electrode 310 .

[0128] Step S2 , sequentially forming a first gate dielectric layer 110 and a first channel layer 100 on the first electrode 310 .

[0129] Figure 5A For Figure 4A A schematic diagram of a top view of the structure of the first gate dielectric layer 110 and the first channel layer 100 is prepared on the basis of the structure shown in FIG. Figure 5B for Figure 5A Schematic diagram of the cross-sectional structure along AA'.

[0130] Reference Figure 5A and Figure 5B As shown, the first gate dielectric layer 110 is located between the first channel layer 100 and the first electrode 310 , and insulates and separates the first channel layer 100 and the first electrode 310 .

[0131] In some examples of this embodiment, the material of the first gate dielectric layer 110 may be an insulating material. Further, the material of the first gate dielectric layer 110 may be a high dielectric constant (high K) material, for example, the material of the first gate dielectric layer 110 may include hafnium oxide.

[0132] In some examples of this embodiment, the thickness of the first gate dielectric layer 110 may be 3 nm to 10 nm. In order to ensure the quality of the first gate dielectric layer 110 at this thickness, the first gate dielectric layer 110 may be prepared by atomic layer deposition.

[0133] In some examples of this embodiment, the first gate dielectric layer 110 may be formed on the entire substrate 10 , so that the resulting structure still has a flat surface after forming the first gate dielectric layer 110 .

[0134] In some examples of this embodiment, the first gate dielectric layer 110 and the first channel layer 100 cover the two first electrodes 310 , so that the two first electrodes 310 can share the same first channel layer 100 .

[0135] In some examples of this embodiment, the material of the first channel layer 100 may be a semiconductor material. Further, the material of the first channel layer 100 is a metal conductive oxide. For example, the material of the first channel layer 100 may be indium gallium zinc oxide (IGZO). The ratio of each metal element and oxygen defects in the indium gallium zinc oxide may be prepared according to actual device requirements.

[0136] In some examples of this embodiment, the thickness of the first channel layer 100 may be 3 nm to 15 nm. In order to ensure the quality of the first channel layer 100 at this thickness, the first channel layer 100 may be prepared by atomic layer deposition or physical vapor deposition.

[0137] In some examples of this embodiment, the step of preparing the first channel layer 100 includes: depositing a material of the first channel layer 100 on the first gate dielectric layer 110 , and then patterning the material of the first channel layer 100 to form the first channel layer 100 .

[0138] It can be understood that by patterning the material of the first channel layer 100, not only the position of the first channel layer 100 can be defined, but also a plurality of first channel layers 100 can be formed simultaneously on the surface of the substrate 10. Figure 5A and Figure 5B As shown, in some examples of this embodiment, the first channel layer 100 extends in the x direction and is arranged in sequence in the y direction. Further, the first channel layer 100 can be simultaneously prepared on two adjacent first electrodes 310 to further improve the density of the transistor.

[0139] In some examples of this embodiment, the step of patterning the material of the first channel layer 100 may include: preparing a photoresist layer on the surface of the material of the first channel layer 100, exposing and developing the photoresist layer, and then etching the material of the first channel layer 100 based on the photoresist layer. When etching the material of the first channel layer 100, the first gate dielectric layer 110 may be used as an etching stop layer.

[0140] Step S3 , forming a first conductive layer 321 and a third electrode 330 on the first channel layer 100 .

[0141] In this embodiment, the first conductive layer 321 serves as a part of the second electrode 320 and is used to participate in forming the second electrode 320 .

[0142] In some examples of this embodiment, preparing the first conductive layer 321 and the third electrode 330 spaced apart on the first channel layer 100 includes: preparing a patterned second dielectric layer 420 on the first channel layer 100, and depositing the material of the first conductive layer 321 and the material of the third electrode 330 on the first channel layer 100 based on the pattern of the second dielectric layer 420 to form the first conductive layer 321 and the third electrode 330, respectively; and performing a flush treatment on the top surface of the second dielectric layer 420, the top surface of the first conductive layer 321, and the top surface of the third electrode 330, so that the top surface of the second dielectric layer 420, the top surface of the first conductive layer 321, and the top surface of the third electrode 330 are flush.

[0143] In some examples of this embodiment, the material of the second dielectric layer 420 may be selected from low dielectric constant (low K) materials, for example, the material of the second dielectric layer 420 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the second dielectric layer 420 may be silicon oxide.

[0144] Fig. 6A For Figure 5A A schematic diagram of a top view of the structure of the second dielectric layer 420 is prepared based on the structure shown in FIG. Figure 6B for Fig. 6A Schematic diagram of the cross-sectional structure at the middle line AA'.

[0145] Reference Fig. 6A and Figure 6B As shown, the second dielectric layer 420 has an opening, and the first channel layer 100 is exposed in the opening of the second dielectric layer 420 . The opening of the second dielectric layer 420 is used to define the positions of the first conductive layer 321 and the third electrode 330 .

[0146] In some examples of this embodiment, the step of preparing the patterned second dielectric layer 420 may include: preparing the second dielectric layer 420 on the first channel layer 100, preparing a photoresist layer on the second dielectric layer 420, performing exposure and development processing on the photoresist layer, and then etching the second dielectric layer 420 based on the photoresist layer to form the patterned second dielectric layer 420. When etching the second dielectric layer 420, the first channel layer 100 may be used as a stop layer.

[0147] Reference Fig. 6A and Figure 6B As shown, in some examples of this embodiment, the patterned second dielectric layer 420 shields the first electrode 310 , so that the first conductive layer 321 and the third electrode 330 prepared subsequently are located on both sides of the first electrode 310 , respectively.

[0148] Fig. 7A For Fig. 6A A schematic diagram of a top view structure of a first conductive layer 321 and a third electrode 330 is prepared based on the structure shown in FIG. Figure 7B for Fig. 7A Schematic diagram of the cross-sectional structure at the middle line AA'.

[0149] Reference Fig. 7A and Figure 7B As shown, in some examples of this embodiment, the thickness of the first conductive layer 321 and / or the third electrode 330 may be 30 nm to 150 nm.

[0150] In some examples of this embodiment, the materials of the first conductive layer 321 and the third electrode 330 can be independently selected from conductive materials. The conductive material can be a metal or a heavily doped semiconductor material. In this embodiment, the materials of the first conductive layer 321 and the third electrode 330 are both metals. For example, the materials of the first conductive layer 321 and the third electrode 330 can independently include one or more of platinum, gold, tungsten and copper.

[0151] It can be understood that the first conductive layer 321 and the third electrode 330 serve as the source and drain of the first transistor. For ease of preparation, in some examples of this embodiment, the material of the first conductive layer 321 is the same as the material of the third electrode 330. Further, the first conductive layer 321 can be prepared simultaneously with the third electrode 330. For example, a metal material is deposited in the opening of the second dielectric layer 420 to serve as the first conductive layer 321 and the third electrode 330, respectively.

[0152] Reference Fig. 7A and Figure 7BAs shown, both sides of the first conductive layer 321 have a first channel layer 100, and there are two first electrodes 310 and two third electrodes 330. The two first electrodes 310 are respectively located on both sides of the first conductive layer 321, and the two third electrodes 330 are also respectively located on both sides of the first conductive layer 321, so that the first conductive layer 321 is shared by the two first transistors, which can further improve the density of the transistor.

[0153] In some examples of this embodiment, before preparing the first conductive layer 321 and the third electrode 330, a step of preparing an electrode contact 120 on the first channel layer 100 is also included. Fig. 7A and Figure 7B As shown, the electrode contact 120 is disposed between the first conductive layer 321 and the first channel layer 100, and the electrode contact 120 is also disposed between the third electrode 330 and the first channel layer 100. The electrode contact 120 is used to reduce the contact resistance between the first conductive layer 321 and the first channel layer 100 and between the third electrode 330 and the first channel layer 100.

[0154] In some examples of this embodiment, the material of the electrode contact 120 may include a metal oxide semiconductor. For example, the material of the electrode contact 120 may be indium tin oxide.

[0155] In some examples of this embodiment, the thickness of the electrode contact 120 may be 1 nm to 5 nm.

[0156] In some examples of this embodiment, the electrode contact 120 may be prepared by physical vapor deposition.

[0157] In some examples of this embodiment, after preparing the first conductive layer 321 and the third electrode 330, a step of flattening the top surfaces of the first conductive layer 321, the third electrode 330 and the second dielectric layer 420 may be included, so that the top surface of the second dielectric layer 420, the top surface of the first conductive layer 321 and the top surface of the third electrode 330 are flush. The flattening method may be chemical mechanical polishing. It is understood that the second dielectric layer 420 can not only be used as a mask for preparing the first conductive layer 321 and the third electrode 330, but also can be used to fill the gap between the first conductive layer 321 and the third electrode 330 to ensure that the first conductive layer 321 and the third electrode 330 have a flat surface as a whole.

[0158] Step S4 , sequentially forming a second bottom gate dielectric layer 210 , a second channel layer 200 , a second top gate dielectric layer 220 and a fourth electrode 340 on the third electrode 330 .

[0159] In some examples of this embodiment, the steps of sequentially preparing a second bottom gate dielectric layer 210, a second channel layer 200, a second top gate dielectric layer 220 and a fourth electrode 340 on the third electrode 330 include: sequentially preparing a bottom gate dielectric material layer 211, a second channel material layer 201 and a top gate dielectric material layer 221 on the first conductive layer 321 and the two third electrodes 330; preparing two fourth electrodes 340 spaced apart on the top gate dielectric material layer 221; and sequentially etching the top gate dielectric material layer 221, the second channel material layer 201 and the bottom gate dielectric material layer 211 located above the first conductive layer 321 to form an electrode opening exposing the first conductive layer 321, and forming two second top gate dielectric layers 220, two second channel layers 200 and two second top gate dielectric layers 220 on both sides of the electrode opening, respectively, and the two fourth electrodes 340 are respectively arranged on the two second top gate dielectric layers 220.

[0160] Fig. 8A For Fig. 7A A schematic diagram of a top view of a structure in which a bottom gate dielectric material layer 211, a second channel material layer 201 and a top gate dielectric material layer 221 are prepared on the basis of the structure shown in FIG. Figure 8B for Fig. 8A Schematic diagram of the cross-sectional structure at the middle line AA'.

[0161] Reference Fig. 8A and Figure 8B As shown, in some examples of this embodiment, the bottom gate dielectric material layer 211 covers the second dielectric layer 420, the third electrode 330 and the first conductive layer 321. The bottom gate dielectric material layer 211 has a flat surface. The second channel material layer 201 and the top gate dielectric material layer 221 are both disposed on the bottom gate dielectric material layer 211. Fig. 8A and Figure 8B As shown, the top gate dielectric material layer 221 and the second channel material layer 201 both extend along the x-direction, and there are multiple top gate dielectric material layers 221 and second channel material layers 201, multiple top gate dielectric material layers 221 are arranged in sequence at intervals in the y-direction, and multiple second channel material layers 201 are arranged in sequence at intervals in the y-direction.

[0162] It is understood that the top gate dielectric material layer 221 and the second channel material layer 201 can be formed by patterning. During the patterning, the bottom gate dielectric material layer 211 can be used as an etching stop layer.

[0163] In some examples of this embodiment, the materials of the bottom gate dielectric material layer 211 and the top gate dielectric material layer 221 can be independently selected from insulating materials. Further, the materials of the bottom gate dielectric material layer 211 and the top gate dielectric material layer 221 can be high dielectric constant (high K) materials. The materials of the bottom gate dielectric material layer 211 and the top gate dielectric material layer 221 can be the same, for example, the bottom gate dielectric material layer 211 and the top gate dielectric material layer 221 can both be hafnium oxide.

[0164] In some examples of this embodiment, the thickness of the bottom gate dielectric material layer 211 may be 3 nm to 10 nm.

[0165] In some examples of this embodiment, the thickness of the top gate dielectric material layer 221 may be 3 nm to 10 nm.

[0166] In some examples of this embodiment, the bottom gate dielectric material layer 211 may be prepared by atomic layer deposition. In some examples of this embodiment, the top gate dielectric material layer 221 may be prepared by atomic layer deposition.

[0167] In some examples of this embodiment, the material of the second channel material layer 201 may be a semiconductor material. Further, the material of the second channel material layer 201 may include a metal oxide semiconductor. For example, the material of the second channel material layer 201 may include indium gallium zinc oxide. In this embodiment, the material of the second channel material layer 201 may be the same as the material of the first channel layer 100.

[0168] In some examples of this embodiment, the thickness of the second channel material layer 201 may be 3 nm to 20 nm. To ensure the quality of the second channel material layer 201 at this thickness, the second channel material layer 201 may be prepared by atomic layer deposition or physical vapor deposition.

[0169] Fig.9A For Fig. 8A A schematic diagram of a top view structure of a fourth electrode 340 is prepared based on the structure shown in FIG. Fig. 9B for Fig.9A Schematic diagram of the cross-sectional structure along AA'.

[0170] In some examples of this embodiment, the material of the fourth electrode 340 may be a metal or a heavily doped semiconductor material. In this embodiment, the material of the fourth electrode 340 is a metal. For example, the material of the fourth electrode 340 may include one or more of platinum, gold, tungsten, and copper.

[0171] In some examples of this embodiment, the thickness of the fourth electrode 340 may be 10 nm to 20 nm.

[0172] In some examples of this embodiment, preparing the fourth electrode 340 may include: depositing material for the fourth electrode 340 on the bottom gate dielectric material layer 211 and the top gate dielectric material layer 221, and patterning the deposited material for the fourth electrode 340 to form two fourth electrodes 340 spaced apart.

[0173] Reference Fig.9A and Fig. 9B As shown, in some examples of this embodiment, the fourth electrode 340 and the third electrode 330 extend in the same direction, both along the y direction, and a plurality of fourth electrodes 340 are arranged in sequence in the x direction. It can be understood that in this step, the prepared fourth electrode 340 can be used as a read word line, or the fourth electrode 340 can be electrically connected to the read word line.

[0174] Reference Fig.9A and Fig. 9B As shown, the fourth electrode 340 is prepared on the top gate dielectric material layer 221. In some examples of this embodiment, at least a portion of the fourth electrode 340 is located directly above the third electrode 330. Further, the fourth electrode 340 is located directly above the third electrode 330 as a whole.

[0175] Fig. 10A For Fig.9A A schematic top view of the structure of the third dielectric layer 430 is prepared based on the structure shown in FIG. Fig. 10B for Fig. 10A Schematic diagram of the cross-sectional structure at the middle line AA'. Fig. 10A and Fig. 10B As shown, the third dielectric layer 430 covers the top gate dielectric material layer 221 and the fourth electrode 340 .

[0176] In some examples of this embodiment, the material of the third dielectric layer 430 may be selected from low dielectric constant (low K) materials, for example, the material of the third dielectric layer 430 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the third dielectric layer 430 may be silicon oxide.

[0177] Fig.11A For Fig. 10A A schematic diagram of a top view structure after patterning the third dielectric layer 430 and etching the top gate dielectric material layer 221, the second channel material layer 201 and the bottom gate dielectric material layer 211 based on the structure shown in FIG. Fig. 11B for Fig.11A Schematic diagram of the cross-sectional structure at the middle line AA'. Fig.11A and Fig. 11BAs shown, the third dielectric layer 430 has an opening after patterning, and the top gate dielectric material layer 221, the second channel material layer 201 and the bottom gate dielectric material layer 211 located below the opening are etched and removed to form an electrode opening for preparing the second conductive layer 322. The top gate dielectric material layer 221 forms two second top gate dielectric layers 220 disposed on both sides of the electrode opening, the second channel material layer 201 forms two second channel layers 200 disposed on both sides of the electrode opening, and the bottom gate dielectric material layer 211 forms two second bottom gate dielectric layers 210 disposed on both sides of the electrode opening. In this way, two second transistors can be formed more easily, and the two second transistors can be controlled by a common second electrode 320.

[0178] When etching the bottom gate dielectric material layer 211 , the second dielectric layer 420 and the first conductive layer 321 may be used as etching stop layers.

[0179] Step S5 , forming a second conductive layer 322 on the first conductive layer 321 , and forming a fifth electrode 350 on a side of the second channel layer 200 away from the second conductive layer 322 .

[0180] Fig. 12A For Fig.11A A schematic diagram of a top view of the structure of the second conductive layer 322 and the fifth electrode 350 is prepared on the basis of the structure shown in FIG. Fig. 12B for Fig. 12A Schematic diagram of the cross-sectional structure at the middle line AA'. Fig. 12A and Fig. 12B As shown, the second conductive layer 322 is located on the first conductive layer 321 and contacts the first conductive layer 321, and the fifth electrode 350 is located on a side of the second channel layer 200 away from the second conductive layer 322 and is insulated and spaced apart from the second conductive layer 322. In this embodiment, the second conductive layer 322 serves as a part of the second electrode 320, and the second conductive layer 322 and the first conductive layer 321 jointly form the second electrode 320.

[0181] In some examples of this embodiment, the second conductive layer 322 is prepared in the electrode opening, and the two sides of the second conductive layer 322 protrude from the two sides of the first conductive layer 321. It can be understood that by designing the electrode opening with wider sides, the two sides of the second conductive layer 322 can protrude from the two sides of the first conductive layer 321.

[0182] In some examples of this embodiment, the materials of the second conductive layer 322 and the fifth electrode 350 can be independently selected from conductive materials. The conductive material can be a metal or a heavily doped semiconductor material. In this embodiment, the materials of the second conductive layer 322 and the fifth electrode 350 are both metals. For example, the materials of the second conductive layer 322 and the fifth electrode 350 can each independently include one or more of platinum, gold, tungsten and copper.

[0183] It can be understood that the second conductive layer 322 and the fifth electrode 350 serve as the source and drain of the second transistor. For ease of preparation, in some examples of this embodiment, the material of the second conductive layer 322 is the same as the material of the fifth electrode 350. Further, the second conductive layer 322 can be prepared simultaneously with the fifth electrode 350. For example, a metal material is deposited in the opening of the third dielectric layer 430 to serve as the material of the second conductive layer 322 and the fifth electrode 350, respectively.

[0184] In some examples of this embodiment, after preparing the materials of the second conductive layer 322 and the fifth electrode 350, a step of etching back the materials of the second conductive layer 322 and the fifth electrode 350 may be further included. Fig.11A As shown, the top surface area of ​​the second conductive layer 322 can be controlled to be larger than the top surface area of ​​the fifth electrode 350, so as to utilize the etching load effect, so that the etching speed of the fifth electrode 350 is greater than the etching speed of the second conductive layer 322, so that the thickness of the second conductive layer 322 is greater than the thickness of the fifth electrode 350, and the top surface of the fifth electrode 350 is lower than the top surface of the second conductive layer 322.

[0185] In some examples of this embodiment, the thickness of the second conductive layer 322 may be 50 nm to 100 nm.

[0186] In some examples of this embodiment, the thickness of the fifth electrode 350 is 10 nm to 50 nm.

[0187] In some examples of this embodiment, after preparing the second conductive layer 322 and the fifth electrode 350 , a step of forming a fourth dielectric layer 440 on the fifth electrode 350 may be further included. Fig.13A For Fig. 12A A schematic diagram of a top view of a fourth dielectric layer 440 prepared on the basis of the structure shown in FIG. Fig. 13B for Fig.13A It can be understood that the fourth dielectric layer 440 covers the fifth electrode 350 and is used to separate the second electrode 320 from other materials prepared subsequently.

[0188] In some examples of this embodiment, after preparing the fourth dielectric layer 440, the fourth dielectric layer 440, the third dielectric layer 430 and the second conductive layer 322 may be flushed so that the top surface of the fourth dielectric layer 440 and the top surface of the third dielectric layer 430 are flush with the top surface of the second conductive layer 322. The flushing process may be performed by chemical mechanical polishing.

[0189] In some examples of this embodiment, the materials of the first dielectric layer 410, the second dielectric layer 420, the third dielectric layer 430 and the fourth dielectric layer 440 may be the same. For example, the materials of the first dielectric layer 410, the second dielectric layer 420, the third dielectric layer 430 and the fourth dielectric layer 440 may all be silicon oxide.

[0190] Furthermore, in some examples of this embodiment, after the second conductive layer 322 is prepared, the following step may be further included: preparing a bit line conductive layer 360 on the second conductive layer 322 . Fig.14A For Fig.13A A schematic diagram of a top view of a bit line conductive layer 360 is prepared based on the structure shown in FIG. Fig. 14B for Fig.14A Schematic diagram of the cross-sectional structure at the middle line AA'.

[0191] Reference Fig.14A and Fig. 14B As shown, the bit line conductive layer 360 contacts the second conductive layer 322. An external circuit can be electrically connected to the second conductive layer 322 through the bit line conductive layer 360 to control the first transistor and the second transistor.

[0192] Reference Fig.14A and Fig. 14B As shown, in some examples of this embodiment, the extension direction of the bit line conductive layer 360 is along the x direction, and a plurality of bit line conductive layers 360 are arranged in sequence in the y direction. It can be understood that in this step, the prepared bit line conductive layer 360 can be used as a bit line, or the bit line conductive layer 360 can be electrically connected to the bit line.

[0193] In some examples of this embodiment, the thickness of the bit line conductive layer 360 may be 10 nm to 20 nm. The bit line conductive layer 360 may be prepared by chemical vapor deposition or physical vapor deposition.

[0194] In some examples of this embodiment, the material of the bit line conductive layer 360 can be selected from a conductive material. The conductive material can be a metal or a heavily doped semiconductor material. In this embodiment, the material of the bit line conductive layer 360 is a metal. For example, the material of the bit line conductive layer 360 can include one or more of platinum, gold, tungsten, and copper.

[0195] In some examples of this embodiment, the materials of the first conductive layer 321 , the second conductive layer 322 , and the bit line conductive layer 360 may be the same.

[0196] Further, in some examples of this embodiment, after preparing the bit line conductive layer 360, a step of preparing a protective layer 450 may be further included. In some examples of this embodiment, the protective layer 450 may cover the bit line conductive layer 360 and be used to protect the bit line conductive layer 360. Further, the protective layer 450 may also cover a structure not covered by the bit line conductive layer 360.

[0197] In some examples of this embodiment, the material of the protective layer 450 may be selected from insulating materials. For example, the material of the protective layer 450 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the protective layer 450 may be selected from silicon nitride.

[0198] In some examples of this embodiment, the thickness of the protection layer 450 may be 20 nm to 80 nm.

[0199] It can be understood that through the specific description of the above steps S1 to S5, the following can be prepared: Figure 1 The semiconductor structure shown.

[0200] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0201] It should be understood that, unless otherwise specified herein, the execution of the steps described is not strictly limited in order, and the steps may be executed in other orders. Moreover, at least a portion of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0202] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0203] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A semiconductor structure, characterized in that: include: A first channel layer, a second channel layer, a first gate dielectric layer, a second bottom gate dielectric layer, a second top gate dielectric layer, a first electrode, a second electrode, a third electrode, a fourth electrode and a fifth electrode; The first electrode is disposed on the substrate, the first gate dielectric layer and the first channel layer are sequentially stacked on the first electrode, the second electrode and the third electrode are both electrically connected to the first channel layer, and the second electrode and the third electrode are laterally spaced apart; The second bottom gate dielectric layer, the second channel layer and the second top gate dielectric layer are sequentially stacked on the third electrode, the fourth electrode is disposed on the second top gate dielectric layer, and the second electrode and the fifth electrode are electrically connected to different regions of the second channel layer and are spaced apart.

2. The semiconductor structure according to claim 1, characterized in that: The second electrode and the third electrode are both arranged on a side of the first channel layer away from the substrate, and the second channel layer is arranged between the second electrode and the fifth electrode.

3. The semiconductor structure according to claim 2, characterized in that: The third electrode, the fourth electrode, the fifth electrode and the second channel layer form a group of functional components. The semiconductor structure includes multiple groups of the functional components arranged at intervals. The second electrode is arranged between two adjacent groups of the functional components, and the second electrode is electrically connected to two of the second channel layers in the two groups of the functional components.

4. The semiconductor structure according to claim 3, characterized in that: The two third electrodes located on both sides of the second electrode are arranged on the same first channel layer. There are also two first electrodes, which are arranged at intervals. The first channel layer is arranged on a side of the two first electrodes away from the substrate.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The semiconductor structure further includes a first dielectric layer, which is disposed between the substrate and the first gate dielectric layer, and the first electrode is located in a recessed region of the first dielectric layer on a side away from the substrate.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The second electrode includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are sequentially stacked on the first channel layer, the bottom surface of the second conductive layer is lower than the bottom surface of the second channel layer, the top surface of the second conductive layer is higher than the top surface of the second channel layer, and both sides of the second conductive layer protrude from both sides of the first conductive layer.

7. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The semiconductor structure further includes a bit line conductive layer, which is disposed on the second electrode and electrically connected to the second electrode.

8. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The material of the first channel layer and / or the material of the second channel layer includes a metal oxide semiconductor material with a band gap greater than 2 eV.

9. A method for preparing a semiconductor structure according to any one of claims 1 to 8, characterized in that: The steps include: preparing the first electrode on the substrate; sequentially forming the first gate dielectric layer and the first channel layer on the first electrode; preparing a first conductive layer and the third electrode on the first channel layer; The second bottom gate dielectric layer, the second channel layer, the second top gate dielectric layer and the fourth electrode are sequentially formed on the third electrode, wherein the first conductive layer is exposed on a side of the second channel layer; A second conductive layer is formed on the first conductive layer, and the fifth electrode is formed on a side of the second channel layer away from the second conductive layer. The second electrode includes the first conductive layer and the second conductive layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: In the step of preparing the first conductive layer and the third electrode on the first channel layer, two third electrodes are prepared and are respectively arranged on both sides of the first conductive layer; The step of sequentially preparing the second bottom gate dielectric layer, the second channel layer, the second top gate dielectric layer and the fourth electrode on the third electrode comprises: Sequentially preparing a bottom gate dielectric material layer, a second channel material layer and a top gate dielectric material layer on the first conductive layer and the two third electrodes; preparing two fourth electrodes spaced apart from each other on the top gate dielectric material layer; and, The top gate dielectric material layer, the second channel material layer and the bottom gate dielectric material layer located above the first conductive layer are etched in sequence to form an electrode opening exposing the first conductive layer, and two second top gate dielectric layers, two second channel layers and two second top gate dielectric layers are formed on both sides of the electrode opening, respectively, and the two fourth electrodes are respectively arranged on the two second top gate dielectric layers.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The second conductive layer is prepared in the electrode opening, and two sides of the second conductive layer protrude from two sides of the first conductive layer.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that: The step of preparing the first electrode on the substrate includes: preparing two first electrodes spaced apart from each other on the substrate; and covering the two first electrodes with the first gate dielectric layer and the first channel layer.

13. The method for preparing a semiconductor structure according to any one of claims 9 to 12, characterized in that: The step of preparing a first conductive layer and the third electrode on the first channel layer comprises: preparing a patterned second dielectric layer on the first channel layer; Based on the pattern of the second dielectric layer, depositing the material of the first conductive layer and the material of the third electrode on the first channel layer to form the first conductive layer and the third electrode respectively; A top surface of the second dielectric layer, a top surface of the first conductive layer, and a top surface of the third electrode are flushed so that the top surface of the second dielectric layer, the top surface of the first conductive layer, and a top surface of the third electrode are flushed.

14. A memory, characterized in that: Comprising the semiconductor structure according to any one of claims 1 to 8.

15. An electronic device, characterized in that: Comprising a memory according to claim 14.

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