Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system are provided. The semiconductor device may include a substrate including a cell array region and a connection region; a stacked structure including a conductive pattern stacked on the substrate; an internal support extending into the stack structure in the connection region; a contact plug extending into a portion of the stacked structure and electrically connected to one of the conductive patterns, and extending at least partially around the inner support in a plan view; an insulating spacer between the contact plug and the stack structure and extending at least partially around the contact plug; and an outer support spaced apart from the contact plug in the connection region and extending into the stack structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0077408 filed in the Korean Intellectual Property Office on June 16, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device and an electronic system including the semiconductor device. Background Art

[0004] There is a need for a semiconductor device capable of storing a large amount of data in an electronic system requiring data storage. Therefore, a technology that can increase the data storage capacity of a semiconductor device is being studied. For example, as one of the methods for increasing the data storage capacity of a semiconductor device, a semiconductor device including a three-dimensionally arranged storage cell instead of a two-dimensionally arranged storage cell has been proposed. Summary of the invention

[0005] Some example embodiments provide a semiconductor device having improved reliability and integration.

[0006] Some example embodiments provide an electronic system including a semiconductor device.

[0007] The present disclosure is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] According to an example embodiment, a semiconductor device may include: a substrate including a connection region; a stack structure including conductive patterns stacked on the substrate; an internal support member extending into the stack structure in the connection region; a contact plug extending into the stack structure and electrically connected to one of the conductive patterns and extending at least partially around the internal support member in a plan view; an insulating spacer between the contact plug and the stack structure and extending at least partially around the contact plug in a plan view; and an external support member spaced apart from the contact plug in the connection region and extending into the stack structure.

[0009] According to example embodiments, a semiconductor device may include: a substrate including a cell array region and a connection region; a stack structure including a conductive pattern stacked on the substrate; a vertical channel extending into the stack structure on the cell array region; a first contact plug extending into the stack structure in the connection region and electrically connected to a first conductive pattern among the conductive patterns; a second contact plug extending into the stack structure in the connection region and electrically connected to a second conductive pattern among the conductive patterns; a first internal support extending into the first contact plug; a second internal support extending into the second contact plug; a first insulating spacer between the first contact plug and the stack structure and extending at least partially around the first contact plug in a plan view; a second insulating spacer between the second contact plug and the stack structure and extending at least partially around the second contact plug; and a plurality of external supports extending into the stack structure and spaced apart from the first contact plug and the second contact plug in the connection region.

[0010] According to example embodiments, an electronic system may include: a semiconductor device including a substrate including a connection region; a stack structure including conductive patterns stacked on the substrate; an internal support extending into the stack structure in the connection region; a contact plug extending into a portion of the stack structure and electrically connected to one of the conductive patterns and extending at least partially around the internal support; an insulating spacer between the contact plug and the stack structure and extending at least partially around the contact plug; an external support extending into the stack structure and spaced apart from the contact plug; an input / output pad electrically connected to a peripheral circuit; and a controller electrically connected to the semiconductor device through the input / output pad and configured to control the semiconductor device.

[0011] Details of other embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting example embodiments described herein.

[0013] Figure 1A and Figure 1B is a plan view of a semiconductor device according to some example embodiments of the present disclosure, wherein Figure 1A shows the upper surface of the semiconductor device, Figure 1B The lower surface of the semiconductor device is shown.

[0014] Figure 2A and Figure 2B are cross-sectional views of semiconductor devices according to some example embodiments of the present disclosure, showing Figure 1A A cross section taken along lines AA' and BB'.

[0015] Figure 3A yes Figure 2A An enlarged view of portion “P1”.

[0016] Figure 3B yes Figure 2A An enlarged view of portion “P2”.

[0017] Figure 4 , Figure 5 , Figure 6 and Figure 7 is a plan view of a semiconductor device according to some example embodiments of the present disclosure.

[0018] Figure 8 is a plan view of a semiconductor device according to some example embodiments of the present disclosure.

[0019] Fig. 9 is a cross-sectional view of a semiconductor device according to some example embodiments of the present disclosure, showing a Figure 8 A cross section taken along line AA'.

[0020] Fig.10 yes Fig. 9 An enlarged view of the “P3” portion of the image.

[0021] Fig.11 According to some example embodiments of the present disclosure Figure 8 A cross-sectional view of the semiconductor device taken along line AA′.

[0022] Fig.12 According to some example embodiments of the present disclosure Figure 8 A cross-sectional view of the semiconductor device taken along line AA′.

[0023] Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A is a diagram for illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and illustrates a method of manufacturing a semiconductor device along the Figure 5 A cross section taken along line AA'.

[0024] Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B and Fig. 21Bis a diagram for illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and illustrates a method of manufacturing a semiconductor device along the Figure 5 The cross section is taken along the line BB'.

[0025] Fig. 22 , Fig.23 , Fig.24 and Fig.25 is a diagram for illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and illustrates a method of manufacturing a semiconductor device along the Figure 5 A cross section taken along line AA'.

[0026] Fig.26 is a diagram schematically illustrating an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0027] Fig. 27 is a schematic perspective view of an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0028] Fig.28 and Fig.29 is a cross-sectional view schematically illustrating a semiconductor package according to some example embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] Hereinafter, a semiconductor device and an electronic system including the same according to embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0030] Figure 1A and Figure 1B is a plan view of a semiconductor device according to some example embodiments of the present disclosure, wherein Figure 1A shows the upper surface of the semiconductor device, Figure 1B The lower surface of the semiconductor device is shown. Figure 2A and Figure 2B are cross-sectional views of semiconductor devices according to some example embodiments of the present disclosure, showing Figure 1A A cross section taken along lines AA' and BB'. Figure 3A yes Figure 2A An enlarged view of portion “P1”. Figure 3B yes Figure 2A An enlarged view of portion “P2”.

[0031] refer to Figure 1A , Figure 1B , Figure 2A and Figure 2B , a semiconductor device according to some example embodiments may include a substrate 100 , a stack structure ST, a vertical structure VC, internal and external supports IS and OS, a cell contact plug CP, a bit line BL, and a connection line CL.

[0032] The substrate 100 may include a cell array region CAR and a connection region CNR. The substrate 100 may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The substrate 100 may include a semiconductor doped with impurities and / or an intrinsic semiconductor not doped with impurities. The substrate 100 may have a crystal structure including at least one selected from a single crystal, an amorphous, and a polycrystalline. As another example, the substrate 100 may be formed of an insulating material such as silicon oxide.

[0033] The stack structure ST may be disposed on the substrate 100. The stack structure ST may extend from the cell array region CAR to the connection region CNR in the first direction D1. The stack structure ST may have a uniform thickness in the cell array region CAR and the connection region CNR.

[0034] The stacked structure ST may include conductive patterns GE and insulating layers ILD alternately stacked in a third direction D3 (i.e., a vertical direction) perpendicular to the first direction D1 and the second direction D2 intersecting each other. The conductive pattern GE may include, for example, at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a transition metal (e.g., titanium, tantalum, etc.). The insulating layer ILD may include a silicon oxide layer and / or a low-k dielectric layer. According to an embodiment, the semiconductor device may be a vertical NAND flash memory device, and in this case, the conductive pattern GE of the stacked structure ST may be used as a gate electrode of a string selection transistor, a memory cell transistor, and / or a ground selection transistor of the NAND flash memory device.

[0035] A plurality of vertical structures VC may pass through the stacked structure ST in the cell array region CAR. When viewed in a plan view, the vertical structures VC may be arranged in one direction or in a zigzag form.

[0036] Each of the vertical structures VC may have a maximum width on the upper surface of the uppermost insulating layer ILD. Each of the vertical structures VC may have a minimum width at its bottom surface, and the minimum width may be smaller than the maximum width. In some embodiments, each of the vertical structures VC may have substantially the same width at its upper surface and its bottom surface. The distance between adjacent vertical structures VC may be smaller than the maximum width of each of the vertical structures VC.

[0037] For details, refer to Figure 3AIn a plan view, each of the vertical structures VC may include a vertical semiconductor pattern VP, a data storage pattern DSP surrounding a sidewall of the vertical semiconductor pattern VP, and a gap-filling insulating pattern VI inside the vertical semiconductor pattern VP.

[0038] In detail, the vertical semiconductor pattern VP may have a bottom-closed tube shape or a macaroni shape. The vertical semiconductor pattern VP may have a U-shape, and the inside of the vertical semiconductor pattern VP may be at least partially filled with a gap-filling insulating pattern VI. A bit line conductive pad may be formed on an upper end of the vertical semiconductor pattern VP, and the bit line conductive pad may be formed of a semiconductor material not doped with impurities, a semiconductor material doped with impurities, or a conductive material.

[0039] The vertical semiconductor pattern VP may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The vertical semiconductor pattern VP including the semiconductor material may serve as a channel of a memory cell transistor constituting a cell string.

[0040] The data storage pattern DSP extends in the third direction D3 and may surround the sidewall of each vertical semiconductor pattern VP in a plan view. The data storage pattern DSP may have a tube shape with an upper end and a lower end open, or a macaroni shape. The data storage pattern DSP may be composed of one thin layer or a plurality of thin layers. In some embodiments of the present invention, the data storage pattern DSP may be a data storage layer of a NAND flash memory device, and may include a tunnel insulating layer TIL, a charge storage layer CIL, and a blocking insulating layer BLK sequentially stacked on the sidewall of the vertical semiconductor pattern VP. For example, the charge storage layer CIL may be a trap insulating layer, a floating gate electrode, or an insulating layer including conductive nanodots. In detail, the charge storage layer CIL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, nanocrystalline silicon, and / or a laminated trap layer. The tunnel insulating layer TIL may include at least one material having a band gap larger than that of the charge storage layer CIL, and the blocking insulating layer BLK may be a high dielectric layer such as an aluminum oxide layer or a hafnium oxide layer.

[0041] The horizontal insulating pattern HP may be disposed between one sidewall of the conductive pattern GE and the data storage pattern DSP. The horizontal insulating pattern HP may extend to the upper and lower surfaces of one sidewall of the conductive pattern GE. The horizontal insulating pattern HP may include, for example, a silicon oxide layer and / or a high dielectric layer.

[0042] Reference again Figure 2A and Figure 2B , the first interlayer insulating layer 110 may cover or overlap an upper surface of the vertical structure VC on the stacked structure ST.

[0043] The bit lines BL extending in the second direction D2 may be disposed on the first interlayer insulating layer 110 in the cell array region CAR. The bit lines BL may be electrically connected to the vertical structures VC through the bit line contact plugs BPLG.

[0044] The separation structure SS may extend from the cell array region CAR to the connection region CNR in the first direction D1. The separation structure SS may be spaced apart in a second direction D2 intersecting the first direction D1. The separation structure SS may include an insulating layer covering or overlapping both side walls of the stacked structure ST. Each of the separation structures SS may have a single-layer structure or a multi-layer structure. The upper surface of the separation structure SS may be disposed at substantially the same height as the upper surface of the first interlayer insulating layer 110. In the separation structure SS, the width of the lower portion may be smaller than the width of the upper portion.

[0045] According to some example embodiments, the internal support IS and the external support OS may pass through the first interlayer insulating layer 110 and the stack structure ST in the connection region CNR.

[0046] The internal support members IS may pass through the first interlayer insulating layer 110 and the stacked structure ST in the connection region CNR. The internal support members IS may be spaced apart from each other in the first direction D1 and the second direction D2. The internal support members IS may have substantially the same width (or diameter) as each other. The internal support members IS may have substantially the same vertical length as each other in the third direction D3. Each of the internal support members IS may have a first upper width R1 at its upper surface, and may have a first lower width R2 at its lower surface. Each of the internal support members IS may have a first lower width R2 that is smaller than the first upper width R1. Each of the internal support members IS may be an insulating column formed of an insulating material.

[0047] Each of the internal supports IS may include a lower portion in contact with the stacked structure ST and an upper portion in contact with the contact plug. The upper surface of the internal support IS may be located at a different height from the upper surface of the vertical structure VC (i.e., at a different distance from the substrate 100). The upper surface of the internal support IS may be located at substantially the same height as the upper surface of the first interlayer insulating layer 110, or at the same distance from the substrate 100. Each of the internal supports IS may have a circular, elliptical, rectangular, or polygonal upper surface. For example, each of the internal supports IS may have a quadrilateral upper surface.

[0048] For example, each of the inner supports IS may be disposed between two outer supports OS adjacent to each other in the first direction D1 , and may be disposed between two outer supports OS adjacent to each other in the second direction D2 .

[0049] According to some example embodiments, contact plugs CP1, CP2, CP3, CP4, CP5, and CP6 may penetrate the first interlayer insulating layer 110 and the stack structure ST in the connection region CNR to be connected to the conductive pattern GE, respectively. Figure 3B Each contact plug CP1 to CP6 may be in direct contact with the upper surface of the corresponding conductive pattern GE. The contact plugs CP1 to CP6 may include, for example, at least one selected from metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), or transition metals (e.g., titanium, tantalum, etc.).

[0050] The contact plugs CP1 to CP6 may be spaced apart from each other in the first direction D1 and the second direction D2 in the connection region CNR. The contact plugs CP1 to CP6 may have different vertical lengths. The vertical lengths of the contact plugs CP1 to CP6 may decrease as the contact plugs CP1 to CP6 are closer to the cell array region CAR. The contact plugs CP1 to CP6 may have bottom surfaces at different heights relative to the substrate 100 and upper surfaces at the same height as each other. The upper surfaces of the contact plugs CP1 to CP6 may be substantially coplanar with the upper surface of the first interlayer insulating layer 110.

[0051] For example, the contact plugs may include first to sixth contact plugs CP1 to CP6, and the first to sixth contact plugs CP1 to CP6 may be connected to the conductive patterns GE located at different heights, respectively. For example, the first contact plug CP1, the third contact plug CP3, and the fifth contact plug CP5 may be spaced apart from each other in the first direction D1, and the second contact plug CP2, the fourth contact plug CP4, and the sixth contact plug CP6 may be disposed to be spaced apart from the first contact plug CP1, the third contact plug CP3, and the fifth contact plug CP5 in the second direction D2. For example, the first contact plug CP1, the third contact plug CP3, and the fifth contact plug CP5 may be connected to the odd-numbered conductive patterns GE, and the second contact plug CP2, the fourth contact plug CP2, and the sixth contact plug CP6 may be connected to the even-numbered conductive patterns GE.

[0052] Each of the contact plugs CP1 to CP6 may surround an upper portion of the internal support IS. Each of the contact plugs CP1 to CP6 may have a closed curve shape or a ring shape. Each of the contact plugs CP1 to CP6 may have a circular, elliptical, rectangular, or polygonal upper surface.

[0053] In a plan view, the contact plugs CP1 to CP6 may be surrounded by the stack structure ST. Each of the contact plugs CP1 to CP6 may have a maximum width Ra at an upper surface thereof and a minimum width Rb at a lower surface thereof. The contact plugs CP1 to CP6 may have a greater width than the vertical structure VC.

[0054] Each contact plug CP1 to CP6 may be disposed between the inner support IS and the outer support OS adjacent thereto. Each contact plug CP1 to CP6 may have a first thickness t1 between the sidewalls of the insulating spacer SP and the inner support IS, and the first thickness t1 may be smaller than the diameters R1 and R2 of the inner support IS.

[0055] The insulating spacers SP may be disposed between the contact plugs CP1 to CP6 and the stacked structure ST. The insulating spacers SP may surround the contact plugs CP1 to CP6, respectively. The insulating spacers SP may be in direct contact with the sidewalls of the contact plugs CP1 to CP6. The insulating spacers SP may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric. Figure 3B , a portion of the horizontal insulation pattern HP may be disposed between each of the insulation spacers SP and the conductive pattern GE.

[0056] The insulating spacers SP may have different vertical lengths. The vertical lengths of the insulating spacers SP may decrease as the insulating spacers SP are closer to the cell array region CAR. The insulating spacers SP may have bottom surfaces located at different heights and upper surfaces located at the same height. The upper surfaces of the insulating spacers SP may be located at substantially the same height as the upper surfaces of the contact plugs CP1 to CP6.

[0057] When viewed in a plan view, an external supporter OS may be disposed around each of the contact plugs CP1 to CP6. Each of the external supports OS may be an insulating column formed of an insulating material.

[0058] The outer supports OS may be spaced apart from each other in the first direction D1 and the second direction D2. In addition, the outer supports OS may be spaced apart from each other in an inclined direction with respect to the first direction D1 and the second direction D2.

[0059] Each of the contact plugs CP1 to CP6 may be disposed between two outer supports OS adjacent to each other in the first direction D1 , and each of the contact plugs CP1 to CP6 may be disposed between two outer supports OS adjacent to each other in the second direction D2 .

[0060] When viewed in a plan view, the external support OS may have a circular, rectangular, bar, or elliptical shape. Some of the external support OS may have a bar shape having a major axis in the first direction D1 or the second direction D2. The number, size, and shape of the external support OS may be variously modified.

[0061] The width of each of the external supports OS may be smaller than the width of the internal supports IS. The lower width of each of the external supports OS may be smaller than the upper width. Each of the external supports OS may be an insulating column formed of an insulating material. The external supports OS may have substantially the same vertical length in the third direction D3. The upper surface of the external supports OS may be located at substantially the same height as the upper surface of the first interlayer insulating layer 110.

[0062] Each of the contact plugs CP1 to CP6 may have a maximum diameter Ra at an upper surface thereof. Each of the contact plugs CP1 to CP6 may have a minimum diameter Rb at a lower surface thereof.

[0063] The inner support IS and the outer support OS adjacent to the contact plugs CP1 to CP6 may be spaced apart from each other at bottom surfaces thereof by a minimum distance Da.

[0064] The inner support IS and the outer support OS adjacent to the contact plugs CP1 to CP6 may be spaced apart from each other at their upper surfaces by a maximum distance Db. For example, the maximum distance Db between the inner support IS and the outer support OS adjacent to the contact plugs CP1 to CP6 may be about 300 nm to about 500 nm, but the inventive concept is not limited thereto.

[0065] Connection lines CL may be disposed on the first interlayer insulating layer 110 of the connection region CNR, and the connection lines CL may be connected to the contact plugs CP1 to CP6, respectively.

[0066] Hereinafter, semiconductor devices according to various example embodiments of the inventive concept will be described, and detailed descriptions of technical features overlapping with those of the above-described embodiments will be omitted, and differences will be described.

[0067] Figure 4 , Figure 5 , Figure 6 and Figure 7 is a plan view of a semiconductor device according to some example embodiments of the present disclosure.

[0068] according to Figure 4 In the example embodiment shown, each of the inner supports IS may have a circular upper surface. That is, each of the inner supports IS may have a cylindrical shape. Each of the outer supports IS may have a circular or elliptical upper surface.

[0069] according to Figure 5 In the example embodiment shown, the internal support member IS and the external support member OS may penetrate the stack structure ST in the connection region CNR, and the contact plugs CP1 to CP9 may respectively surround the internal support member IS in a plan view. The contact plugs CP1 to CP9 may form three columns, and each column may include a plurality of contact plugs CP1 to CP9 arranged along the first direction D1. For example, the contact plugs may include: a first contact plug CP1, a second contact plug CP2, and a third contact plug CP3 spaced apart from each other in the second direction D2, a fourth contact plug CP4, a fifth contact plug CP5, and a sixth contact plug CP6 spaced apart from each other in the second direction D2, and a seventh contact plug CP7, an eighth contact plug CP8, and a ninth contact plug CP9 spaced apart from each other in the second direction D2. As described above, the contact plugs CP1 to CP9 may have different vertical lengths in the third direction D3. In addition, insulating spacers SP may be respectively disposed between the contact plugs CP1 to CP9 and the stack structure ST.

[0070] In example embodiments, it is illustrated that the contact plugs are arranged in two or three rows in the second direction D2 , but the inventive concept is not limited thereto, and the contact plugs may be arranged in one row or may be arranged in four or more rows.

[0071] according to Figure 6 In the example embodiment shown, the width of the internal support member IS may increase as the distance from the cell array region CAR increases. Therefore, the width of the contact plugs CP1 to CP6 may also increase as the distance from the cell array region CAR increases. On the contrary, the width of the internal support member IS and the contact plugs CP1 to CP6 may decrease as the distance from the cell array region CAR increases.

[0072] according to Figure 7 In the illustrated example embodiment, widths of the internal support members IS arranged along the first direction D1 may be different from each other, and the number of the contact plugs CPa, CPb, and CPc may be different depending on the distance from the cell array region CAR.

[0073] In detail, the contact plugs may include a first contact plug CPa having a first width, a second contact plug CPb having a second width greater than the first width, and a third contact plug CPc having a third width greater than the second width.

[0074] The first contact plug CPa may be disposed at a first distance from the vertical structure VC of the cell array region CAR, the second contact plug CPb may be disposed at a second distance from the vertical structure VC of the cell array region CAR that is greater than the first distance, and the third contact plug CPc may be disposed at a third distance from the vertical structure VC of the cell array region CAR that is greater than the second distance.

[0075] According to some example embodiments, "l" (e.g., four) first contact plugs CPa may be spaced apart from each other in the second direction D2, and "m" (e.g., three) second contact plugs CPb may be spaced apart from each other in the second direction D2, "m" being smaller than "l". In addition, "n" (e.g., two) third contact plugs CPc may be spaced apart from each other in the second direction D2, "n" being smaller than "m".

[0076] As described above, each of the first, second, and third contact plugs CPa, CPb, and CPc may surround the upper portion of the internal support IS, and the insulating spacer SP may surround each of the first, second, and third contact plugs CPa, CPb, and CPc.

[0077] Figure 8 is a plan view of a semiconductor device according to some example embodiments of the present disclosure. Fig. 9 is a cross-sectional view of a semiconductor device according to some example embodiments of the present disclosure, showing a Figure 8 A cross section taken along line AA'. Fig.10 yes Fig. 9 An enlarged view of the “P3” portion of the image.

[0078] refer to Figure 8 and Fig. 9 , a semiconductor device according to some example embodiments may include a substrate 100 , a stack structure ST, a vertical structure VC, internal and external supports IS and OS, a cell contact plug CP, a through conductive plug TP, a bit line BL, and a connection line CL.

[0079] According to some example embodiments, each of the internal supports IS may include a through conductive plug TP penetrating the stack structure ST, and a through insulating spacer TIS surrounding the through conductive plug TP in a plan view. The through insulating spacer TIS may insulate the contact plugs CP1 to CP6 from the through conductive plug TP, and may insulate the stack structure ST from the through conductive plug TP.

[0080] The through conductive plugs TP may include the same conductive material as the contact plugs CP1 to CP6. The through insulating spacers TIS may include an insulating material such as silicon oxide or silicon nitride.

[0081] The through conductive plugs TP of the internal support IS may have substantially the same length in the third direction D3. In some embodiments, the through conductive plugs TP of the internal support IS may have different lengths in the third direction D3 and may be connected to the conductive patterns GE of different heights.

[0082] Fig.11 According to some example embodiments of the present disclosure Figure 8 A cross-sectional view of the semiconductor device taken along line AA′.

[0083] refer to Fig.11 , a semiconductor device according to some example embodiments may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS.

[0084] The peripheral circuit structure PS may include a peripheral circuit PTR integrated on an upper surface of a semiconductor substrate 10, and a lower insulating layer 50 covering the peripheral circuit PTR. The semiconductor substrate 10 may be a silicon substrate. The semiconductor substrate 10 may include a cell array region CAR and a connection region CNR.

[0085] The peripheral circuit PTR may include a row decoder and a column decoder, a page buffer, and a control circuit. In detail, the peripheral circuit PTR may include NMOS and PMOS transistors. The peripheral circuit wiring PLP may be electrically connected to the peripheral circuit PTR through a peripheral contact plug PCP.

[0086] The lower insulating layer 50 may be disposed on the upper surface of the semiconductor substrate 10. The lower insulating layer 50 may cover or overlap the peripheral circuit PTR, the peripheral contact plug PCP, and the peripheral circuit wiring PLP on the semiconductor substrate 10. The peripheral contact plug PCP and the peripheral circuit wiring PLP may be electrically connected to the peripheral circuit PTR.

[0087] The lower insulating layer 50 may include insulating layers stacked in a plurality of layers. For example, the lower insulating layer 50 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0088] The cell array structure CS may be disposed on the lower insulating layer 50. The cell array structure CS may include a substrate 100, a stack structure ST, a vertical structure VC, internal and external supports IS and OS, cell contact plugs CP, through contact plugs TP, bit lines BL, and connection lines CL.

[0089] As reference Figure 8 and Fig. 9As described above, each of the internal supports IS may include a through conductive plug TP penetrating the stack structure ST and a through insulating spacer TIS surrounding the through conductive plug TP. For example, the through conductive plug TP may extend vertically and be connected to the peripheral circuit wiring PLP of the peripheral circuit structure PS.

[0090] Fig.12 According to the embodiment of the present invention, Figure 8 A cross-sectional view of the semiconductor device taken along line AA′.

[0091] refer to Fig.12 , according to some example embodiments, the semiconductor device may have a chip-to-chip (C2C) structure. The C2C structure may mean that after an upper chip including a cell array structure CS is manufactured on a first wafer, and a lower chip including a peripheral circuit structure PS is manufactured on a second wafer different from the first wafer, the upper chip and the lower chip are connected to each other in a bonding manner. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on the topmost metal layer of the upper chip and a bonding metal formed on the topmost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu to Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0092] The semiconductor device according to an embodiment of the inventive concept may include a peripheral circuit structure PS on a semiconductor substrate 200 , and a cell array structure CS on the peripheral circuit structure PS.

[0093] According to some example embodiments, when the cell array structure CS is combined with the peripheral circuit structure PS, the cell capacity per unit area of ​​the semiconductor device according to the present invention can be increased. In addition, the semiconductor device according to the present invention can prevent damage to the peripheral circuit PTR due to various heat treatment processes by manufacturing the peripheral circuit structure PS and the cell array structure CS and combining them with each other, thereby improving its electrical characteristics and reliability.

[0094] In detail, the peripheral circuit structure PS may include a semiconductor substrate 200, a peripheral circuit PTR controlling a memory cell array, and peripheral interlayer insulating layers 210 and 220 covering or overlapping the peripheral circuit PTR. The peripheral circuit PTR may be integrated on the upper surface of the semiconductor substrate 200. A surface insulating layer 201 may be provided on the rear surface of the semiconductor substrate 200.

[0095] The semiconductor substrate 200 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The semiconductor substrate 200 may have an upper surface parallel to a first direction D1 and a second direction D2, wherein the second direction D2 intersects the first direction D1 and is perpendicular to a third direction D3. For example, the first direction to the third direction D1, D2, and D3 may be perpendicular to each other.

[0096] The peripheral circuit PTR may include a row decoder and a column decoder, a page buffer, and a control circuit. In detail, the peripheral circuit PTR may include NMOS and PMOS transistors. The peripheral circuit wiring PLP may be electrically connected to the peripheral circuit PTR through a peripheral contact plug PCP.

[0097] For example, the width of the peripheral contact plug PCP may increase in the first direction D1 or the second direction D2 toward the third direction D3. The peripheral contact plug PCP and the peripheral circuit wiring PLP may include a conductive material such as metal.

[0098] Peripheral interlayer insulating layers 210 and 220 may be disposed on the upper surface of the semiconductor substrate 200. Peripheral interlayer insulating layers 210 and 220 may cover or overlap peripheral circuits PTR, peripheral contact plugs PCP, and peripheral circuit wirings PLP on the semiconductor substrate 200. The peripheral contact plugs PCP and the peripheral circuit wirings PLP may be electrically connected to the peripheral circuits PTR. The peripheral interlayer insulating layers 210 and 220 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0099] The first bonding pad BP1 may be disposed in the uppermost peripheral interlayer insulating layer 220. The peripheral interlayer insulating layer 220 may not cover the upper surface of the first bonding pad BP1, or may not overlap the upper surface. The upper surface of the uppermost peripheral interlayer insulating layer 220 may be substantially coplanar with the upper surface of the first bonding pad BP1. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through the peripheral circuit wiring PLP and the peripheral contact plug PCP.

[0100] The cell array structure CS may be disposed on the peripheral circuit structure PS. The cell array structure CS may include a memory cell array including memory cells three-dimensionally arranged on the substrate 100. The memory cell array may be electrically connected to the second bonding pad BP2. The second bonding pad BP2 may be electrically and physically connected to the first bonding pad BP1 by bonding. That is, the second bonding pad BP2 may be in direct contact with the first bonding pad BP1.

[0101] The second bonding pad BP2 may include the same metal material as the first bonding pad BP1. The second bonding pad BP2 may have substantially the same shape, width, or area as the first bonding pad BP1.

[0102] As reference Figure 1A , Figure 1B , Figure 2A and Figure 2B As described above, the cell array structure CS may include a stack structure ST, a vertical structure VC, a bit line BL, contact plugs CP1 to CP6 , an internal support IS and an external support OS, and an input / output contact plug IOPLG.

[0103] A plurality of stacked structures ST of the cell array structure CS may be provided. The plurality of stacked structures ST may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. Hereinafter, for ease of description, a single stacked structure ST will be described, but the following description may be equally applied to other stacked structures ST.

[0104] The stacked structure ST may include conductive patterns GE and insulating layers ILD alternately stacked in a third direction D3 (ie, a vertical direction) perpendicular to the first and second directions D1 and D2 crossing each other.

[0105] As described above, in the connection region CNR, the contact plugs CP1 to CP6 may penetrate the stack structure ST and be connected to the conductive pattern GE, respectively.

[0106] The input / output contact plug IOPLG may be electrically connected to the input / output pad by penetrating the planar insulating layer 120 in the connection region CNR.

[0107] The second interlayer insulating layer 130 may be disposed on the first interlayer insulating layer 110, and the upper conductive line UCL may be disposed on the second interlayer insulating layer 130. The upper conductive line UCL may be electrically connected to the bit line BL or the connection line CL.

[0108] The third interlayer insulating layer 140 and the fourth interlayer insulating layer 150 may be disposed on the second interlayer insulating layer 130, and the second bonding pad BP2 may be disposed in the fourth interlayer insulating layer 150 (i.e., the uppermost interlayer insulating layer). The second bonding pad BP2 may be electrically connected to the upper conductive line UCL. The second bonding pad BP2 may be formed of aluminum, copper, or tungsten.

[0109] The second bonding pad BP2 may be electrically and physically connected to the first bonding pad BP1 by bonding. That is, the second bonding pad BP2 may be in direct contact with the first bonding pad BP1.

[0110] The second bonding pad BP2 may include the same metal material as the first bonding pad BP1. The second bonding pad BP2 may have substantially the same shape, width, or area as the first bonding pad BP1.

[0111] The upper insulating layer 300 may cover the substrate 100 or overlap the substrate 100. The input / output pads PAD may be provided on the upper insulating layer 300. The capping insulating layer 320 may be provided on the upper insulating layer 300, and the capping insulating layer 320 may cover the input / output pads PAD or overlap the input / output pads PAD.

[0112] Capping insulating layers 320 and 330 and a passivation layer 340 may be sequentially formed on the entire surface of the upper insulating layer 300. The capping insulating layers 320 and 330 may be, for example, silicon nitride layers or silicon oxynitride layers. The passivation layer 340 may be, for example, a polyimide-based material such as photosensitive polyimide (PSPI).

[0113] The capping insulating layers 320 and 330 and the passivation layer 340 may have a pad opening OP exposing a portion of the input / output pad PAD.

[0114] Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A is a diagram for illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and illustrates a method of manufacturing a semiconductor device along the Figure 5 A cross section taken along line AA'.

[0115] Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B and Fig. 21B is a diagram for illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and illustrates a method of manufacturing a semiconductor device along the Figure 5 The cross section is taken along the line BB'.

[0116] refer to Fig.13A and Fig. 13B , the substrate 100 may include a cell array region CAR and a connection region CNR adjacent to the cell array region CAR.

[0117] The substrate 100 may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The substrate 100 may include a semiconductor doped with impurities and / or an intrinsic semiconductor not doped with impurities. The substrate 100 may have a crystal structure including at least one selected from single crystal, amorphous, and / or polycrystalline.

[0118] A mold structure PST in which insulating layers ILD and sacrificial layers SL are vertically alternately stacked may be formed on the substrate 100 .

[0119] The mold structure PST may have a uniform thickness over the cell array region CAR and the connection region CNR. The sacrificial layers SL may have substantially the same thickness, and some of the insulating layers ILD may have different thicknesses.

[0120] In the mold structure PST, the sacrificial layer SL may be formed of a material having an etching selectivity relative to the insulating layer ILD and may be etched. For example, the sacrificial layer SL may be formed of an insulating material different from the insulating material of the insulating layer ILD. For example, the sacrificial layer SL may be formed of a silicon nitride layer, and the insulating layer ILD may be formed of a silicon oxide layer.

[0121] The insulating layer ILD and the sacrificial layer SL may be formed by a thermal CVD process, a plasma enhanced CVD process, a physical CVD process, or an atomic layer deposition ALD process.

[0122] Subsequently, a vertical channel hole exposing the substrate 100 may be formed through the mold structure PST in the cell array region CAR. When a vertical sacrificial pattern (not shown) is formed in the mold structure PST, forming the vertical channel hole may include removing the vertical sacrificial pattern to expose the substrate 100 .

[0123] Forming the vertical channel hole may include: forming a hard mask pattern on the mold structure PST, and anisotropically etching the mold structure PST using the hard mask pattern as an etching mask. In the anisotropic etching process for forming the vertical channel hole, the upper surface of the substrate 100 may be over-etched, so the upper surface of the vertical channel hole exposed to the substrate 100 may be recessed to a certain depth. In addition, during the anisotropic etching process for forming the vertical channel hole, the recessed depth of the substrate 100 may vary depending on the position of the vertical channel hole.

[0124] Thereafter, a vertical structure VC may be formed in the vertical channel hole of the cell array region CAR.

[0125] Forming the vertical structure VC may include forming a vertical channel hole exposing the substrate 100 through the mold structure PST, sequentially depositing a data storage layer and a vertical channel layer in the vertical channel hole, and etching and planarizing the data storage layer and the vertical channel layer.

[0126] The data storage layer may be deposited to a uniform thickness on the bottom surface and inner wall of the vertical channel hole using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The data storage layer may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer sequentially stacked in the vertical channel hole. The vertical channel layer may be deposited to a uniform thickness on the data storage layer using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. After forming the data storage layer and the vertical channel layer, the vertical channel hole may be filled with a gap filling insulating layer. Thus, as described above with reference to Figure 3A As described above, a data storage pattern DSP, a vertical semiconductor pattern VP, and a gap-filling insulating pattern VI may be formed in each vertical channel hole. In addition, a bit line conductive pad may be formed on an upper end of the vertical semiconductor pattern VP. The bit line conductive pad may be an impurity region doped with impurities, or may be formed of a conductive material.

[0127] refer to Fig.14A and Fig. 14B , a first interlayer insulating layer 110 may be formed on the mold structure PST. The first interlayer insulating layer 110 may cover an upper surface of the vertical structure VC or overlap the upper surface.

[0128] Subsequently, an external support OS of the through-mold structure PST may be formed in the connection region CNR.

[0129] Forming the outer support OS may include forming a mask pattern (not shown) on the first interlayer insulating layer, anisotropically etching the mold structure PST using the mask pattern (not shown) as an etching mask to form a vertical hole exposing the substrate 100, and filling an insulating material in the vertical hole.

[0130] Like the above-described embodiment, the outer supports OS may be spaced apart from each other in the first direction D1 and the second direction D2 when viewed in a plan view, and may have various shapes and sizes.

[0131] refer to Fig.15A and Fig. 15B , contact holes OP1, OP2, OP3, and OP5 penetrating a portion of the mold structure PST may be formed in the connection region CNR. The contact holes OP1, OP3, and OP5 may expose the upper surface of the sacrificial layer SL located at different heights. Some of the sidewalls of the sacrificial layer SL and some of the sidewalls of the insulating layer ILD may be exposed through the contact holes OP1, OP2, OP3, and OP5.

[0132] The contact holes OP1 , OP2 , OP3 , and OP5 may be formed between the outer supports OS adjacent to each other in the first direction D1 and between the outer supports OS adjacent to each other in the second direction D2 .

[0133] A lower width of each of the contact holes OP1, OP2, OP3, and OP5 may be smaller than an upper width. When viewed in a plan view, each of the contact holes OP1, OP2, OP3, and OP5 may be formed in a circular shape, a bar shape, an elliptical shape, or a polygonal shape.

[0134] According to some example embodiments, the contact holes OP1, OP2, OP3, and OP5 may have different vertical depths. That is, the sacrificial layers SL exposed through the contact holes OP1, OP2, OP3, and OP5 may be located at different heights. In other words, the number of sacrificial layers SL through which the contact holes OP1, OP2, OP3, and OP5 pass may be different from each other.

[0135] The contact holes OP1, OP2, OP3, and OP5 having different vertical depths may be formed by repeating the mask forming process and the mold structure etching process a plurality of times. The contact holes OP1, OP2, OP3, and OP5 may be formed by anisotropic etching processes of different times.

[0136] refer to Fig.16A and Fig. 16B , the insulating spacer SP may be formed to cover the inner walls of the contact holes OP1, OP2, OP3, and OP5. The insulating spacer SP may cover the sidewalls of the sacrificial layer SL and the insulating layer ILD exposed by the contact holes, or may overlap the sidewalls. The insulating spacer SP may have different vertical lengths within the contact holes.

[0137] The insulating spacers SP may include an insulating material having an etch selectivity with respect to the sacrificial layer. The insulating spacers SP may include, for example, silicon oxide, silicon oxynitride, and / or a low-k material.

[0138] Forming the insulating spacers SP may include depositing a spacer layer having a uniform thickness on the mold structure having the contact holes, and anisotropically etching the spacer layer to expose an upper surface of the sacrificial layer SL in each of the contact holes.

[0139] refer to Fig.17A and Fig. 17B , a buffer spacer BI and a sacrificial spacer SC may be formed in each contact hole.

[0140] Forming the buffer spacer BI and the sacrificial spacer SC may include sequentially depositing a buffer layer and a sacrificial spacer layer in a contact hole formed with an insulating spacer, and sequentially anisotropically etching the buffer layer and the sacrificial spacer layer to expose an upper surface of the sacrificial layer SL in the contact hole.

[0141] In some embodiments, the sum of the thicknesses of the insulating spacers SP, the buffer spacers BI, and the sacrificial spacers SC may be less than ½ of the diameter of each contact hole.

[0142] The buffer spacer BI may be formed of a material having an etching selectivity relative to the sacrificial layer SL. The buffer spacer BI may include the same insulating material as the insulating spacer SP. For example, the buffer spacer BI may include a silicon oxide layer. The buffer spacer BI may be formed between the bottom surface of the sacrificial spacer SC and the upper surface of the sacrificial layer SL and between the insulating spacer SP and the sacrificial spacer SC. The sacrificial spacers SC in the contact holes may have different vertical lengths.

[0143] The sacrificial spacers SC may be formed of a material having an etch selectivity with respect to the buffer spacers BI. The sacrificial spacers SC may include, for example, silicon nitride or silicon oxynitride.

[0144] refer to Fig.18A and Fig.18B , a through hole TH penetrating the mold structure PST may be formed in each of the contact holes.

[0145] Forming the through hole TH may include anisotropically etching the mold structure PST using the sacrificial spacer SC as an etching mask. The through hole TH may expose the substrate 100.

[0146] The through holes TH in the contact holes may have substantially the same vertical depth. A lower width of each of the through holes TH may be smaller than an upper width.

[0147] Afterwards, refer to Fig.19A and Fig.19B , the through hole TH may be filled with an insulating material to form an internal support member IS. An insulating layer may be deposited on the mold structure PST to form the internal support member IS, in which the through hole TH may be planarized, and then the insulating layer may be planarized to expose the upper surface of the first interlayer insulating layer 110.

[0148] Since the lower width of each of the internal support member IS and the external support member OS is smaller than the upper width, the distance between the adjacent internal support members IS and the external support member OS can be larger in the lower part of the internal support member IS and the external support member OS than in the upper part of the internal support member IS and the external support member OS.

[0149] After forming the internal support member IS, the mold structure PST may be patterned to form a separation trench TR extending in the first direction D1. The separation trench TR may expose the substrate 100. Therefore, the mold structure PST may be patterned into a line shape extending in the first direction D1.

[0150] Then, the sacrificial layer SL exposed in the separation trench TR may be removed to form a gate region GR between the insulating layers ILD. The gate region GR is formed by isotropically etching the sacrificial layer SL using an etching recipe having an etching selectivity for the insulating layer ILD, the vertical structure VC, and the internal support OS and the external support IS. The gate region GR formed as described above may extend horizontally from the separation trench TR. In addition, the gate region GR may expose a portion of the vertical structure VC located in the cell array region CAR, and may expose a portion of the internal support OS and the external support IS and the insulating spacer located in the connection region CNR.

[0151] When forming the gate region GR, the internal support member IS and the external support member OS can prevent the vertically stacked insulating layer ILD in the connection region CNR from collapsing. According to an embodiment, as the internal support members IS are respectively disposed between the external support members OS adjacent to each other, the number of stacked conductive patterns GE increases, and the diameters of the contact plugs CP1 to CP6 increase, the distance between the external support members OS can be increased, thereby preventing the insulating layer ILD from collapsing between the external support members OS adjacent to each other.

[0152] refer to Fig. 20A and Fig. 20B , the conductive pattern GE may be formed in the gate region. The conductive pattern GE may partially fill the gate region GR or completely fill the gate region GR. In one example, the conductive pattern GE may include sequentially depositing a metal nitride layer (e.g., TiN, TaN, or WN) and a metal layer (e.g., W, Al, Ti, Ta, Co, or Cu). Subsequently, the portions of the metal nitride layer and the metal layer formed in the separation trench TR may be removed to locally form the conductive pattern GE in the gate region GR. Therefore, a stacked structure ST in which insulating layers ILD and conductive patterns GE are alternately stacked may be formed on the substrate 100.

[0153] According to some example embodiments of the present disclosure, before forming the conductive pattern GE, a horizontal insulating pattern HP (see Figure 3A and Figure 3B ), the horizontal insulation pattern HP conformally covers or overlaps the inner wall of the gate region GR. The horizontal insulation pattern HP may be formed on the inner wall of the gate region GR to have a substantially uniform thickness.

[0154] After forming the conductive pattern GE, a separation structure SS may be formed by filling the separation trench TR with an insulating material.

[0155] After forming the separation structure SS, a process of replacing the sacrificial spacers SC with the contact plugs CP may be performed in the connection region CNR.

[0156] In detail, an isotropic etching process for removing the sacrificial spacer SC may be performed to form a recessed area between the insulating spacer SP and the internal support member IS. During the isotropic etching process performed on the sacrificial spacer SC, the buffer spacer BI may be used as an etching stop layer. Subsequently, a portion of the horizontal insulating pattern located on the upper surface of the buffer spacer BI and the conductive pattern GE may be etched. Therefore, the upper surface of the conductive pattern GE may be exposed in the recessed area.

[0157] Then, if Fig.21A and Fig. 21B As shown, a contact plug CP connected to the conductive pattern GE may be formed by filling the recessed region with a conductive material.

[0158] For details, refer to Fig.21A and Fig. 21B Forming the contact plugs CP1 to CP6 may include depositing a conductive layer filling the recessed regions on the first interlayer insulating layer 110 , and planarizing the conductive layer to expose the first interlayer insulating layer 110 .

[0159] That is, upper surfaces of the contact plugs CP1 to CP6 may be coplanar with an upper surface of the first interlayer insulating layer 110. The contact plugs CP1 to CP6 may have different vertical lengths and may make contact with upper surfaces of the conductive patterns GE, respectively.

[0160] Figure 22 to Figure 25 is a diagram for illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and illustrates a method of manufacturing a semiconductor device along the Figure 5 A cross section taken along line AA'.

[0161] refer to Fig. 22 , as referenced Fig.18A and Fig.18B As described above, a through hole TH exposing the substrate 100 may be formed by penetrating the mold structure PST in the connection region CNR, and then a through insulating spacer TIS may be formed in the through hole TH.

[0162] Forming the through insulating spacer TIS may include depositing a spacer layer having a uniform thickness on the mold structure PST formed with the through holes TH, and anisotropically etching the spacer layer to expose the upper surface of the substrate 100 located in each through hole TH. Here, the thickness of the spacer layer may be less than about 1 / 2 of the diameter of each through hole TH. The through insulating spacer TIS may include, for example, silicon oxide, silicon oxynitride, and / or a low-k material.

[0163] refer to Fig.23 The through sacrificial spacer TSC may be formed in the through hole TH in which the through insulating spacer TIS is formed. Forming the through sacrificial spacer TSC may include depositing a sacrificial spacer layer to fill the through hole TH in which the through insulating spacer TIS is formed, and planarizing the sacrificial spacer layer to expose the first interlayer insulating layer 110 .

[0164] The through sacrificial spacers TSC may be formed of a material having an etch selectivity with respect to the through insulating spacers TIS. The through sacrificial spacers TSC may be formed of the same material as the sacrificial spacers SC. The through sacrificial spacers TSC may include, for example, silicon nitride or silicon oxynitride.

[0165] refer to Fig.24 , after forming the through insulating spacer TIS and the through sacrificial spacer TSC, as shown in reference Fig.19A , Fig.19B , Fig. 20A and Fig. 20B As described above, the sacrificial layer SL of the mold structure PST may be replaced with the conductive pattern GE. Thus, the stacked structure ST may be formed on the substrate 100.

[0166] refer to Fig.25 , operations of replacing the sacrificial spacers SC with the contact plugs CP1 to CP6 and replacing the through sacrificial spacers TSC with the through conductive plugs TP may be performed.

[0167] In detail, the isotropic etching process may be performed to remove the sacrificial spacers SC and the through-sacrificial spacers TSC to form a recessed area between the insulating spacers SP and the internal support IS, and simultaneously the through-insulating spacers TIS in the through holes TH may be exposed.

[0168] Subsequently, a conductive layer filling the through hole having the recessed region and the insulating spacer SP formed therein may be deposited on the first interlayer insulating layer 110 and then planarized to expose the first interlayer insulating layer 110. Thus, contact plugs CP1 to CP6 and through conductive plugs TP may be formed.

[0169] Fig.26is a diagram schematically illustrating an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0170] refer to Fig.26 , an electronic system 1000 according to some embodiments of the inventive concept may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a memory device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical system, or a communication system in which at least one semiconductor device 1100 is disposed.

[0171] The semiconductor device 1100 may be a nonvolatile memory device (eg, a NAND flash memory device). The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed beside the second structure 1100S.

[0172] The first structure 3100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer circuit 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure (e.g., a cell array structure according to any one of the embodiments) including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0173] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously changed according to embodiments.

[0174] In some embodiments, the upper transistors UT1 and UT2 may include at least one string selection transistor, and the lower transistors LT1 and LT2 may include at least one ground selection transistor. The lower gate lines LL1 and LL2 may be used as gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be used as gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1 and UL2 may be used as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0175] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used for an erase operation of erasing data stored in the memory cell transistor MCT using a gate induced drain leakage (GIDL) phenomenon.

[0176] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer circuit 1120 through a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0177] In the first structure 1100F, the decoder circuit 1110 and the page buffer circuit 1120 may be configured to perform a control operation on at least one selected memory cell transistor MCT among the memory cell transistors MCT. The decoder circuit 1110 and the page buffer circuit 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through the input / output connection line 1135 extending from the first structure 3100F to the second structure 3100S.

[0178] Although not shown in the drawings, the first structure 1100F may include a voltage generator (not shown). The voltage generator may generate a program voltage, a read voltage, a pass voltage, a verification voltage, etc. required for operating the memory cell string CSTR. Here, the program voltage may be a relatively high voltage (e.g., 20V to 40V) compared to the read voltage, the pass voltage, and the verification voltage.

[0179] In some embodiments, the first structure 1100F may include a high voltage transistor and a low voltage transistor. The decoder circuit 1110 may include a channel transistor connected to the word line WL of the memory cell string CSTR. The channel transistor may include a high voltage transistor capable of withstanding a high voltage (e.g., a programming voltage applied to the word line WL during a programming operation). The page buffer circuit 1120 may also include a high voltage transistor capable of withstanding a high voltage.

[0180] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the semiconductor devices 1100 .

[0181] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on a specific firmware, and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 for communicating with the semiconductor device 1100. The NAND interface 1221 may be configured to send and receive control commands for controlling the semiconductor device 1100, data written to or read from the memory cell transistors MCT of the semiconductor device 1100, and the like. The host interface 1230 may be configured to implement communication between the electronic system 1000 and an external host. When the processor 1210 receives a control command sent from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0182] Fig. 27 is a schematic perspective view of an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0183] refer to Fig. 27 , an electronic system 2000 according to some embodiments of the inventive concept may include a main substrate 2001, and a controller 2002, at least one semiconductor package 2003, and a DRAM 2004 mounted on the main substrate 2001. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnection pattern 2005 formed in the main substrate 2001.

[0184] The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host. In the connector 2006, the number and arrangement of the pins may be changed according to the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host according to one of the following interfaces: for example, a universal serial bus (USB), a peripheral component interconnect express (PCI express), a serial advanced technology attachment (SATA), a universal flash memory (UFS) M-Phy, etc. In some embodiments, the electronic system 2000 may be driven by power supplied from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) configured to distribute power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0185] The controller 2002 may be configured to control a write or read operation on the semiconductor package 2003 and improve an operation speed of the electronic system 2000 .

[0186] DRAM 2004 may be a buffer memory that alleviates technical difficulties caused by the speed difference between semiconductor package 2003 acting as a data storage device and an external host. In some embodiments, DRAM 2004 in electronic system 2000 may act as a high-speed cache memory and may be used as a storage space configured to temporarily store data during a control operation of semiconductor package 2003. In the case where electronic system 2000 includes DRAM 2004, controller 2002 may include a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0187] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on respective bottom surfaces of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 disposed on the package substrate 2100 to cover the semiconductor chip 2200 and the connection structure 2400.

[0188] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each of the semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.26 The input / output pads 1101 are provided. Each of the semiconductor chips 2200 may include a gate stack 3210 and a vertical structure 3220. Each of the semiconductor chips 2200 may include a semiconductor device to be described below according to some embodiments of the inventive concept.

[0189] In some embodiments, the connection structure 2400 may be a bonding wire, which is provided to electrically connect the input / output pad 2210 to the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in the form of a bonding wire, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via (TSV) instead of through a connection structure 2400 provided in the form of a bonding wire.

[0190] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on an additional interposer substrate different from the main substrate 2001 and may be connected to each other through interconnection lines provided in the interposer substrate.

[0191] Fig.28 and Fig.29 is a cross-sectional view schematically showing a semiconductor package according to some example embodiments of the present disclosure, which conceptually shows a semiconductor package formed by cutting along a cutting line II'. Fig. 27 area obtained by packaging of semiconductors.

[0192] refer to Fig.28 The package substrate 2100 of the semiconductor package 2003 may be a printed circuit board. The package substrate 2100 may include a package substrate main body portion 2120, a package upper pad 2130 (eg, see Fig. 27 ), a lower pad 2125 disposed on or exposed by the bottom surface of the package substrate main body 2120, and an internal line 2135 disposed in the package substrate main body 2120 to electrically connect the package upper pad 2130 to the lower pad 2125. The package upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the conductive connection portion 2800. Fig. 27 The electronic system 2000 is shown with an interconnection pattern 2005 of a main substrate 2001 .

[0193] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 , and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010 .

[0194] Fig.28 The first structure 3100 may correspond to the peripheral circuit structure in the above-mentioned embodiment, and Fig.28 The second structure 3200 may correspond to the cell array structure in the above-mentioned embodiment.

[0195] The first structure 3100 may include a peripheral circuit region including a peripheral line 3110. The second structure 3200 may include a source structure 3205, a gate stack 3210 on the source structure 3205, a vertical structure 3220 and a separation structure 3230 penetrating the gate stack 3210, a bit line 3240 electrically connected to the vertical structure 3220, a bonding structure 3250, and a word line WL (for example, see Fig.26 ) are electrically connected to the cell contact plug 3235. Each of the first and second structures 3100 and 3200 and the semiconductor chip 2200 may further include a separate structure which will be described below.

[0196] Each of the semiconductor chips 2200 may include a through-wire 3245 that is electrically connected to the peripheral interconnection line 3110 of the first structure 3100 and extends into the second structure 3200. The through-wire 3245 may be disposed outside the gate stack 3210, and in some embodiments, the through-wire 3245 may be disposed to further penetrate the gate stack 3210. Each of the semiconductor chips 2200 may also include an input / output pad 2210 (e.g., see Fig. 27 ), which is electrically connected to the outer peripheral line 3110 of the first structure 3100.

[0197] refer to Fig.29 In the semiconductor package 2003A, each of the semiconductor chips 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 in a wafer bonding manner. Fig.29 The first structure 4100 may correspond to the peripheral circuit structure in the above-mentioned embodiment, and Fig.29 The second structure 4200 may correspond to the cell array structure in the above-described embodiment.

[0198] The first structure 4100 may include a peripheral circuit region including a peripheral line 4110 and a first bonding structure 4150. The second structure 4200 may include a source structure 4205, a stack 4210 between the source structure 4205 and the first structure 4100, a vertical structure 4220 and a separation structure 3230 penetrating the stack 4210, and vertical structures 4220 and word lines WL (see, for example, FIG. 4B ) respectively connected to the stack 4210. Fig.26 ) is electrically connected to the second bonding structure 4250. For example, the second bonding structure 4250 can be electrically connected to the bit line 4240 of the vertical structure 4220 and electrically connected to the word line WL (for example, see Fig.26 ) are electrically connected to the vertical structure 4220 and the word line WL (for example, see Fig.26 ). The first bonding structure 4150 of the first structure 4100 may contact and bond with the second bonding structure 4250 of the second structure 4200. The bonding portions of the first bonding structure 4150 and the second bonding structure 4250 may be formed of, for example, copper (Cu), or include, for example, copper (Cu).

[0199] Each of the first structure 4100, the second structure 4200 and the semiconductor chip 2200 may further include a source structure according to some embodiments to be described below. Each of the semiconductor chips 2200 may further include an input / output pad 2210 (eg, see Fig. 27 ), which is electrically connected to the outer line 4110 of the first structure 4100.

[0200] Fig.28 The semiconductor chip 2200 or Fig.29 The semiconductor chips 2200 may be electrically connected to each other through a connection structure 2400 provided in the form of bonding wires. However, in some embodiments, the semiconductor chips (eg, Fig.28 The semiconductor chip 2200 and Fig.29 The semiconductor chips 2200) may be electrically connected to each other through a connection structure including through silicon vias (TSVs).

[0201] According to an embodiment of the present invention, internal supports may be respectively disposed between adjacent external supports, and the distance between the external supports may increase with an increase in the number of stacked conductive patterns and an increase in the diameter of the contact plug, thereby preventing the insulating layer between the supports from collapsing.

[0202] Although the terms (e.g., first, second, or third) may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish elements from each other. For example, without departing from the teachings of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0203] As used herein, an element or region that "covers" or "surrounds" or "fills" another element or region may completely or partially cover or surround or fill or overlap the other element or region. In addition, "element A is connected to element B" (or similar language) may mean that element A is electrically connected to element B and / or element A contacts element B.

[0204] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. Therefore, the exemplary embodiments of the present disclosure are to be considered in all respects as illustrative and not restrictive, and the spirit and scope of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor device, include: a substrate, including a connection region; A stacked structure comprising a conductive pattern stacked on the substrate; an internal support extending into the stack in the connection region; a contact plug extending into the stacked structure and electrically connected to one of the conductive patterns, wherein the contact plug extends at least partially around the inner support member in a plan view; an insulating spacer between the contact plug and the stack structure, wherein in the plan view, the insulating spacer at least partially extends around the contact plug; and An external support member is provided in the connection region, wherein the external support member is spaced apart from the contact plug and extends into the stack structure.

2. The semiconductor device according to claim 1, in, The inner support comprises a first insulating column and the outer support comprises a respective second insulating column.

3. The semiconductor device according to claim 1, in, The internal support includes: a through conductive plug extending into the stack structure; and a through insulating spacer extending at least partially around the through conductive plug in the plan view.

4. The semiconductor device according to claim 1, in, The contact plug and the insulating spacer are in contact with an upper surface of one of the conductive patterns.

5. The semiconductor device according to claim 1, in, The contact plug is between the inner supporter and an adjacent one of the outer supporters.

6. The semiconductor device according to claim 1, in, A distance between the inner supporter and adjacent ones of the outer supporters is smaller than a maximum diameter of the contact plug.

7. The semiconductor device according to claim 1, in, The width of the inner supports is greater than the respective widths of the outer supports.

8. The semiconductor device according to claim 1, in, A width of a lower portion of the inner support member is smaller than a width of an upper portion of the inner support member.

9. The semiconductor device according to claim 1, in, The contact plug has a first thickness between a sidewall of the insulating spacer and a sidewall of the inner support, and Wherein, the first thickness is smaller than the diameter of the inner support member.

10. The semiconductor device according to claim 1, in, The substrate further includes a cell array region, and the semiconductor device further includes: A vertical channel runs through the stacked structure in the cell array region, The distance between the upper surface of the vertical channel and the substrate is different from the distance between the upper surfaces of the inner support and the outer support and the substrate.

11. The semiconductor device according to claim 1, in, In the plan view, the stacked structure extends at least partially around the inner support and the outer support.

12. A semiconductor device, include: A substrate including a cell array region and a connection region; A stacked structure comprising a conductive pattern stacked on the substrate; A vertical channel extending into the stacked structure over the cell array region; a first contact plug extending into the stack structure over the connection region and electrically connected to a first conductive pattern among the conductive patterns; a second contact plug extending into the stack structure over the connection region and electrically connected to a second conductive pattern among the conductive patterns; a first internal support member extending into the first contact plug; a second inner support member extending into the second contact plug; a first insulating spacer between the first contact plug and the stack structure, wherein the first insulating spacer at least partially extends around the first contact plug in a plan view; a second insulating spacer between the second contact plug and the stack structure, wherein in the plan view, the second insulating spacer at least partially extends around the second contact plug; and A plurality of external support members extend into the stack structure and are spaced apart from the first contact plug and the second contact plug on the connection region.

13. The semiconductor device according to claim 12, in, The upper surfaces of the first contact plug and the second contact plug are at substantially the same distance from the substrate.

14. The semiconductor device according to claim 12, in, Upper surfaces of the first and second contact plugs and upper surfaces of the first and second internal supporters are at substantially the same distance from the substrate.

15. The semiconductor device according to claim 12, in, The first inner support and the second inner support have substantially the same length in a direction perpendicular to an upper surface of the substrate.

16. The semiconductor device according to claim 12, in, Each of the first inner supporter and the second inner supporter includes: a through conductive plug extending into the stack structure; and a through insulating spacer extending at least partially around the through conductive plug in the plan view.

17. The semiconductor device according to claim 12, in, The first inner support and the second inner support include respective first insulating columns, and the outer support includes respective second insulating columns.

18. The semiconductor device according to claim 12, in, A diameter of the first contact plug is different from a diameter of the second contact plug.

19. The semiconductor device according to claim 12, in, In the plan view, each of the conductive patterns extends at least partially around the first inner support, the second inner support, and the outer support.

20. An electronic system, include: A semiconductor device comprising a substrate, the substrate comprising a connection region; A stacked structure comprising a conductive pattern stacked on the substrate; an internal support extending into the stack in the connection region; a contact plug extending into a portion of the stack structure and electrically connected to one of the conductive patterns, wherein the contact plug extends at least partially around the inner support member in a plan view; an insulating spacer between the contact plug and the stack structure, wherein in the plan view, the insulating spacer at least partially extends around the contact plug; an external support extending into the stack structure and spaced apart from the contact plug; Input / output pads electrically connected to peripheral circuits; and A controller is electrically connected to the semiconductor device through the input / output pad and is configured to control the semiconductor device.

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