Battery structure and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, and mainly provides a cell structure and a preparation method thereof. The cell structure comprises a perovskite cell, a crystalline silicon high-low junction resistor and a middle composite layer, wherein the crystalline silicon high-low junction resistor comprises a first doped microcrystalline / amorphous silicon layer, a silicon substrate, a second doped microcrystalline / amorphous silicon layer, a first transparent conductive layer and a first electrode which are sequentially stacked in the direction away from the middle composite layer; the doping type of the first doped microcrystalline / amorphous silicon layer and the doping type of the second doped microcrystalline / amorphous silicon layer are the same as the doping type of the silicon substrate. According to the technical scheme, the cell structure can be used for independently representing the electrical performance of the perovskite cell at the top, so that the purpose of independently analyzing the performance of the perovskite cell in the laminated cell is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a cell structure and a preparation method thereof, wherein the cell structure is used to characterize a perovskite / crystalline silicon stacked cell. Background Art

[0002] After years of development, perovskite solar cells have developed rapidly, using crystalline silicon as the bottom cell and perovskite as the top cell. Perovskite / crystalline silicon tandem cells combine the wide bandgap characteristics of perovskite materials with the narrow bandgap characteristics of crystalline silicon, broadening the spectral response range of the cell, thereby improving the photoelectric conversion efficiency of the cell and reducing the preparation cost.

[0003] Perovskite / crystalline silicon tandem cells include perovskite top cells and crystalline silicon bottom cells, and usually have a typical structure of perovskite / n-type amorphous silicon / silicon wafer / p-type amorphous silicon, or two pn junctions are connected in series to form a two-junction tandem cell with a series structure, which has a great advantage in achieving efficiency. However, it is impossible to perform IV testing on a single cell (perovskite cell or crystalline silicon cell) in a perovskite / crystalline silicon tandem cell. When a defect occurs in a perovskite / crystalline silicon tandem cell, it is impossible to analyze what problems caused the defect, for example, it is impossible to know whether it is caused by a matching problem between the perovskite cell and the crystalline silicon cell, or a defect in the crystalline silicon cell itself. As a result, the performance analysis of a single cell is limited, and the battery performance cannot be accurately optimized. Summary of the invention

[0004] The present application provides a battery structure and a preparation method thereof to solve or alleviate the technical problems mentioned above. The battery structure in the technical solution of the present application can be used to separately characterize the electrical properties of the top perovskite battery, thereby achieving the purpose of separately analyzing the performance of the perovskite battery in the stacked battery.

[0005] In a first aspect, an embodiment of the present application provides a battery structure, including: a perovskite battery, a crystalline silicon high and low junction resistor, and an intermediate composite layer connecting the perovskite battery and the crystalline silicon high and low junction resistor;

[0006] The crystalline silicon high-low junction resistor comprises: a first doped microcrystalline / amorphous silicon layer, a silicon substrate, a second doped microcrystalline / amorphous silicon layer, a first transparent conductive layer, and a first electrode, which are sequentially stacked in a direction away from the intermediate composite layer;

[0007] The doping type of the first doped microcrystalline / amorphous silicon layer and the doping type of the second doped microcrystalline / amorphous silicon layer are both the same as the doping type of the silicon substrate.

[0008] Optionally, the crystalline silicon high-low junction resistance further includes: a first intrinsic amorphous silicon layer located between the first doped microcrystalline / amorphous silicon layer and the silicon substrate, and a second intrinsic amorphous silicon layer located between the silicon substrate and the second doped microcrystalline / amorphous silicon layer.

[0009] Optionally, the first doped microcrystalline / amorphous silicon layer is a first P-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer is a second P-type doped microcrystalline / amorphous silicon layer, and the silicon substrate is a P-type silicon substrate;

[0010] The perovskite battery comprises an electron transport layer, a perovskite active layer, a hole transport layer, a second transparent conductive layer, and a second electrode which are sequentially stacked in a direction away from the intermediate composite layer.

[0011] Optionally, the first doped microcrystalline / amorphous silicon layer is a first N-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer is a second N-type doped microcrystalline / amorphous silicon layer, and the silicon substrate is an N-type silicon substrate;

[0012] The perovskite battery comprises a hole transport layer, a perovskite active layer, an electron transport layer, a second transparent conductive layer, and a second electrode which are sequentially stacked in a direction away from the intermediate composite layer.

[0013] Optionally, the material of the intermediate composite layer includes one or both of transparent conductive oxide and conductive metal.

[0014] Optionally, the transparent conductive oxide includes one or more of indium tin oxide, aluminum-doped zinc oxide, indium-doped zinc oxide, and fluorine-doped tin oxide; and / or

[0015] The conductive metal includes one or more of gold, silver, copper, iron, aluminum, and platinum.

[0016] Optionally, the thickness of the intermediate composite layer is 0.1-20 nm.

[0017] Optionally, the doping concentration of the first doped microcrystalline / amorphous silicon layer is 1×10 14 cm -3 -1×10 21 cm -3 The doping concentration of the silicon substrate is 1×10 10 cm -3 -1×10 18 cm -3 The doping concentration of the second doped microcrystalline / amorphous silicon layer is 1×10 14 cm -3 -1×10 21 cm -3 ;

[0018] The doping concentration of the first doped microcrystalline / amorphous silicon layer is greater than the doping concentration of the silicon substrate, and the doping concentration of the second doped microcrystalline / amorphous silicon layer is greater than the doping concentration of the silicon substrate.

[0019] Optionally, the doping concentration of the first doped microcrystalline / amorphous silicon layer is equal to the doping concentration of the second doped microcrystalline / amorphous silicon layer.

[0020] Optionally, the conductivity of the first doped microcrystalline / amorphous silicon layer is 0.1-10 S / cm, the conductivity of the silicon substrate is 0.01-1 S / cm, and the conductivity of the second doped microcrystalline / amorphous silicon layer is 0.1-10 S / cm.

[0021] Optionally, the thickness of the first doped microcrystalline / amorphous silicon layer is 0.5-20 nm, the thickness of the silicon substrate is 10-500 μm, and the thickness of the second doped microcrystalline / amorphous silicon layer is 0.5-20 nm.

[0022] In a second aspect, an embodiment of the present application provides a method for preparing the battery structure described in any one of the above embodiments, comprising:

[0023] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other;

[0024] forming a first doped microcrystalline / amorphous silicon layer on the first surface of the silicon substrate, and forming a second doped microcrystalline / amorphous silicon layer on the second surface of the silicon substrate;

[0025] forming an intermediate composite layer and a perovskite cell in sequence on the first doped microcrystalline / amorphous silicon layer;

[0026] forming a first transparent conductive layer and a first electrode in sequence on the second doped microcrystalline / amorphous silicon layer;

[0027] Wherein, the doping type of the first doped microcrystalline / amorphous silicon layer and the doping type of the second doped microcrystalline / amorphous silicon layer are both the same as the doping type of the silicon substrate;

[0028] The first doped microcrystalline / amorphous silicon layer forms a high-low junction with the silicon substrate, and the second doped microcrystalline / amorphous silicon layer forms a high-low junction with the silicon substrate.

[0029] The above technical solution adopted in the embodiment of the present application may have the following advantages:

[0030] The battery structure in the embodiment of the present application includes a perovskite battery and a crystalline silicon high-low junction resistor, wherein the perovskite battery is the same as the perovskite top battery structure in the perovskite / crystalline silicon stacked battery to be characterized, and the structure of the crystalline silicon high-low junction resistor is p-type microcrystalline / amorphous silicon-silicon wafer-p-type microcrystalline / amorphous silicon or n-type microcrystalline / amorphous silicon-silicon wafer-n-type microcrystalline / amorphous silicon, which does not have a built-in electric field of a pn junction, but forms a pp junction or nn junction, which is equivalent to a resistor. Although the high-low junction has resistance, its resistance value is relatively small and has little effect on the perovskite top battery. In addition, the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer in the crystalline silicon high-low junction resistor are both doped layers, and have a good work function match with the transparent conductive layer, thereby forming a good ohmic contact and avoiding the occurrence of a rectification effect. Therefore, the battery structure in the embodiment of the present application, based on the high and low junction resistances of crystalline silicon, can more accurately measure the IV characteristics of the perovskite top cell, thereby realizing the performance analysis of the perovskite / crystalline silicon stacked battery neutron cell, and then accurately optimizing the battery performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0032] Figure 1 is a schematic diagram of the structure of the battery provided in Example 1 of the present application;

[0033] Figure 2 is a schematic structural diagram of a battery structure provided in Example 2 of the present application;

[0034] Figure 3 It is a flow chart of the method for preparing the battery structure provided in the embodiment of the present application.

[0035] Description of reference numerals:

[0036] 10. Crystalline silicon high and low junction resistance; 11. First doped microcrystalline / amorphous silicon layer; 12. First intrinsic amorphous silicon layer; 13. Silicon substrate; 14. Second intrinsic amorphous silicon layer; 15. Second doped microcrystalline / amorphous silicon layer; 16. First transparent conductive layer; 17. First electrode;

[0037] 20. Intermediate composite layer;

[0038] 30. Perovskite battery; 31. Electron transport layer; 32. Perovskite active layer; 33. Hole transport layer; 34. Second transparent conductive layer; 35. Second electrode. DETAILED DESCRIPTION

[0039] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0040] like Figure 1 and Figure 2 As shown, an embodiment of the present application provides a battery structure, including:

[0041] Perovskite cell 30, crystalline silicon high-low junction resistor 10, and an intermediate composite layer 20 connecting the perovskite cell 30 and the crystalline silicon high-low junction resistor 10;

[0042] The crystalline silicon high-low junction resistor 10 includes: a first doped microcrystalline / amorphous silicon layer 11, a silicon substrate 13, a second doped microcrystalline / amorphous silicon layer 15, a first transparent conductive layer 16, and a first electrode 17, which are sequentially stacked in a direction away from the intermediate composite layer 20;

[0043] The doping type of the first doped microcrystalline / amorphous silicon layer 11 and the doping type of the second doped microcrystalline / amorphous silicon layer 15 are both the same as the doping type of the silicon substrate 13 .

[0044] The battery structure in the embodiment of the present application includes a perovskite battery and a crystalline silicon high-low junction resistor, wherein the perovskite battery is the same as the perovskite top battery structure in the perovskite / crystalline silicon stacked battery to be characterized, and the crystalline silicon high-low junction resistor includes a first doped microcrystalline / amorphous silicon layer, a second doped microcrystalline / amorphous silicon layer, and a silicon substrate. The doping type of the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer are the same as the doping type of the silicon substrate, but the doping concentration of the two is different from the doping concentration of the silicon substrate, so that the first doped microcrystalline / amorphous silicon layer forms a high-low junction with the silicon substrate, and the second doped microcrystalline / amorphous silicon layer forms another high-low junction with the silicon substrate.

[0045] The structure of the high and low junction resistance of crystalline silicon is p-type microcrystalline / amorphous silicon-silicon wafer-p-type microcrystalline / amorphous silicon or n-type microcrystalline / amorphous silicon-silicon wafer-n-type microcrystalline / amorphous silicon. It does not have the built-in electric field of the pn junction, but forms a pp junction or nn junction, which is equivalent to a resistor. Although the high and low junctions have resistance, their resistance values ​​are relatively small and have little effect on the perovskite top battery. In addition, the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer in the high and low junction resistance of crystalline silicon are both doped layers, and have a good work function match with the transparent conductive layer, thereby forming a good ohmic contact and avoiding the generation of the rectification effect. Therefore, the battery structure in the embodiment of the present application, based on the high and low junction resistance of crystalline silicon, can more accurately measure the IV characteristics of the perovskite top battery, thereby realizing the performance analysis of the perovskite / crystalline silicon stacked battery neutron battery, and then accurately optimize the battery performance.

[0046] The middle composite layer can not only connect the perovskite cell on the top and the crystalline silicon high and low junction resistors on the bottom, but also enable the electrons (or holes) in the perovskite cell to effectively recombine with the holes (or electrons) in the crystalline silicon high and low junction resistors to ensure the formation of a complete circuit.

[0047] like Figure 1 and Figure 2 As shown, in some embodiments, the crystalline silicon high-low junction resistor 10 further includes: a first intrinsic amorphous silicon layer 12 located between the first doped microcrystalline / amorphous silicon layer 11 and the silicon substrate 13, and a second intrinsic amorphous silicon layer 14 located between the silicon substrate 13 and the second doped microcrystalline / amorphous silicon layer 15. The first intrinsic amorphous silicon layer 12 and the second intrinsic amorphous silicon layer 14 can effectively passivate the dangling bonds on the surface of the silicon substrate 13 and reduce interface carrier recombination.

[0048] In an optional embodiment, the thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are respectively and independently 0.5-20nm, and specifically, the thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer can be respectively and independently 0.5nm, 1nm, 3nm, 5nm, 8nm, 10nm, 12nm, 15nm or 20nm. In an optional embodiment, the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are formed on the surface of the silicon substrate by one or both of plasma enhanced chemical vapor deposition (PECVD) and hot filament chemical vapor deposition (HWCVD).

[0049] like Figure 1 As shown, in some embodiments, the first doped microcrystalline / amorphous silicon layer 11 is a first P-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer 15 is a second P-type doped microcrystalline / amorphous silicon layer, and the silicon substrate 13 is a P-type silicon substrate 13;

[0050] The perovskite cell 30 includes an electron transport layer 31 , a perovskite active layer 32 , a hole transport layer 33 , a second transparent conductive layer 34 , and a second electrode 35 which are sequentially stacked in a direction away from the intermediate composite layer 20 .

[0051] It should be noted that the first P-type doped microcrystalline / amorphous silicon layer, the second P-type doped microcrystalline / amorphous silicon layer and the P-type silicon substrate contain P-type doping elements (ie, elements such as boron, aluminum, gallium, and indium).

[0052] like Figure 2 As shown, in some embodiments, the first doped microcrystalline / amorphous silicon layer 11 is a first N-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer 15 is a second N-type doped microcrystalline / amorphous silicon layer, and the silicon substrate 13 is an N-type silicon substrate 13;

[0053] The perovskite cell 30 includes a hole transport layer 33 , a perovskite active layer 32 , an electron transport layer 31 , a second transparent conductive layer 34 , and a second electrode 35 which are sequentially stacked in a direction away from the intermediate composite layer 20 .

[0054] It should be noted that the first N-type doped microcrystalline / amorphous silicon layer, the second N-type doped microcrystalline / amorphous silicon layer and the N-type silicon substrate contain N-type doping elements (ie, elements such as phosphorus, arsenic, antimony, and bismuth).

[0055] In an optional embodiment, the perovskite active layer includes a perovskite material, and the perovskite material has a three-dimensional structure, and its general structural formula may be: ABX 3 ; Wherein, A is a monovalent cation, including but not limited to potassium ion (K + ), cesium ion (Cs + ), rubidium ions (Rb + ), methylamine cation (CH 3 NH 3 + ), carboxamidino cation (CH 2 (NH 2 ) 2 + ) is a mixture of one or more of: B is a divalent cation, including but not limited to lead ions (Pb 2+ ), zinc ion (Zn 2+ ), tin ions (Sn 2+ ) is a mixture of one or more of: X is a monovalent anion, including but not limited to iodide ion (I - ), bromide ion (Br - ), chloride ion (Cl -), or a mixture of one or more of the following. In an optional embodiment, the thickness of the perovskite active layer is 100-1000 nm, and specifically, the thickness of the perovskite active layer can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm. In an optional embodiment, the perovskite active layer is prepared by one or more of a spin coating method, a spray pyrolysis method, a thermal evaporation method, a blade coating method, a coating method or a printing method.

[0056] In an optional embodiment, the material of the hole transport layer includes but is not limited to 2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene (Sprio-OMeTAD), poly(bis(4-phenyl)(2,4,6-trimethylphenyl)amine) (PTAA), polymer of 3-hexylthiophene (P3HT), poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid (PEDOT:PS S), 2,2',7,7'-tetrakis (di-p-tolylamino) spiro-9,9'-difluorene (Spiro-TTB), 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanodimethyl-p-benzoquinone (F4-TCNQ), 2,2'-(perfluoronaphthalene-2,6-diylidene) dimalononitrile (F6TCNNQ), 4,4'-cyclohexylbis[N,N-bis(4-methylphenyl)aniline] (TAPC), nickel oxide (NiO x ), tin dioxide (SnO 2 ), cuprous thiocyanate (CuSCN), copper aluminate (CuAlO 2 ), vanadium pentoxide (V 2 O 5 ), cadmium sulfide (CdS), cadmium selenide (CdSe) or more thereof. In an optional embodiment, the thickness of the hole transport layer is 1-500nm, and specifically, the thickness of the hole transport layer can be 1nm, 30nm, 50nm, 100nm, 200nm, 300nm, 400nm or 500nm. In an optional embodiment, the hole transport layer is prepared by one or more of spin coating, thermal evaporation, blade coating, coating or printing.

[0057] In an optional embodiment, the material of the electron transport layer includes but is not limited to TiO 2 SnO 2 、ZnO、ZrO 2 , gallium zinc oxide (GZO), indium zinc oxide (IZO), fluorine-doped tin oxide (FTO), indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), BaSnO 3 、TiSnO x SnZnO x, fullerene, and one or more of fullerene derivatives. Exemplarily, fullerene can be selected from C 60 , C 70 One or two of the fullerene derivatives can be selected from PCBM (such as [6,6]-phenyl-C61-butyric acid isomethyl ester, [6,6]-phenyl-C71-butyric acid isomethyl ester). In an optional embodiment, the thickness of the electron transport layer is 1-500nm, specifically, the thickness of the electron transport layer can be 1nm, 30nm, 50nm, 100nm, 200nm, 300nm, 400nm or 500nm. In an optional embodiment, the electron transport layer is prepared by one or more of a solution method, a magnetron sputtering method, a spray pyrolysis method, a thermal evaporation method, an atomic layer deposition method, a doctor blade method, a coating method or a printing method.

[0058] In an optional embodiment, the materials of the first transparent conductive layer and the second transparent conductive layer include, but are not limited to, one or more of indium tin oxide (ITO), indium zinc oxide (IZO), tungsten-doped indium oxide (IWO), fluorine-doped tin oxide (FTO), cerium-doped indium oxide (ICO), aluminum-doped zinc oxide (AZO), and boron-doped zinc oxide (BZO). In an optional embodiment, the thickness of the first transparent conductive layer and the second transparent conductive layer is 1-500nm, respectively and independently. Specifically, the thickness of the first transparent conductive layer and the second transparent conductive layer can be 1nm, 30nm, 50nm, 100nm, 200nm, 300nm, 400nm or 500nm, respectively and independently. In an optional embodiment, the first transparent conductive layer and the second transparent conductive layer are prepared by one or more of ALD, PECVD, spin coating, sputtering or thermal evaporation.

[0059] In an optional embodiment, the materials of the first electrode and the second electrode respectively and independently include but are not limited to one or more of Au, Ag, Al, Cu, conductive oxides, and graphene, wherein the conductive oxide may include tin oxide (SnO 2 ), titanium oxide (TiO 2 ), indium tin oxide, indium zinc oxide, tungsten-doped indium oxide, aluminum-doped zinc oxide or one or more thereof. In an optional embodiment, the thickness of the first electrode and the second electrode is 1-500nm respectively and independently. Specifically, the thickness of the first electrode and the second electrode can be 1nm, 30nm, 50nm, 100nm, 200nm, 300nm, 400nm or 500nm respectively and independently. In an optional embodiment, the first electrode and the second electrode are prepared by one or both of thermal evaporation method and screen printing method.

[0060] In some embodiments, the material of the intermediate composite layer includes one or both of transparent conductive oxide and conductive metal. The transparent conductive oxide includes one or more of indium tin oxide, aluminum-doped zinc oxide, indium-doped zinc oxide, and fluorine-doped tin oxide; the conductive metal may include one or more of gold, silver, copper, iron, aluminum, and platinum.

[0061] The materials of these intermediate composite layers have good conductivity, which can reduce the internal resistance of the battery, further realize the effective recombination of electrons and holes, and reduce the recombination loss of carriers, thereby more accurately characterizing the electrical properties of the perovskite top battery.

[0062] In some embodiments, the thickness of the intermediate composite layer is 0.1-20nm. When the thickness of the intermediate composite layer is too small, an effective number of composite channels cannot be formed; if the thickness of the intermediate composite layer is too large, the probability of leakage will increase, resulting in abnormal battery performance, and will also cause waste of resources and increase costs. Specifically, the thickness of the intermediate composite layer can be 0.1nm, 1nm, 3nm, 5nm, 7nm, 10nm, 12nm, 15nm, 18nm or 20nm.

[0063] In some embodiments, the doping concentration of the first doped microcrystalline / amorphous silicon layer is 1×10 14 cm -3 -1×10 21 cm -3 , the doping concentration of the silicon substrate is 1×10 10 cm -3 -1×10 18 cm -3 The doping concentration of the second doped microcrystalline / amorphous silicon layer is 1×10 14 cm -3 -1×10 21 cm -3 ;

[0064] The doping concentration of the first doped microcrystalline / amorphous silicon layer is greater than the doping concentration of the silicon substrate, and the doping concentration of the second doped microcrystalline / amorphous silicon layer is greater than the doping concentration of the silicon substrate.

[0065] If the doping concentration in the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer is too low, the mobility of electrons (or holes) will be low. Increasing the doping concentration can improve the conductivity and is also conducive to forming a good ohmic contact with the transparent conductive oxide layer (TCO).

[0066] In addition to the P-type doping element or the N-type doping element, the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer may also contain doping elements such as C and O. When the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer contain only the P-type doping element or the N-type doping element, the doping concentrations of the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer are respectively and independently 1×10 14 cm -3 -1×10 20 cm -3 , specifically 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 or 1×10 20 cm -3 When the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer contain at least one doping element of C and O in addition to the P-type doping element or the N-type doping element, the doping concentrations of the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer are respectively and independently 1×10 14 cm -3 -1×10 21 cm -3 , specifically 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 or 1×10 21 cm -3 .

[0067] The doping concentration of the silicon substrate cannot be too high, otherwise the recombination rate will be too fast; the doping concentration of the silicon substrate cannot be too low, otherwise the resistivity will be too large, affecting the characterization of the perovskite top cell. Specifically, the doping concentration of the silicon substrate can be 1×10 10 cm -3, 1×10 11 cm -3 , 1×10 12 cm -3 , 1×10 13 cm -3 , 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 or 1×10 18 cm -3 .

[0068] In some embodiments, the doping concentration of the first doped microcrystalline / amorphous silicon layer is equal to the doping concentration of the second doped microcrystalline / amorphous silicon layer.

[0069] When the doping concentrations of the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer are equal, the electrical properties on both sides of the silicon substrate can be kept consistent, reducing defects and performance differences caused by mismatch on the two sides, improving the process stability, electrical and optical properties and reliability of the battery, extending the service life of the battery, and reducing the defective rate in the production process.

[0070] In some embodiments, the conductivity of the first doped microcrystalline / amorphous silicon layer is 0.1-10 S / cm, the conductivity of the silicon substrate is 0.01-1 S / cm, and the conductivity of the second doped microcrystalline / amorphous silicon layer is 0.1-10 S / cm.

[0071] The conductivity of the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer are controlled to 0.1-10S / cm respectively and independently, which has a higher conductivity, helps to improve the fill factor and short-circuit current of the battery, and thus improves the overall performance of the battery. The conductivity of the silicon substrate is controlled to 0.01-1S / cm, so that the silicon substrate has a lower conductivity, which helps to reduce electrical losses, reduce the lateral leakage of crystalline silicon cells, and improve the open circuit voltage of the battery. By reasonably adjusting the conductivity of the first doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer, and the silicon substrate, effective matching of the internal current of the battery can be achieved, ensuring the overall photoelectric conversion efficiency of the battery and the stability of the battery. Specifically, the conductivity of the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer can be 0.1S / cm, 0.5S / cm, 1S / cm, 3S / cm, 5S / cm, 7S / cm, 8S / cm or 10S / cm respectively and independently. Specifically, the electrical conductivity of the silicon substrate may be 0.01 S / cm, 0.05 S / cm, 0.1 S / cm, 0.3 S / cm, 0.5 S / cm, 0.6 S / cm, 0.8 S / cm or 1 S / cm.

[0072] In some embodiments, the thickness of the first doped microcrystalline / amorphous silicon layer is 0.5-20 nm, and specifically, the thickness of the first doped microcrystalline / amorphous silicon layer can be 0.5 nm, 1 nm, 5 nm, 10 nm, 13 nm, 15 nm, or 20 nm. In some embodiments, the thickness of the silicon substrate is 10-500 μm, and specifically, the thickness of the silicon substrate can be 10 μm, 50 μm, 100 μm, 200 μm, 250 μm, 300 μm, 400 μm, or 500 μm. In some embodiments, the thickness of the second doped microcrystalline / amorphous silicon layer is 0.5-20 nm, and specifically, the thickness of the second doped microcrystalline / amorphous silicon layer can be 0.5 nm, 1 nm, 5 nm, 10 nm, 13 nm, 15 nm, or 20 nm.

[0073] In an optional embodiment, the battery structure further includes: an anti-reflection layer located on the surface of the second transparent conductive layer.

[0074] In an optional embodiment, the material of the anti-reflection layer includes but is not limited to LiF, MgF 2 、Si 3 N 4 、SiO 2 In an optional embodiment, the thickness of the anti-reflection layer is 0.1 to 5 mm. Specifically, the thickness of the anti-reflection layer can be 0.1 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm, respectively and independently. In an optional embodiment, the anti-reflection layer is prepared by one or more of evaporation, sputtering, and ALD.

[0075] like Figure 3 As shown, the embodiment of the present application provides a method for preparing a battery structure, which is used to prepare the battery structure of any of the above embodiments. The method for preparing the battery structure includes:

[0076] S110: Provide a silicon substrate, where the silicon substrate includes a first surface and a second surface that are opposite to each other.

[0077] In step S110, the silicon substrate may be a P-type silicon substrate or an N-type silicon substrate. The doping type of the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer formed subsequently need to be the same as the doping type of the silicon substrate.

[0078] S120: forming a first doped microcrystalline / amorphous silicon layer on the first surface of the silicon substrate, and forming a second doped microcrystalline / amorphous silicon layer on the second surface of the silicon substrate.

[0079] In step S120, the doping type of the first doped microcrystalline / amorphous silicon layer and the doping type of the second doped microcrystalline / amorphous silicon layer are the same as the doping type of the silicon substrate; the first doped microcrystalline / amorphous silicon layer forms a high-low junction with the silicon substrate, and the second doped microcrystalline / amorphous silicon layer forms a high-low junction with the silicon substrate.

[0080] In step S120, a doped microcrystalline / amorphous silicon layer is formed on the surface of the silicon substrate by using one or both of plasma enhanced chemical vapor deposition (PECVD) and hot filament chemical vapor deposition (HWCVD).

[0081] In step S120, when the silicon substrate is a P-type silicon substrate, one or both of PECVD and HWCVD are used to form a first P-type doped microcrystalline / amorphous silicon layer on the first surface of the silicon substrate, and a second P-type doped microcrystalline / amorphous silicon layer is formed on the second surface of the silicon substrate using P-type doping elements (i.e., boron, aluminum, gallium, indium and other elements).

[0082] In step S120, when the silicon substrate is an N-type silicon substrate, one or both of PECVD and HWCVD are used to form a first N-type doped microcrystalline / amorphous silicon layer on the first surface of the silicon substrate, and a second N-type doped microcrystalline / amorphous silicon layer is formed on the second surface of the silicon substrate using N-type doping elements (i.e., phosphorus, arsenic, antimony, bismuth and other elements).

[0083] S130: sequentially forming an intermediate composite layer and a perovskite cell on the first doped microcrystalline / amorphous silicon layer.

[0084] In step S130, an intermediate composite layer is formed on the first doped microcrystalline / amorphous silicon layer by using one or more of atomic deposition (ALD), PECVD, spin coating, sputtering or thermal evaporation.

[0085] In step S130, when the silicon substrate is a P-type silicon substrate, an electron transport layer, a perovskite active layer, a hole transport layer, a second transparent conductive layer, and a second electrode are sequentially formed on the intermediate composite layer.

[0086] In step S130, when the silicon substrate is an N-type silicon substrate, a hole transport layer, a perovskite active layer, an electron transport layer, a second transparent conductive layer, and a second electrode are sequentially formed on the intermediate composite layer.

[0087] S140: forming a first transparent conductive layer and a first electrode in sequence on the second doped microcrystalline / amorphous silicon layer.

[0088] In some embodiments, before step S120, the method for preparing the battery structure further includes: forming a first intrinsic amorphous silicon layer on the first surface of the silicon substrate, and forming a second intrinsic amorphous silicon layer on the second surface of the silicon substrate.

[0089] In some embodiments, before forming the second electrode, the method for preparing the battery structure further includes: forming an anti-reflection layer on the surface of the second transparent conductive layer, wherein the second electrode formed subsequently burns through the anti-reflection layer and contacts the second transparent conductive layer.

[0090] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application.

[0091] Example 1

[0092] like Figure 1 As shown, the battery structure of Example 1 includes: a perovskite battery, a crystalline silicon high and low junction resistor, and an intermediate composite layer connecting the perovskite battery and the crystalline silicon high and low junction resistor;

[0093] The crystalline silicon high-low junction resistor comprises: a first doped microcrystalline / amorphous silicon layer, a first intrinsic amorphous silicon layer, a silicon substrate, a second intrinsic amorphous silicon layer, a second doped microcrystalline / amorphous silicon layer, a first transparent conductive layer, and a first electrode, which are sequentially stacked in a direction away from the middle composite layer; the first doped microcrystalline / amorphous silicon layer is a first P-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer is a second P-type doped microcrystalline / amorphous silicon layer, and the silicon substrate is a P-type silicon substrate;

[0094] The perovskite battery comprises: an electron transport layer, a perovskite active layer, a hole transport layer, a second transparent conductive layer, and a second electrode which are stacked in sequence in a direction away from the middle composite layer.

[0095] The method for preparing the battery structure of Example 1 comprises:

[0096] S210: Provide a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the silicon substrate is a P-type silicon substrate (doped with boron) with a thickness of 200 μm, and the doping concentration of the silicon substrate is 1×10 16 cm -3 .

[0097] S220: using PECVD, a first intrinsic amorphous silicon layer with a thickness of 5 nm is formed on the first surface of the silicon substrate, and a second intrinsic amorphous silicon layer with a thickness of 5 nm is formed on the second surface of the silicon substrate.

[0098] S230: Using HWCVD, a first P-type doped microcrystalline / amorphous silicon layer with a thickness of 10 nm is formed on the first intrinsic amorphous silicon layer, and a second P-type doped microcrystalline / amorphous silicon layer with a thickness of 10 nm is formed on the second intrinsic amorphous silicon layer; the doping concentration of the first P-type doped microcrystalline / amorphous silicon layer (doped with boron) is 1×10 19 cm -3 The doping concentration of the second P-type doped microcrystalline / amorphous silicon layer (doped with boron) is 1×10 19 cm -3 .

[0099] S240: using ALD to form an intermediate composite layer with a thickness of 5 nm on the first P-type doped microcrystalline / amorphous silicon layer.

[0100] S250: forming an electron transport layer with a thickness of 200 nm on the intermediate composite layer by a thermal evaporation method;

[0101] A perovskite active layer with a thickness of 500 nm is formed on the electron transport layer by a coating method;

[0102] A hole transport layer with a thickness of 200 nm was formed on the perovskite active layer by thermal evaporation.

[0103] S260: using PECVD, a second transparent conductive layer with a thickness of 150 nm is formed on the hole transport layer, and a first transparent conductive layer with a thickness of 150 nm is formed on the second P-type doped microcrystalline / amorphous silicon layer.

[0104] S270: using a screen printing method, forming a first electrode with a thickness of 200 nm on the first transparent conductive layer, and forming a second electrode with a thickness of 200 nm on the second transparent conductive layer.

[0105] Example 2

[0106] like Figure 2 As shown, the battery structure of Example 2 includes: a perovskite battery, a crystalline silicon high and low junction resistor, and an intermediate composite layer connecting the perovskite battery and the crystalline silicon high and low junction resistor;

[0107] The crystalline silicon high-low junction resistor comprises: a first doped microcrystalline / amorphous silicon layer, a first intrinsic amorphous silicon layer, a silicon substrate, a second intrinsic amorphous silicon layer, a second doped microcrystalline / amorphous silicon layer, a first transparent conductive layer, and a first electrode, which are sequentially stacked in a direction away from the middle composite layer; the first doped microcrystalline / amorphous silicon layer is a first N-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer is a second N-type doped microcrystalline / amorphous silicon layer, and the silicon substrate is an N-type silicon substrate;

[0108] The perovskite battery comprises: a hole transport layer, a perovskite active layer, an electron transport layer, a second transparent conductive layer, and a second electrode which are stacked in sequence in a direction away from the middle composite layer.

[0109] The method for preparing the battery structure of Example 2 comprises:

[0110] S310: Provide a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the silicon substrate is an N-type silicon substrate (doped with phosphorus) with a thickness of 200 μm, and the doping concentration of the silicon substrate is 1×10 16 cm -3 .

[0111] S320: using PECVD, a first intrinsic amorphous silicon layer with a thickness of 5 nm is formed on the first surface of the silicon substrate, and a second intrinsic amorphous silicon layer with a thickness of 5 nm is formed on the second surface of the silicon substrate.

[0112] S330: Using HWCVD, a first N-type doped microcrystalline / amorphous silicon layer with a thickness of 10 nm is formed on the first intrinsic amorphous silicon layer, and a second N-type doped microcrystalline / amorphous silicon layer with a thickness of 10 nm is formed on the second intrinsic amorphous silicon layer; the doping concentration of the first N-type doped microcrystalline / amorphous silicon layer (doped with phosphorus) is 1×10 19 cm -3 The doping concentration of the second N-type doped microcrystalline / amorphous silicon layer (doped with phosphorus) is 1×10 19 cm -3 .

[0113] S340: using ALD to form an intermediate composite layer with a thickness of 5 nm on the first N-type doped microcrystalline / amorphous silicon layer.

[0114] S350: forming a hole transport layer with a thickness of 200 nm on the intermediate composite layer by a thermal evaporation method;

[0115] A perovskite active layer with a thickness of 500 nm is formed on the hole transport layer by a coating method;

[0116] An electron transport layer with a thickness of 200 nm was formed on the perovskite active layer by thermal evaporation.

[0117] S360: using PECVD, a second transparent conductive layer with a thickness of 150 nm is formed on the electron transport layer, and a first transparent conductive layer with a thickness of 150 nm is formed on the second N-type doped microcrystalline / amorphous silicon layer.

[0118] S370: Using a screen printing method, a first electrode with a thickness of 200 nm is formed on the first transparent conductive layer, and a second electrode with a thickness of 200 nm is formed on the second transparent conductive layer.

[0119] In order to more clearly illustrate the technical effects of the embodiments of the present application, the present application also points out the battery structure and preparation method of Comparative Example 1 and Reference Example 1.

[0120] Comparative Example 1

[0121] The battery structure of comparative example 1 includes: a perovskite battery, a crystalline silicon battery, and an intermediate composite layer connecting the perovskite battery and the crystalline silicon battery;

[0122] The crystalline silicon cell comprises: a first doped microcrystalline / amorphous silicon layer, a first intrinsic amorphous silicon layer, a silicon substrate, a second intrinsic amorphous silicon layer, a second doped microcrystalline / amorphous silicon layer, a first transparent conductive layer, and a first electrode, which are stacked in sequence in a direction away from the middle composite layer; the first doped microcrystalline / amorphous silicon layer is an N-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer is a P-type doped microcrystalline / amorphous silicon layer, and the silicon substrate is an N-type silicon substrate;

[0123] The perovskite battery comprises: a hole transport layer, a perovskite active layer, an electron transport layer, a second transparent conductive layer, and a second electrode which are stacked in sequence in a direction away from the middle composite layer.

[0124] The preparation method of the battery structure of Comparative Example 1 comprises:

[0125] S410: Provide a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the silicon substrate is an N-type silicon substrate (doped with phosphorus) with a thickness of 200 μm, and the doping concentration of the silicon substrate is 1×10 16 cm -3 .

[0126] S420: using PECVD, a first intrinsic amorphous silicon layer with a thickness of 5 nm is formed on the first surface of the silicon substrate, and a second intrinsic amorphous silicon layer with a thickness of 5 nm is formed on the second surface of the silicon substrate.

[0127] S430: Using HWCVD, an N-type doped microcrystalline / amorphous silicon layer with a thickness of 10 nm is formed on the first intrinsic amorphous silicon layer, and a P-type doped microcrystalline / amorphous silicon layer with a thickness of 10 nm is formed on the second intrinsic amorphous silicon layer; the doping concentration of the N-type doped microcrystalline / amorphous silicon layer (doped element is phosphorus) is 1×10 19 cm-3 The doping concentration of the P-type doped microcrystalline / amorphous silicon layer (doped with boron) is 1×10 19 cm -3 .

[0128] S440: ALD is used to form an intermediate composite layer with a thickness of 5 nm on the N-type doped microcrystalline / amorphous silicon layer.

[0129] S450: forming a hole transport layer with a thickness of 200 nm on the intermediate composite layer by a thermal evaporation method;

[0130] A perovskite active layer with a thickness of 500 nm is formed on the hole transport layer by a coating method;

[0131] An electron transport layer with a thickness of 200 nm was formed on the perovskite active layer by thermal evaporation.

[0132] S460: using PECVD, a second transparent conductive layer with a thickness of 150 nm is formed on the electron transport layer, and a first transparent conductive layer with a thickness of 150 nm is formed on the P-type doped microcrystalline / amorphous silicon layer.

[0133] S470: Using a screen printing method, a first electrode with a thickness of 200 nm is formed on the first transparent conductive layer, and a second electrode with a thickness of 200 nm is formed on the second transparent conductive layer.

[0134] Reference example 1

[0135] The battery structure of Reference Example 1 includes a perovskite battery, which includes a transparent conductive glass (ITO) layer, an electron transport layer, a perovskite active layer, a hole transport layer, a second transparent conductive layer, and a second electrode.

[0136] The preparation method of the battery structure of reference example 1 comprises:

[0137] S510: forming a hole transport layer with a thickness of 200 nm on the ITO layer by a thermal evaporation method;

[0138] A perovskite active layer with a thickness of 500 nm is formed on the hole transport layer by a coating method;

[0139] An electron transport layer with a thickness of 200 nm was formed on the perovskite active layer by thermal evaporation.

[0140] S520: forming a second transparent conductive layer with a thickness of 150 nm on the electron transport layer by using PECVD.

[0141] S530: forming a second electrode with a thickness of 200 nm on the second transparent conductive layer by screen printing.

[0142] The present application also prepares the cell structures of Examples 1-2, Comparative Example 1 and Reference Example 1 into corresponding solar cell modules, and tests the performance of the corresponding solar cell modules, thereby obtaining the short-circuit current density Jsc, open-circuit voltage Voc, fill factor FF, and photoelectric conversion efficiency PCE of the corresponding solar cell modules. The test results are shown in Table 1.

[0143] Table 1

[0144] Voc(V) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) PCE(%) Example 1 1.28 21.3 83.2 22.7 Example 2 1.26 21.6 84.2 22.9 Comparative Example 1 1.94 20.1 81.1 31.6 Reference example 1 1.26 21.6 86.0 23.4

[0145] It can be seen from the data in Table 1 that, compared with the solar cell module of Comparative Example 1, the solar cell modules of Examples 1 to 2 of the present application have significantly lower open circuit voltage and photoelectric conversion efficiency, but higher short circuit current density and fill factor, which indicates that the battery structure of the present application embodiment can effectively avoid the current loss and composite series resistance loss caused by the crystalline silicon bottom battery. In addition, compared with the solar cell module of Reference Example 1, although the fill factor and photoelectric conversion efficiency of the solar cell modules of Examples 1 to 2 of the present application are slightly reduced, there is no significant difference in open circuit voltage and short circuit current density, which is the performance of a single perovskite cell, which indicates that the present application embodiment can effectively strip the perovskite cell from the stacked cell, and can perform separate device optimization and performance characterization.

[0146] In summary, the battery structure in the embodiment of the present application includes a perovskite battery and a crystalline silicon high-low junction resistor, wherein the perovskite battery is the same as the perovskite top battery structure in the perovskite / crystalline silicon stacked battery to be characterized, and the structure of the crystalline silicon high-low junction resistor is p-type microcrystalline / amorphous silicon-silicon wafer-p-type microcrystalline / amorphous silicon or n-type microcrystalline / amorphous silicon-silicon wafer-n-type microcrystalline / amorphous silicon, which does not have a built-in electric field of a pn junction, but forms a pp junction or nn junction, which is equivalent to a resistor. Although the high-low junction has resistance, its resistance value is relatively small and has little effect on the perovskite top battery. In addition, the first doped microcrystalline / amorphous silicon layer and the second doped microcrystalline / amorphous silicon layer in the crystalline silicon high-low junction resistor are both doped layers, and have a good work function match with the transparent conductive layer, thereby forming a good ohmic contact and avoiding the occurrence of a rectification effect. Therefore, the battery structure in the embodiment of the present application, based on the high and low junction resistances of crystalline silicon, can more accurately measure the IV characteristics of the perovskite top cell, thereby realizing the performance analysis of the perovskite / crystalline silicon stacked battery neutron cell, and then accurately optimizing the battery performance.

[0147] It should be noted that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0148] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0149] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0150] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0151] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A battery structure, characterized in that: include: Perovskite cell, crystalline silicon high and low junction resistors, and an intermediate composite layer connecting the perovskite cell and the crystalline silicon high and low junction resistors; The crystalline silicon high-low junction resistor comprises: a first doped microcrystalline / amorphous silicon layer, a silicon substrate, a second doped microcrystalline / amorphous silicon layer, a first transparent conductive layer, and a first electrode, which are sequentially stacked in a direction away from the intermediate composite layer; The doping type of the first doped microcrystalline / amorphous silicon layer and the doping type of the second doped microcrystalline / amorphous silicon layer are both the same as the doping type of the silicon substrate.

2. The battery structure according to claim 1, characterized in that: The crystalline silicon high-low junction resistance also includes: a first intrinsic amorphous silicon layer located between the first doped microcrystalline / amorphous silicon layer and the silicon substrate, and a second intrinsic amorphous silicon layer located between the silicon substrate and the second doped microcrystalline / amorphous silicon layer.

3. The battery structure according to claim 1, characterized in that: The first doped microcrystalline / amorphous silicon layer is a first P-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer is a second P-type doped microcrystalline / amorphous silicon layer, and the silicon substrate is a P-type silicon substrate; The perovskite battery comprises an electron transport layer, a perovskite active layer, a hole transport layer, a second transparent conductive layer, and a second electrode which are sequentially stacked in a direction away from the intermediate composite layer.

4. The battery structure according to claim 1, characterized in that: The first doped microcrystalline / amorphous silicon layer is a first N-type doped microcrystalline / amorphous silicon layer, the second doped microcrystalline / amorphous silicon layer is a second N-type doped microcrystalline / amorphous silicon layer, and the silicon substrate is an N-type silicon substrate; The perovskite battery comprises a hole transport layer, a perovskite active layer, an electron transport layer, a second transparent conductive layer, and a second electrode which are sequentially stacked in a direction away from the intermediate composite layer.

5. The battery structure according to any one of claims 1 to 4, characterized in that: The material of the intermediate composite layer includes one or both of transparent conductive oxide and conductive metal.

6. The battery structure according to claim 5, characterized in that: The transparent conductive oxide comprises one or more of indium tin oxide, aluminum-doped zinc oxide, indium-doped zinc oxide, and fluorine-doped tin oxide; and / or The conductive metal includes one or more of gold, silver, copper, iron, aluminum, and platinum.

7. The battery structure according to any one of claims 1 to 4, characterized in that: The thickness of the intermediate composite layer is 0.1-20 nm.

8. The battery structure according to any one of claims 1 to 4, characterized in that: The doping concentration of the first doped microcrystalline / amorphous silicon layer is 1×10 14 cm -3 -1×10 21 cm -3 The doping concentration of the silicon substrate is 1×10 10 cm -3 -1×10 18 cm -3 The doping concentration of the second doped microcrystalline / amorphous silicon layer is 1×10 14 cm -3 -1×10 21 cm -3 ; The doping concentration of the first doped microcrystalline / amorphous silicon layer is greater than the doping concentration of the silicon substrate, and the doping concentration of the second doped microcrystalline / amorphous silicon layer is greater than the doping concentration of the silicon substrate.

9. The battery structure according to any one of claims 1 to 4, characterized in that: The doping concentration of the first doped microcrystalline / amorphous silicon layer is equal to the doping concentration of the second doped microcrystalline / amorphous silicon layer.

10. The battery structure according to any one of claims 1 to 4, characterized in that: The conductivity of the first doped microcrystalline / amorphous silicon layer is 0.1-10 S / cm, the conductivity of the silicon substrate is 0.01-1 S / cm, and the conductivity of the second doped microcrystalline / amorphous silicon layer is 0.1-10 S / cm.

11. The battery structure according to any one of claims 1 to 4, characterized in that: The thickness of the first doped microcrystalline / amorphous silicon layer is 0.5-20 nm, the thickness of the silicon substrate is 10-500 μm, and the thickness of the second doped microcrystalline / amorphous silicon layer is 0.5-20 nm.

12. A method for preparing a battery structure, characterized in that: include: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other; forming a first doped microcrystalline / amorphous silicon layer on the first surface of the silicon substrate, and forming a second doped microcrystalline / amorphous silicon layer on the second surface of the silicon substrate; forming an intermediate composite layer and a perovskite cell in sequence on the first doped microcrystalline / amorphous silicon layer; forming a first transparent conductive layer and a first electrode in sequence on the second doped microcrystalline / amorphous silicon layer; Wherein, the doping type of the first doped microcrystalline / amorphous silicon layer and the doping type of the second doped microcrystalline / amorphous silicon layer are both the same as the doping type of the silicon substrate; The first doped microcrystalline / amorphous silicon layer forms a high-low junction with the silicon substrate, and the second doped microcrystalline / amorphous silicon layer forms a high-low junction with the silicon substrate.

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