FPGA logic synthesis optimization method and electronic device based on finite state machine

Abstract

The present application provides an FPGA logic synthesis optimization method and electronic device based on a finite state machine, the method comprising: traversing each D flip-flop in a circuit netlist, obtaining the input signal and output signal of the D flip-flop; when the output signal of the D flip-flop belongs to the state signal of the finite state machine, extracting the state signal of each state and saving it in a state signal set according to a preset encoding method, extracting the state transition condition of each state and saving it in a state transition set; eliminating the unreachable states and state transitions in the state signal set, identifying the deadlock state in the state signal set; for each state signal and state transition condition of the finite state machine, generating a multiplexer unit and a trigger unit for each state signal, and deleting the D flip-flop from the circuit netlist. The present application can accurately and effectively optimize the logic of the finite state machine, reducing the number of resources after FPGA logic synthesis.

Description

Technical Field

[0001] The present application belongs to the field of FPGA technology, and in particular relates to an FPGA logic synthesis optimization method and electronic device based on a finite state machine. Background Art

[0002] Logic synthesis is an important step in the FPGA EDA software design process. It converts the Verilog / VHDL circuit files at the behavioral level or register transfer level (RTL) input by the user into a netlist file composed of FPGA basic logic units such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis is to convert the circuit files at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping is to map the logic netlist composed of gate circuits into a netlist file composed of FPGA basic logic units.

[0003] Area, that is, the number of resources, is an important indicator of FPGA logic synthesis tools. Reducing the number of resources after FPGA logic synthesis is very important for improving the routing rate and timing performance of FPGA software. State control can realize complex logic functions and can be physically realized through logic hardware. Complex Verilog application circuit design systems usually contain finite state control machines.

[0004] Finite state machine is a mathematical model that represents the behavior of realizing a finite number of discrete states and the transition between states. Synthesis tools usually need to occupy a large amount of logic resources to realize finite state machines. If the finite state machine cannot be effectively optimized, a large amount of logic resources will be consumed. Therefore, the optimization of finite state machines is an urgent problem to be solved. Summary of the invention

[0005] The present application discloses a finite state machine-based FPGA logic synthesis optimization method and electronic device, which can accurately and effectively optimize the logic of the finite state machine and reduce the number of logic resources after logic synthesis.

[0006] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0007] To achieve one or part or all of the above purposes or other purposes, in a first aspect, the present application provides an FPGA logic synthesis optimization method based on a finite state machine, the method comprising: traversing each D flip-flop in a circuit netlist to obtain the input signal and output signal of the D flip-flop; when the output signal of the D flip-flop belongs to the state signal of the finite state machine, extracting the state signal of each state and saving it in a state signal set according to a preset encoding method, extracting the state transition condition of each state and saving it in a state transition set; eliminating unreachable states and state transitions in the state signal set, and identifying deadlock states in the state signal set; for each state signal and state transition condition of the finite state machine, generating a multiplexer unit and a trigger unit for each of the state signals, and deleting the D flip-flop from the circuit netlist.

[0008] In one implementation, if the output signal of the D flip-flop satisfies the following three conditions, then the output signal of the D flip-flop belongs to the state signal of the finite state machine, and the three conditions include: Condition 1: the right-value signal of the assignment statement of the output signal of the D flip-flop has a certain constant value set; Condition 2: the operation type of the logic unit with the output signal of the D flip-flop as the input signal is an equality comparison operation or a logical negation type, or the output signal of the D flip-flop is on a branch path that can be reached by the input signal of the D flip-flop; Condition 3: the path of the assignment statement of the output signal of the D flip-flop contains the condition that the output terminal signal is equal to a constant value in the constant value set.

[0009] In one implementation, determining whether the output signal of the D flip-flop satisfies condition 2 includes: recursively traversing each logic unit c in the circuit netlist; if the input signal of the logic unit c includes the output signal of the D flip-flop, storing the logic unit c in the first logic unit set; obtaining a multiplexer unit m that uses the input signal of the D flip-flop as an output signal, obtaining the input signal of the multiplexer unit m, and if at least one input signal of the multiplexer unit m is the same as the output signal of the D flip-flop, deleting the multiplexer unit m from the first logic unit set; until the input signal of the multiplexer unit m is different from the output signal of any multiplexer unit, and generating a second logic unit set; wherein the logic units in the second logic unit set are equal comparison operations or logical negation types.

[0010] In one implementation, determining whether the output signal of the D flip-flop satisfies condition three includes obtaining a multiplexer unit m that uses the input signal of the D flip-flop as the output signal, recursively traversing the input B-end signal of the multiplexer unit m and the selection signal sig_s1 corresponding to the input B-end signal, and querying a first logic unit c1 that uses the selection signal sig_s1 as the output signal. If the first logic unit c1 is not an equal comparison operation type or the input A-end signal of the first logic unit c1 is different from the output signal of the D flip-flop, obtaining a recursive return value b1; if the first logic unit c1 is an equal comparison operation type, If the comparison operation type is the same as the output signal of the D flip-flop and the input A-end signal of the first logic unit c1 is the same as the output signal of the D flip-flop, the input A-end signal of the multiplexer unit m and the selection signal sig_s2 corresponding to the input A-end signal are obtained, and the second logic unit c2 with the selection signal sig_s2 as the output signal is queried. If the second logic unit c2 is not the same as the comparison operation type or the input A-end signal of the second logic unit c2 is different from the output signal of the D flip-flop, the recursive return value b2 is obtained. If the return value b1 and the return value b2 are both TRUE, the output signal of the D flip-flop satisfies condition three.

[0011] In one implementation, the preset encoding method is a one-hot encoding method.

[0012] In one implementation, the state signal of each state is extracted and saved in a state signal set, and the state transition condition of each state is extracted and saved in a state transition set, including obtaining a multiplexer unit in the circuit netlist with an input signal of a D flip-flop as an output signal; recursively traversing the input terminal signals of the multiplexer unit in turn, extracting each state transition condition and saving it in a state transition set.

[0013] In one implementation, the input terminal signal of the multiplexer unit is recursively traversed, and each state transition condition is extracted and saved in a state transition set, including recursively traversing a third logic unit c3 with the input B terminal signal of the multiplexer unit as the output signal; if the type of the third logic unit c3 is an equal comparison operation type, and the input A terminal signal of the third logic unit c3 is the same as the output signal of the D flip-flop, then the constant value v1 represented by the input B terminal signal of the third logic unit c3 is obtained, and the first starting state v0 is obtained from the branch path p, and a state transition t1 is generated in which the state takes effect with the first starting state v0 as the starting state, p as the state transition condition, and the constant value v1 as the target state, and a state transition t2 is generated in which the state takes effect with the first starting state v0 as the starting state, p as the state transition condition, and the first starting state v0 as the target state; and the state transition t1 and the state transition t2 are saved in the state transition set.

[0014] In one implementation, unreachable states and state transitions in the state signal set are eliminated, and deadlock states in the state signal set are identified, including looping through each state signal s in the state signal set to obtain a state transition set T1 in which the state of the state signal s is effective and a state transition set T2 in which the state of the state signal s is invalid; traversing each state transition t1 in the state transition set T1, and if the starting state of the state transition t1 is in the unreachable state set, deleting the state transition t1 from the state transition set T1; if the number of elements in the state transition set T2 is 0, adding the state signal s to the deadlock state set.

[0015] In one implementation, for each state signal and state transition condition of a finite state machine, a multiplexer unit and a trigger unit are generated for each state signal, including, for each state signal s in the state signal set, obtaining a state transition set T1 in which the state of the state signal s is effective and a state transition set T2 in which the state of the state signal s is invalid; based on the state transition t1 in the state transition set T1, obtaining a second starting state s0 and a state transition condition p1, and generating a logic AND signal sig1 based on the state transition condition p1; if the state transition set T1 is the same as the state transition set T2, a multiplexer unit is generated; wherein the input S-end signal of the multiplexer unit is equal to the logic AND signal sig1, the input B-end signal of the multiplexer unit is equal to the second starting state s0, and the input A-end signal of the multiplexer unit is equal to state signal s; if the state transition set T1 and the state transition set T2 are different, then based on the state transition t2 in the state transition set T2, the state transition condition p2 is obtained, and a logic signal sig2 is generated based on the state transition condition p2; an AND signal and1 is generated with the inverted signal of the logic signal sig2 and the state signal s as input signals, and a multiplexer unit is generated; wherein the input S-end signal of the multiplexer unit is equal to the second starting state s0, the input B-end signal of the multiplexer unit is equal to the logic signal sig1, and the input A-end signal of the multiplexer unit is equal to the AND signal and1; a trigger unit is generated for the state signal s; wherein the input signal of the trigger unit is equal to the output signal of the multiplexer unit, and the output signal of the trigger unit is equal to the state signal s.

[0016] In one implementation, after deleting the D flip-flop from the circuit netlist, each logic unit c in the circuit netlist is traversed again. If the operation type of the logic unit c is an equal comparison operation or a logical negation type, and the input A-end signal of the logic unit c is the same as the state signal s in the state signal set, then a connection is established in the circuit netlist from the output Y-end signal of the logic unit c to the state signal s.

[0017] In a second aspect, the present application provides a computer-readable storage medium, in which program code is stored, and the program code is called by a processor to execute any one of the finite state machine-based FPGA logic synthesis optimization methods of the first aspect.

[0018] In a third aspect, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an FPGA logic synthesis optimization method based on a finite state machine as described in any one of the first aspects.

[0019] The above-mentioned FPGA logic synthesis optimization method based on the finite state machine extracts the state signal and state transition condition of each state according to the preset coding method when the output signal of the D flip-flop unit belongs to the state signal of the finite state machine; and eliminates the unreachable states and state transitions in the state signal set, identifies the deadlock state in the state signal set, generates the multiplexer unit and the flip-flop unit for each state signal, and deletes the D flip-flop unit from the circuit netlist. Thus, accurate and effective logic optimization of the finite state machine is achieved, and the number of logic resources after logic synthesis is reduced.

[0020] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a flow chart of the FPGA logic synthesis optimization method based on the finite state machine of this application.

[0023] Figure 2 This is a flow chart of determining whether the output signal of a D flip-flop satisfies condition 2 in the present application.

[0024] Figure 3 This is a flow chart of determining whether the output signal of a D flip-flop satisfies condition three in the present application.

[0025] Figure 4 A flowchart of the state signal and state transition conditions for each state is extracted for this application.

[0026] Figure 5 A flowchart of eliminating unreachable states and state transitions in a state signal set for this application.

[0027] Figure 6 A flow chart of a multiplexer unit and a trigger unit for generating each state signal for the present application. DETAILED DESCRIPTION

[0028] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0029] Embodiment 1 provides a FPGA logic synthesis optimization method based on a finite state machine. By traversing each D flip-flop unit in the circuit netlist, when the output signal of the D flip-flop unit belongs to the state signal of the finite state machine, the state signal and state transition condition of each state are extracted according to a preset encoding method. And by eliminating the unreachable states and state transitions in the state signal set, the deadlock state in the state signal set is identified to optimize the state signal set. For each state signal and state transition condition of the finite state machine, a multiplexer unit and a trigger unit for each state signal are generated, and the D flip-flop unit is deleted from the circuit netlist. Thereby, accurate and effective logic optimization of the finite state machine is achieved, and the number of logic resources after logic synthesis is reduced.

[0030] The present application is described in detail below with reference to the accompanying drawings.

[0031] refer to Figure 1 The embodiment of the present application provides an FPGA logic synthesis optimization method based on a finite state machine, comprising the following steps:

[0032] Step S101: traverse each D flip-flop in the circuit netlist to obtain the input D-end signal sig_d and the output Q-end signal sig_q of the D flip-flop.

[0033] Step S102: When the output signal sig_q of the D flip-flop belongs to the state signal of the finite state machine, the state signal of each state is extracted and saved in the state signal set, and the state transition condition of each state is extracted and saved in the state transition set according to the preset encoding method. The preset encoding method can be but is not limited to one-hot code, etc.

[0034] Step S103: Eliminate unreachable states and state transitions in the state signal set, and identify deadlock states in the state signal set.

[0035] Step S104: for each state signal and state transition condition of the finite state machine, generate a multiplexer unit and a trigger unit for each state signal, and delete the D trigger from the circuit netlist.

[0036] After deleting the D flip-flop from the circuit netlist, you can traverse each logic unit c in the netlist again. If the operation type of the logic unit c is an equal comparison operation or a logical negation type, and the input A-end signal of the logic unit c is the same as the state signal s in the state signal set, then establish a connection from the output Y-end signal of the logic unit c to the state signal s in the circuit netlist. Through this process, the circuit netlist can be reconstructed so that the state signal can be directly driven by the output of the logic unit, further improving the logic optimization of the finite state machine.

[0037] In one implementation, the output signal of the D flip-flop belongs to the state signal of the finite state machine and needs to meet the following three conditions:

[0038] Condition 1: The right-hand side signal of the assignment statement of the output signal of the D flip-flop has a certain set of constant values. This means that the finite state machine has a finite number of discrete states, and each state can be represented by a constant value in the constant value set V.

[0039] Condition 2: The operation type of the logic unit that uses the output signal of the D flip-flop as the input signal is an equality comparison operation or a logical negation type, or the output signal of the D flip-flop is on a branch path that can be reached by the input signal of the D flip-flop.

[0040] Condition three: The path of the assignment statement for the output signal of the D flip-flop contains the condition that the output signal is equal to a constant value in the constant value set.

[0041] refer to Figure 2 , judging whether the output signal of the D flip-flop satisfies condition 2 comprises the following steps:

[0042] Step S201: recursively traverse each logic unit c in the netlist.

[0043] Step S202: Determine whether the input signal of the logic unit c includes the output signal sig_q of the D flip-flop; if so, execute step S203; if not, return to step S201.

[0044] Step S203: if the input signal of the logic unit c includes the output signal sig_q of the D flip-flop, the logic unit c is stored in a logic unit set L (ie, a first logic unit set), where the logic unit set L is a set of logic units using sig_q.

[0045] Step S204: obtaining a multiplexer unit m that uses the input signal sig_d of the D flip-flop as the output signal.

[0046] Step S205: Obtain the input B-end signal sig_b of the multiplexer unit m.

[0047] Step S206: Determine whether the input B-end signal sig_b of the multiplexer unit m is the same as the output signal sig_q of the D flip-flop; if so, execute step S207; if not, execute step S208.

[0048] Step S207: if the input B-end signal sig_b of the multiplexer unit m is the same as the output signal sig_q of the D flip-flop, the multiplexer unit m is deleted from the logic unit set L.

[0049] Step S208: determine whether the input B-end signal sig_b of the multiplexer unit m is the output signal sig_q of a certain multiplexer unit; if so, return to step S204, if not, execute step S209.

[0050] Step S209: Obtain the input A-end signal sig_a of the multiplexer unit m.

[0051] Step S210: Determine whether the input A-end signal sig_a of the multiplexer unit m is the same as the output signal sig_q of the D flip-flop; if so, execute step S211, if not, execute step S212.

[0052] Step S211: if the input A-end signal sig_a of the multiplexer unit m is the same as the output signal sig_q of the D flip-flop, the multiplexer unit m is deleted from the logic unit set L.

[0053] Step S212: determine whether the input A-end signal sig_a of the multiplexer unit m is the output signal of a certain multiplexer unit; if so, return to step S204, if not, execute step S213.

[0054] Step S213: traverse each remaining logical unit in the logical unit set L (ie, the logical units in the second logical unit set).

[0055] Step S214: Determine whether the logic unit is an equality comparison operation or a logic negation type. If so, the output signal of the D flip-flop satisfies condition 2; if not, the output signal of the D flip-flop does not satisfy condition 2.

[0056] refer to Figure 3 , judging whether the output signal of the D flip-flop satisfies condition three includes the following steps:

[0057] Step S301: obtaining a multiplexer unit m that uses an input signal sig_d of a D flip-flop as an output signal.

[0058] Step S302: traverse the input B-end signal sig_b of the multiplexer unit m and the selection signal sig_s1 corresponding to the input B-end signal sig_b.

[0059] Step S303: query to select the signal sig_s1 as the first logic unit c1 of the output signal.

[0060] Step S304: Determine whether the first logic unit c1 is not an equality comparison operation type or whether the input A terminal signal of the first logic unit c1 is not equal to sig_q; if so, execute step S305, if not, execute step S307.

[0061] Step S305: recursively execute steps S302 to S304 on the input B-end signal sig_b of the multiplexer unit m to obtain a recursive return value b1.

[0062] Step S306: Determine whether the return value b1 is equal to FALSE; if so, the output signal of the D flip-flop does not meet condition three, if not, execute step S307.

[0063] Step S307: obtaining the input A-end signal of the multiplexer unit m and the selection signal sig_s2 corresponding to the input A-end signal.

[0064] Step S308: query to select the signal sig_s2 as the second logic unit c2 of the output signal.

[0065] Step S309: Determine whether the second logic unit c2 is not of the equality comparison operation type or whether the input A-end signal of the second logic unit c2 is not equal to sig_q; if so, execute step S310; if not, execute step S307.

[0066] Step S310: recursively execute steps S307 to S309 on the input B-end signal sig_b of the multiplexer unit m to obtain a recursive return value b2.

[0067] Step S311: Determine whether the return value b2 is equal to FALSE; if so, the output signal of the D flip-flop does not meet condition three, if not, execute step S312.

[0068] Step S312: When the return value b1 and the return value b2 are both TRUE, the output signal of the D flip-flop satisfies condition three.

[0069] Through the above judgment logic, the efficiency and accuracy of identifying that the output signal of the D flip-flop meets conditions two and three can be improved, thereby improving the reliability of identifying that the output signal of the D flip-flop belongs to the state signal of the finite state machine.

[0070] In one implementation, the preset encoding method is a one-hot encoding method, which can improve the accuracy and effectiveness of representing the state signal of the finite state machine, thereby accurately and effectively optimizing the state transition logic, and helping to reduce the number of logic resources after synthesis. For example, if the finite state machine has 3 states and is encoded using a one-hot encoding, then the constant value set V may include values ​​such as 000, 001, 010, etc.

[0071] In one implementation, a multiplexer unit with a D flip-flop input signal as an output signal is obtained in a circuit netlist, and the input signals of the multiplexer unit are recursively traversed in sequence, each state transition condition is extracted and saved in a state transition set, so as to accurately extract the state signal and state transition condition of each state, thereby providing necessary information for further logic optimization and logic synthesis.

[0072] refer to Figure 4 ,The process of extracting the state signal and state transition condition of each state specifically includes the following steps:

[0073] Step S401: recursively traverse the third logic unit c3 that uses the multiplexer unit input B-end signal sig_b as the output signal.

[0074] Step S402: Determine whether the operation type of the third logic unit c3 is an equal comparison operation type, and whether the input A terminal signal of the third logic unit c3 is equal to the output signal sig_q of the D flip-flop; if so, execute step S403, if not, execute step S407.

[0075] Step S403: If the type of the third logic unit c3 is the equality comparison operation type, and the input A-end signal of the third logic unit c3 is the same as the output signal of the D flip-flop, then the constant value v1 represented by the input B-end signal of the third logic unit c3 is obtained.

[0076] Step S404: Obtain the first starting state v0 from the branch path p.

[0077] Step S405: Generate a state transition t1 that takes v0 as the starting state, p as the state transition condition, and v1 as the target state.

[0078] Step S406: Generate a state failure state transition t2 with v0 as the starting state, p as the state transition condition, and v0 as the target state.

[0079] Step S407: determine whether the type of the third logic unit c3 is a multiplexer, if so, execute step S408, if not, exit the processing flow.

[0080] Step S408: adding the selection signal sig_s corresponding to the signal sig_b at the input B end of the multiplexer unit to the current branch path p, and saving the state transition t1 and the state transition t2 to the state transition set.

[0081] Step S409: recursively execute steps S401 to S408 on the input B-end signal sig_b of the multiplexer unit.

[0082] refer to Figure 5 , eliminating the unreachable states and state transitions in the state signal set, and identifying the deadlock state in the state signal set specifically includes the following steps:

[0083] Step S501: traverse each state signal s in the state signal set.

[0084] Step S502: Acquire a state transition set T1 in which the state of the state signal s is effective.

[0085] Step S503: traverse each state transition t1 in the state transition set T1 in which the state is effective.

[0086] Step S504: Determine whether the second starting state s0 of state transition t1 is in the unreachable state set U; if so, execute step S505; if not, return to step S503.

[0087] Step S505: Delete the state transition t1 from the state-validated state transition set T1.

[0088] Step S506: Determine whether the number of elements in the state transition set T1 in which the state is effective is equal to 0; if so, execute step S507; if not, execute step S508.

[0089] Step S507: Add the state signal s to the unreachable state set U.

[0090] Step S508: Acquire a state transition set T2 of the state failure of the state signal s.

[0091] Step S509: Determine whether the number of elements in the state transition set T2 of the state failure is equal to 0; if so, execute step S510, if not, execute step S511.

[0092] Step S510: adding the state signal s to the deadlock state set D.

[0093] Step S511: Determine whether the elements in the unreachable state set U have changed; if so, return to step S501; if not, exit this optimization.

[0094] Through this process, the efficiency of logic synthesis can be improved, and it helps to discover potential unreachable states or deadlocks, thereby improving the accuracy and reliability of the optimized finite state machine.

[0095] refer to Figure 6 , for each state signal and state transition condition of the finite state machine, the process of generating the multiplexer unit and the trigger unit of each state signal specifically includes the following steps:

[0096] Step S601: traverse each state signal s in the state signal set.

[0097] Step S602: Acquire a state transition set T1 of a state-validated state and a state transition set T2 of a state-invalidated state of the state signal s.

[0098] Step S603: Obtain the second starting state s0 and the state transition condition p1 from the state transition t1 of the state transition set T1, and generate a logic AND signal sig1 according to the state transition condition p1.

[0099] Step S604: Determine whether the state transition set T1 is equal to the state transition set T2; if so, execute step S605; if not, execute step S606.

[0100] Step S605: Generate a first multiplexer unit m1, the input S-end signal of the first multiplexer unit m1 is equal to the logic AND signal sig1, the input B-end signal of the first multiplexer unit m1 is equal to the second starting state s0, and the input A-end signal of the first multiplexer unit m1 is equal to the state signal s.

[0101] Step S606: Obtain the state transition condition p2 from the state transition t2 of the state transition set T2, and generate a logical AND signal sig2 according to the state transition condition p2.

[0102] Step S607: Generate an AND signal and1, wherein the AND signal and1 takes the negated signal of the logical AND signal sig2 and the state signal s as input signals.

[0103] Step S608: Generate a first multiplexer unit m1, the input S-end signal of the first multiplexer unit m1 is equal to the second starting state s0, the input B-end signal of the first multiplexer unit m1 is equal to the logic AND signal sig1, and the input A-end signal of the first multiplexer unit m1 is equal to the AND signal and1.

[0104] Step S609: Generate a trigger unit d1 for the state signal s, the input D-end signal of the trigger unit d1 is equal to the output signal of the first multiplexer unit m1, and the output Q-end signal of the trigger unit d1 is equal to the state signal s. The trigger unit is a D trigger.

[0105] In summary, the FPGA logic synthesis optimization method based on the finite state machine of the present application can not only realize the accurate and effective identification and encoding of the finite state machine, but also improve the practicality of the judgment rules of the finite state machine through further logic optimization, and improve the efficiency of the state signal generation logic unit, thereby reducing the number of logic resources after logic synthesis and reducing the area of ​​FPGA logic synthesis.

[0106] Embodiment 2 provides a computer-readable storage medium, in which a program code is stored. The program code is called by a processor to execute any of the above-mentioned finite state machine-based FPGA logic synthesis optimization methods.

[0107] Embodiment 3 provides an electronic device, which includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute any of the above-mentioned finite state machine-based FPGA logic synthesis optimization methods.

[0108] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A FPGA logic synthesis optimization method based on a finite state machine, characterized in that: The method comprises: Traversing each D flip-flop in the circuit netlist to obtain an input signal and an output signal of the D flip-flop; When the output signal of the D flip-flop belongs to the state signal of the finite state machine, the state signal of each state is extracted and saved in the state signal set according to the preset encoding method, and the state transition condition of each state is extracted and saved in the state transition set; Eliminating unreachable states and state transitions in the state signal set, and identifying deadlock states in the state signal set; For each state signal and state transition condition of the finite state machine, a multiplexer unit and a trigger unit are generated for each state signal, and the D trigger is deleted from the circuit netlist.

2. The FPGA logic synthesis optimization method based on finite state machine according to claim 1, characterized in that: If the output signal of the D flip-flop satisfies the following three conditions, then the output signal of the D flip-flop belongs to the state signal of the finite state machine, and the three conditions include: Condition 1: the right-hand side signal of the assignment statement of the output signal of the D flip-flop has a certain constant value set; Condition 2: the operation type of the logic unit that uses the output signal of the D flip-flop as the input signal is an equal comparison operation or a logical negation type, or the output signal of the D flip-flop is on a branch path that the input signal of the D flip-flop can reach; Condition three: the path of the assignment statement of the output signal of the D flip-flop contains the condition that the output terminal signal is equal to a constant value in the constant value set.

3. The FPGA logic synthesis optimization method based on finite state machine according to claim 2 is characterized in that: Determining whether the output signal of the D flip-flop satisfies condition 2 includes: Recursively traverse each logic unit c in the circuit netlist, and if the input signal of the logic unit c includes the output signal of the D flip-flop, store the logic unit c in the first logic unit set; Obtain a multiplexer unit m that uses the input signal of the D flip-flop as an output signal, obtain the input signal of the multiplexer unit m, and if at least one input signal of the multiplexer unit m is the same as the output signal of the D flip-flop, delete the multiplexer unit m from the first logic unit set; Until the input signal of the multiplexer unit m is different from the output signal of any multiplexer unit, and a second logic unit set is generated; wherein the logic units in the second logic unit set are equal comparison operation or logical negation type.

4. The FPGA logic synthesis optimization method based on finite state machine according to claim 2 is characterized in that: Determining whether the output signal of the D flip-flop satisfies condition three includes: Obtain a multiplexer unit m that uses the input signal of the D flip-flop as the output signal, recursively traverse the input B-end signal of the multiplexer unit m and the selection signal sig_s1 corresponding to the input B-end signal, and query the first logic unit c1 that uses the selection signal sig_s1 as the output signal. If the first logic unit c1 is not an equal comparison operation type or the input A-end signal of the first logic unit c1 is different from the output signal of the D flip-flop, obtain a recursive return value b1; If the first logic unit c1 is an equal comparison operation type and the input A-end signal of the first logic unit c1 is the same as the output signal of the D flip-flop, then the input A-end signal of the multiplexer unit m and the selection signal sig_s2 corresponding to the input A-end signal are obtained, and the second logic unit c2 with the selection signal sig_s2 as the output signal is queried; if the second logic unit c2 is not an equal comparison operation type or the input A-end signal of the second logic unit c2 is different from the output signal of the D flip-flop, the recursive return value b2 is obtained; if the return value b1 and the return value b2 are both TRUE, the output signal of the D flip-flop satisfies condition three.

5. The FPGA logic synthesis optimization method based on finite state machine according to claim 1 is characterized in that: The preset encoding method is a one-hot encoding method.

6. The FPGA logic synthesis optimization method based on finite state machine according to claim 5 is characterized in that: Extract the state signal of each state and save it in the state signal set, extract the state transition condition of each state and save it in the state transition set, include, Acquire a multiplexer unit in the circuit netlist that uses an input signal of a D flip-flop as an output signal; Recursively traverse the input signals of the multiplexer unit in turn, extract each state transition condition and save it in the state transition set.

7. The FPGA logic synthesis optimization method based on finite state machine according to claim 6 is characterized in that: Recursively traverse the input signals of the multiplexer unit, extract each state transition condition and save it to the state transition set, including, Recursively traverse the third logic unit c3 that uses the multiplexer unit input terminal B signal as the output signal; If the type of the third logic unit c3 is an equal comparison operation type, and the input A-end signal of the third logic unit c3 is the same as the output signal of the D flip-flop, then the constant value v1 represented by the input B-end signal of the third logic unit c3 is obtained, and the first starting state v0 is obtained from the branch path p, and a state transition t1 in which the state is effective with the first starting state v0 as the starting state, p as the state transition condition, and the constant value v1 as the target state is generated, and a state transition t2 in which the state is invalid with the first starting state v0 as the starting state, p as the state transition condition, and the first starting state v0 as the target state is generated; The state transition t1 and the state transition t2 are saved in a state transition set.

8. The FPGA logic synthesis optimization method based on finite state machine according to claim 1 is characterized in that: Eliminating unreachable states and state transitions in the state signal set, and identifying deadlock states in the state signal set, including: Loop through each state signal s of the state signal set, and obtain a state transition set T1 where the state of the state signal s is effective and a state transition set T2 where the state of the state signal s is invalid; Traverse each state transition t1 in the state transition set T1, and if the starting state of the state transition t1 is in the unreachable state set, delete the state transition t1 from the state transition set T1; If the number of elements in the state transition set T2 is 0, the state signal s is added to the deadlock state set.

9. The FPGA logic synthesis optimization method based on finite state machine according to claim 1, characterized in that: For each state signal and state transition condition of the finite state machine, a multiplexer unit and a trigger unit are generated for each state signal, including: For each state signal s in the state signal set, obtaining a state transition set T1 in which the state of the state signal s is valid and a state transition set T2 in which the state of the state signal s is invalid; Based on the state transition t1 in the state transition set T1, a second starting state s0 and a state transition condition p1 are obtained, and a logic AND signal sig1 is generated based on the state transition condition p1; If the state transition set T1 is the same as the state transition set T2, a multiplexer unit is generated; wherein the input S terminal signal of the multiplexer unit is equal to the logic AND signal sig1, the input B terminal signal of the multiplexer unit is equal to the second starting state s0, and the input A terminal signal of the multiplexer unit is equal to the state signal s; If the state transition set T1 is different from the state transition set T2, then based on the state transition t2 in the state transition set T2, the state transition condition p2 is obtained, and a logic AND signal sig2 is generated based on the state transition condition p2; Generate an AND signal and1 with the negated signal of the logic AND signal sig2 and the state signal s as input signals, and generate a multiplexer unit; wherein the input S terminal signal of the multiplexer unit is equal to the second starting state s0, the input B terminal signal of the multiplexer unit is equal to the logic AND signal sig1, and the input A terminal signal of the multiplexer unit is equal to the AND signal and1; A trigger unit is generated for the state signal s; wherein the input signal of the trigger unit is equal to the output signal of the multiplexer unit, and the output signal of the trigger unit is equal to the state signal s.

10. The FPGA logic synthesis optimization method based on finite state machine according to claim 1, characterized in that: After deleting the D flip-flop from the circuit netlist, traverse each logic unit c in the circuit netlist again. If the operation type of the logic unit c is an equal comparison operation or a logical negation type, and the input A-end signal of the logic unit c is the same as the state signal s in the state signal set, then establish a connection from the output Y-end signal of the logic unit c to the state signal s in the circuit netlist.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the FPGA logic synthesis optimization method based on a finite state machine as described in any one of claims 1 to 10.

12. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the finite state machine-based FPGA logic synthesis optimization method as described in any one of claims 1 to claim 10.

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