Time sequence optimization control method and device based on FPGA device movement
By screening and merging FPGA devices, and moving control is performed based on the single-unit device timing optimization algorithm, the problem of low FPGA layout efficiency caused by device movement is solved, synchronous timing optimization of multiple devices is achieved, and layout efficiency is improved.
Patent Information
- Application Number
- CN202411023770.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-29
- Publication Date
- 2024-12-20
AI Technical Summary
The problem of low layout efficiency in device movement in existing FPGA layouts, and existing timing optimization methods can easily lead to low FPGA layout efficiency.
By obtaining the position information and Slack timing values of the FPGA device to be moved, filtering the target device with a distance of grid spacing, combining it into a camouflage device, and moving control of the camouflage device based on a single-unit device timing optimization algorithm, realizing synchronization of multiple devices Move and timing optimization.
The layout efficiency of FPGA is improved, and the layout efficiency is improved through synchronous movement and timing optimization of multiple devices.
Smart Images
Figure CN119167854A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of FPGA design technology, and in particular to a timing optimization control method and device based on FPGA device movement. Background Art
[0002] Field Programmable Gate Array (FPGA) application design is divided into front-end logic design and optimization and back-end layout and routing. In the layout stage, the position of the logic device is optimized according to the estimated timing. After the timing reaches the expected target, the layout is completed and the routing stage begins. Routing is to connect the logical connection relationship with physical lines. In the routing stage, the device position is usually not adjusted to avoid destroying the optimized timing results.
[0003] During the FPGA layout phase, the commonly used timing optimization method is to move the device position and copy some devices and reposition them. From the perspective of convergence, moving a device will re-estimate the timing. If the estimated timing result does not improve the timing, the previous move will be rolled back and a new move method will be found. Therefore, the existing device movement method is prone to low FPGA layout efficiency.
[0004] Therefore, a timing optimization control strategy is urgently needed to solve the problem of low FPGA layout efficiency caused by the movement of a single device. Summary of the invention
[0005] The embodiment of the present invention provides a timing optimization control method and device based on FPGA device movement to solve the problem of low FPGA layout efficiency caused by the movement of a single device.
[0006] In order to solve the above problem, an embodiment of the present invention provides a timing optimization control method based on FPGA device movement, comprising:
[0007] Obtain location information and Slack timing values of several FPGA devices to be moved;
[0008] According to the position information, a target FPGA device is selected from the plurality of FPGA devices to be moved; wherein the distance between each of the target FPGA devices is a grid spacing;
[0009] Filter the target FPGA device whose Slack timing value is less than the timing stress threshold to obtain the synchronous mobile device;
[0010] Each of the synchronous moving devices is combined into a camouflage device, and the movement of the camouflage device is controlled based on a single device timing optimization algorithm.
[0011] As an improvement of the above solution, the step of merging each of the synchronous mobile devices into a camouflage device includes:
[0012] Using the unconnected input ports in each of the synchronous movement devices as a combined input port;
[0013] Using the output ports that are not connected to each other in each of the synchronous movement devices as a combined output port;
[0014] Arranging each of the synchronous moving devices at a positional relationship with a distance equal to a grid spacing to obtain an internal arrangement relationship;
[0015] Based on the merged input port, the merged output port and the internal arrangement relationship, each of the synchronous mobile devices is merged into a camouflage device.
[0016] As an improvement of the above solution, the mobile control of the camouflage device based on the single device timing optimization algorithm includes:
[0017] Calculating the target position of the camouflage device based on a single device timing optimization algorithm;
[0018] Based on the physical property limitation of PFGA, determining whether the target position exists;
[0019] If yes, the camouflage device is moved to the target position, and the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA;
[0020] If not, the connection of the camouflage device is removed, and the FPGA device to be moved in the camouflage device is not moved.
[0021] As an improvement of the above solution, after the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA, the method further includes:
[0022] Performing timing calculation on each to-be-moved FPGA device in the camouflage device connected to the target position of the FPGA;
[0023] When the timing is greater than or equal to the timing threshold, no action is taken;
[0024] When the timing is less than the timing threshold, the position of the current FPGA device to be moved is calculated based on the single device timing optimization algorithm and the device is moved based on the calculated position information.
[0025] As an improvement of the above solution, the determination of the FPGA device to be moved includes:
[0026] Perform timing calculations for each FPGA device;
[0027] An FPGA device whose timing is less than a timing threshold is selected as the FPGA device to be moved.
[0028] Accordingly, an embodiment of the present invention further provides a timing optimization control device based on FPGA device movement, comprising: a data acquisition module, a first screening module, a second screening module and a data control module;
[0029] The data acquisition module is used to obtain the location information and Slack timing values of several FPGA devices to be moved;
[0030] The first screening module is used to select a target FPGA device from the plurality of FPGA devices to be moved according to the position information; wherein the distance between each of the target FPGA devices is a grid spacing;
[0031] The second screening module is used to screen the target FPGA device whose Slack timing value is less than the timing stress threshold to obtain the synchronous mobile device;
[0032] The data control module is used to merge each of the synchronous mobile devices into a camouflage device, and perform movement control on the camouflage device based on a single device timing optimization algorithm.
[0033] As an improvement of the above solution, the step of merging each of the synchronous mobile devices into a camouflage device includes:
[0034] Using the unconnected input ports in each of the synchronous movement devices as a combined input port;
[0035] Using the output ports that are not connected to each other in each of the synchronous movement devices as a combined output port;
[0036] Arranging each of the synchronous moving devices at a positional relationship with a distance equal to a grid spacing to obtain an internal arrangement relationship;
[0037] Based on the merged input port, the merged output port and the internal arrangement relationship, each of the synchronous mobile devices is merged into a camouflage device.
[0038] As an improvement of the above solution, the mobile control of the camouflage device based on the single device timing optimization algorithm includes:
[0039] Calculating the target position of the camouflage device based on a single device timing optimization algorithm;
[0040] Based on the physical property limitation of PFGA, determining whether the target position exists;
[0041] If yes, the camouflage device is moved to the target position, and the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA;
[0042] If not, the connection of the camouflage device is removed, and the FPGA device to be moved in the camouflage device is not moved.
[0043] As an improvement of the above solution, after the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA, the method further includes:
[0044] Performing timing calculation on each to-be-moved FPGA device in the camouflage device connected to the target position of the FPGA;
[0045] When the timing is greater than or equal to the timing threshold, no action is taken;
[0046] When the timing is less than the timing threshold, the position of the current FPGA device to be moved is calculated based on the single device timing optimization algorithm and the device is moved based on the calculated position information.
[0047] As an improvement of the above solution, the determination of the FPGA device to be moved includes:
[0048] Perform timing calculations for each FPGA device;
[0049] An FPGA device whose timing is less than a timing threshold is selected as the FPGA device to be moved.
[0050] As can be seen from the above, the present invention has the following beneficial effects:
[0051] The present invention provides a timing optimization control method based on the movement of FPGA devices, which obtains the position information and Slack timing values of several FPGA devices to be moved; selects a target FPGA device from several FPGA devices to be moved according to the position information; wherein the distance between each target FPGA device is a grid spacing; screens the target FPGA devices whose Slack timing values are greater than the timing tension threshold to obtain synchronous moving devices; merges each synchronous moving device into a camouflage device, and performs movement control on the camouflage device based on a single device timing optimization algorithm. The present invention screens FPGA devices based on position information and Slack timing values, merges FPGA devices whose distance is the grid spacing and whose Slack timing values are greater than the timing tension threshold into camouflage devices, and applies the single device timing optimization algorithm to all FPGA devices in the camouflage device in a single device manner, thereby realizing the synchronous movement of multiple FPGA devices, and then realizing the synchronous timing optimization of multiple FPGA devices, thereby improving the layout efficiency of FPGA. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] Figure 1 It is a flow chart of a timing optimization control method based on FPGA device movement provided by an embodiment of the present invention;
[0053] Figure 2 It is a structural schematic diagram of a timing optimization control device based on FPGA device movement provided by an embodiment of the present invention;
[0054] Figure 3 is a schematic diagram of camouflage devices combined according to an embodiment of the present invention;
[0055] Figure 4 This is a schematic diagram of the structure of a terminal device provided by an embodiment of the present invention;
[0056] Figure 5 It is a schematic diagram of obtaining a synchronous mobile device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0058] Embodiment 1
[0059] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a timing optimization control method based on FPGA device movement provided by an embodiment of the present invention. Figure 1 As shown, this embodiment includes steps 101 to 104, and each step is specifically as follows:
[0060] Step 101: Obtain location information and Slack timing values of several FPGA devices to be moved.
[0061] In this embodiment, the determination of the FPGA device to be moved includes:
[0062] Perform timing calculations for each FPGA device;
[0063] An FPGA device whose timing is less than a timing threshold is selected as the FPGA device to be moved.
[0064] Step 102: Select a target FPGA device from the plurality of FPGA devices to be moved according to the position information; wherein the distance between each of the target FPGA devices is a grid spacing.
[0065] In this embodiment, the FPGA chip is arranged in a grid, and when the distance is the grid spacing, it can be limited to adjacent grids, so that there is no space for a single device to move.
[0066] Step 103: Filter the target FPGA devices whose Slack timing values are less than the timing stress threshold to obtain synchronous mobile devices.
[0067] In this embodiment, the timing stress threshold may be 0, and may also be adaptively adjusted according to the user's application requirements for different FPGAs. When slack is less than this value, the timing is considered to be tight, otherwise, the timing is considered not tight.
[0068] For better explanation, the following example is provided. Figure 5 , R3 is the end point of a timing path, and its negative timing is not ideal. To improve it, it needs to move forward, but it will be blocked by devices such as L3 in front, so it is necessary to bind multiple devices together and move them together. Considering the distance, L1, L2, L3, and L5 are close to R3 and can be bound. Considering the timing, the critical path is R2=>L4=>L2=>L3=>R3, and its slack is -100ps. R1=>L1=>L3=>R3 is another path to R3, and the timing is 800ps. When selecting, L5 has nothing to do with R3 timing and does not need to be bound; although L1 is timing-related, its timing is loose and has a margin of 800ps. Even if the movement causes a slight decrease in slack, it is acceptable and does not need to be moved together. In this example, the final bound devices selected are L2, L3, and R3.
[0069] Step 104: Merge each of the synchronous moving devices into a camouflage device, and control the movement of the camouflage device based on a single device timing optimization algorithm.
[0070] In this embodiment, the step of combining each of the synchronous mobile devices into a camouflage device includes:
[0071] Using the unconnected input ports in each of the synchronous movement devices as a combined input port;
[0072] Using the output ports that are not connected to each other in each of the synchronous movement devices as a combined output port;
[0073] Arranging each of the synchronous moving devices at a positional relationship with a distance equal to a grid spacing to obtain an internal arrangement relationship;
[0074] Based on the merged input port, the merged output port and the internal arrangement relationship, each of the synchronous mobile devices is merged into a camouflage device.
[0075] For a better explanation, see Figure 3, Figure 3 This is an example of the present invention in which a synchronous mobile device is combined into a camouflage device, such as Figure 3 As shown, the input ports (D, A, B, D) that are not connected to each other are used as combined input ports (I1, I2, I3, I4), and the connection relationship of the ports that are connected to each other is used as the internal connection of the camouflage device and is not set to the outside, such as Q and C; the output port O that is not connected to each other is used as a combined output port (Z), and the internal arrangement relationship of the two devices R1 and L1 inside the camouflage device is not adjacent to the grid, that is, the distance is the grid spacing.
[0076] In this embodiment, the mobile control of the camouflage device based on the single device timing optimization algorithm includes:
[0077] Calculating the target position of the camouflage device based on a single device timing optimization algorithm;
[0078] Based on the physical property limitation of PFGA, determining whether the target position exists;
[0079] If yes, the camouflage device is moved to the target position, and the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA;
[0080] If not, the connection of the camouflage device is removed, and the FPGA device to be moved in the camouflage device is not moved.
[0081] In a specific embodiment, the camouflage device is composed of a plurality of real devices bundled together, and the parameters of the camouflage device will record these original devices. After finding the target location, the original devices are placed one by one in the corresponding physical units of the target location area.
[0082] In this embodiment, after the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA, the method further includes:
[0083] Performing timing calculation on each to-be-moved FPGA device in the camouflage device connected to the target position of the FPGA;
[0084] When the timing is greater than or equal to the timing threshold, no action is taken;
[0085] When the timing is less than the timing threshold, the position of the current FPGA device to be moved is calculated based on the single device timing optimization algorithm and the device is moved based on the calculated position information.
[0086] In a specific embodiment, the timing threshold may be set by a user.
[0087] In a specific embodiment, considering that the devices with tight timing may move in different directions, the timing of the moved devices is calculated again after the movement; if this situation exists, a multi-device clustering situation will usually not be formed.
[0088] See also Figure 2 , Figure 2 It is a structural schematic diagram of a timing optimization control device based on FPGA device movement provided by an embodiment of the present invention, comprising: a data acquisition module 201, a first screening module 202, a second screening module 203 and a data control module 204;
[0089] The data acquisition module is used to obtain the location information and Slack timing values of several FPGA devices to be moved;
[0090] The first screening module is used to select a target FPGA device from the plurality of FPGA devices to be moved according to the position information; wherein the distance between each of the target FPGA devices is a grid spacing;
[0091] The second screening module is used to screen the target FPGA device whose Slack timing value is greater than the timing stress threshold to obtain the synchronous mobile device;
[0092] The data control module is used to merge each of the synchronous mobile devices into a camouflage device, and perform movement control on the camouflage device based on a single device timing optimization algorithm.
[0093] As an improvement of the above solution, the step of merging each of the synchronous mobile devices into a camouflage device includes:
[0094] Using the unconnected input ports in each of the synchronous movement devices as a combined input port;
[0095] Using the output ports that are not connected to each other in each of the synchronous movement devices as a combined output port;
[0096] Arranging each of the synchronous moving devices at a positional relationship with a distance equal to a grid spacing to obtain an internal arrangement relationship;
[0097] Based on the merged input port, the merged output port and the internal arrangement relationship, each of the synchronous mobile devices is merged into a camouflage device.
[0098] As an improvement of the above solution, the mobile control of the camouflage device based on the single device timing optimization algorithm includes:
[0099] Calculating the target position of the camouflage device based on a single device timing optimization algorithm;
[0100] Based on the physical property limitation of PFGA, determining whether the target position exists;
[0101] If yes, the camouflage device is moved to the target position, and the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA;
[0102] If not, the connection of the camouflage device is removed, and the FPGA device to be moved in the camouflage device is not moved.
[0103] As an improvement of the above solution, after the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA, the method further includes:
[0104] Performing timing calculation on each to-be-moved FPGA device in the camouflage device connected to the target position of the FPGA;
[0105] When the timing is greater than or equal to the timing threshold, the position of the current FPGA device to be moved is calculated based on the single device timing optimization algorithm and the device is moved based on the calculated position information;
[0106] When the timing is less than the timing threshold, no action is taken.
[0107] As an improvement of the above solution, the determination of the FPGA device to be moved includes:
[0108] Perform timing calculations for each FPGA device;
[0109] An FPGA device whose timing is greater than or equal to the timing threshold is selected as the FPGA device to be moved.
[0110] This embodiment obtains the position information and Slack timing values of several FPGA devices to be moved; selects a target FPGA device from the several FPGA devices to be moved according to the position information; wherein the distance between each target FPGA device is the grid spacing; screens the target FPGA devices whose Slack timing values are greater than the timing tension threshold to obtain synchronous moving devices; merges each synchronous moving device into a camouflage device, and controls the movement of the camouflage device based on the single device timing optimization algorithm. The present invention screens FPGA devices based on position information and Slack timing values, merges FPGA devices whose distance is the grid spacing and whose Slack timing values are greater than the timing tension threshold into camouflage devices, and applies the single device timing optimization algorithm to all FPGA devices in the camouflage device in the form of a single device, thereby realizing the synchronous movement of multiple FPGA devices, and then realizing the synchronous timing optimization of multiple FPGA devices, thereby improving the layout efficiency of FPGA.
[0111] Embodiment 2
[0112] See also Figure 4 , Figure 4 It is a schematic diagram of the structure of a terminal device provided in one embodiment of the present invention.
[0113] A terminal device of this embodiment includes: a processor 401, a memory 402, and a computer program stored in the memory 402 and executable on the processor 401. When the processor 401 executes the computer program, the steps of the above-mentioned timing optimization control method based on FPGA device movement in the embodiment are implemented, for example Figure 1 All steps of the timing optimization control method based on FPGA device movement shown. Alternatively, when the processor executes the computer program, the functions of each module in the above-mentioned device embodiments are realized, for example: Figure 2 The FPGA-based device shown moves all modules of the timing optimization control device.
[0114] In addition, an embodiment of the present invention also provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the timing optimization control method based on FPGA device movement as described in any of the above embodiments.
[0115] Those skilled in the art will understand that the schematic diagram is merely an example of a terminal device and does not constitute a limitation on the terminal device. The terminal device may include more or fewer components than shown in the diagram, or a combination of certain components, or different components. For example, the terminal device may also include input and output devices, network access devices, buses, etc.
[0116] The processor 401 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor 401 is the control center of the terminal device, and uses various interfaces and lines to connect various parts of the entire terminal device.
[0117] The memory 402 can be used to store the computer program and / or module, and the processor 401 realizes various functions of the terminal device by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory 402. The memory 402 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.
[0118] Wherein, if the module / unit integrated in the terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc.
[0119] It should be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the accompanying drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art may understand and implement it without paying any creative effort.
[0120] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A timing optimization control method based on FPGA device movement, characterized in that: include: Obtain location information and Slack timing values of several FPGA devices to be moved; According to the position information, a target FPGA device is selected from the plurality of FPGA devices to be moved; wherein the distance between each of the target FPGA devices is a grid spacing; Filter the target FPGA device whose Slack timing value is less than the timing stress threshold to obtain the synchronous mobile device; Each of the synchronous moving devices is combined into a camouflage device, and the movement of the camouflage device is controlled based on a single device timing optimization algorithm.
2. The timing optimization control method based on FPGA device movement according to claim 1 is characterized in that: The step of combining each of the synchronous mobile devices into a camouflage device comprises: Using the unconnected input ports in each of the synchronous movement devices as a combined input port; Using the output ports that are not connected to each other in each of the synchronous movement devices as a combined output port; Arranging each of the synchronous moving devices at a positional relationship with a distance equal to a grid spacing to obtain an internal arrangement relationship; Based on the merged input port, the merged output port and the internal arrangement relationship, each of the synchronous mobile devices is merged into a camouflage device.
3. The timing optimization control method based on FPGA device movement according to claim 2 is characterized in that: The controlling the movement of the camouflage device based on the single device timing optimization algorithm includes: Calculating the target position of the camouflage device based on a single device timing optimization algorithm; Based on the physical property limitation of PFGA, determining whether the target position exists; If yes, the camouflage device is moved to the target position, and the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA; If not, the connection of the camouflage device is removed, and the FPGA device to be moved in the camouflage device is not moved.
4. The timing optimization control method based on FPGA device movement according to claim 3 is characterized in that: After the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA, the method further includes: Performing timing calculation on each to-be-moved FPGA device in the camouflage device connected to the target position of the FPGA; When the timing is greater than or equal to the timing threshold, no action is taken; When the timing is less than the timing threshold, the position of the current FPGA device to be moved is calculated based on the single device timing optimization algorithm and the device is moved based on the calculated position information.
5. The timing optimization control method based on FPGA device movement according to any one of claims 1 to 4, characterized in that: The determination of the FPGA device to be moved includes: Perform timing calculations for each FPGA device; An FPGA device whose timing is less than a timing threshold is selected as the FPGA device to be moved.
6. A timing optimization control device based on FPGA device movement, characterized in that: include: A data acquisition module, a first screening module, a second screening module and a data control module; The data acquisition module is used to obtain the location information and Slack timing values of several FPGA devices to be moved; The first screening module is used to select a target FPGA device from the plurality of FPGA devices to be moved according to the position information; wherein the distance between each of the target FPGA devices is a grid spacing; The second screening module is used to screen the target FPGA device whose Slack timing value is less than the timing stress threshold to obtain the synchronous mobile device; The data control module is used to merge each of the synchronous mobile devices into a camouflage device, and perform movement control on the camouflage device based on a single device timing optimization algorithm.
7. The timing optimization control device based on FPGA device movement according to claim 6, characterized in that: The step of combining each of the synchronous mobile devices into a camouflage device comprises: Using the unconnected input ports in each of the synchronous movement devices as a combined input port; Using the output ports that are not connected to each other in each of the synchronous movement devices as a combined output port; Arranging each of the synchronous moving devices at a positional relationship with a distance equal to a grid spacing to obtain an internal arrangement relationship; Based on the merged input port, the merged output port and the internal arrangement relationship, each of the synchronous mobile devices is merged into a camouflage device.
8. The timing optimization control device based on FPGA device movement according to claim 7, characterized in that: The controlling the movement of the camouflage device based on the single device timing optimization algorithm includes: Calculating the target position of the camouflage device based on a single device timing optimization algorithm; Based on the physical property limitation of PFGA, determining whether the target position exists; If yes, the camouflage device is moved to the target position, and the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA; If not, the connection of the camouflage device is removed, and the FPGA device to be moved in the camouflage device is not moved.
9. The timing optimization control device based on FPGA device movement according to claim 8, characterized in that: After the FPGA device to be moved in the camouflage device is connected to the target position of the FPGA, the method further includes: Performing timing calculation on each to-be-moved FPGA device in the camouflage device connected to the target position of the FPGA; When the timing is greater than or equal to the timing threshold, no action is taken; When the timing is less than the timing threshold, the position of the current FPGA device to be moved is calculated based on the single device timing optimization algorithm and the device is moved based on the calculated position information.
10. The timing optimization control device based on FPGA device movement according to any one of claims 6 to 9, characterized in that: The determination of the FPGA device to be moved includes: Perform timing calculations for each FPGA device; An FPGA device whose timing is less than a timing threshold is selected as the FPGA device to be moved.