Asymmetric pad structure and test element group module

Abstract

The invention provides an asymmetric pad structure and a test element group module, which are used on a cutting channel of a wafer and comprise a test element device which is electrically connected with a first pad and a second pad respectively. Wherein a first distance between the second connecting pad and the test element device is enough to accommodate a second connecting pad of another asymmetric connecting pad structure, two adjacent asymmetric connecting pad structures can be mutually crossed to form a crossed structure, and through the asymmetric connecting pad structures and the test element group module, cutting channels can be shrunk, and meanwhile, the cutting efficiency of the test element group module can be improved. Increasing the number of test element group modules in the cutting channel; and the measurement technical conditions under the chip miniaturization trend are met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an asymmetric pad structure and a test element group module. Background Art

[0002] Over the years, there have been many major breakthroughs in the development of nanoscale process flows in semiconductor technology. Figure 1 The current technology trend is to reduce the size of the chip and the width of the scribe line (S / L) to obtain more effective dies on the wafer 1, where the scribe line defines the frame limit 400 of the die on the wafer 1. The development of nanometer-scale process technology aims to achieve higher integrated circuit density and performance to meet the needs of modern electronic products for smaller, faster and more energy-efficient devices.

[0003] In the semiconductor process flow, it is necessary to continuously monitor the process flow at each stage to maintain and ensure the quality of the components. Specifically, it is necessary to align the probe card with the test element group (TEG) / pad PAD (hereinafter referred to as TEG / PAD) configuration on wafer 1. This usually involves positioning the probe card so that the test probes on it are aligned with the pads of the TEG / PAD configuration on wafer 1. Once the probe card is aligned, the test probes on the probe card can contact the pads. These test probes are usually small and flexible metal needles that can provide electrical or test signal connections when in contact with the pads. Once the test probes on the probe card contact the pads, the test system transmits test signals to the test element group TEG on wafer 1 through the probe card. These signals may involve voltage, current, timing or other specific test conditions to test components on wafer 1. The test system monitors and records the test results obtained from the test element group TEG. These results may reflect the electrical characteristics of the components, functional operation conditions, and other relevant test data.

[0004] Please refer to Figure 2, the traditional test element group module is usually set in the area between the two crack-blocking lines, and the area of ​​the area is smaller than the area of ​​the cutting path S / L for cutting the wafer 1. The test element group module is composed of a plurality of symmetrical TEG / PAD configurations, each TEG / PAD is composed of two pads (PAD1 and PAD2) and a test element T configuration. The two pads (PAD1 and PAD2) are electrically connected to the left and right ends of the test element T, respectively, as input and output connections. There is a pitch PITCH0 between the pads (PAD1 and PAD2), and the pitch corresponds to the spacing between every two adjacent test probes on the probe card, which is used to align the pads and the test probes. With the development of nano-sized process flow, the chip size and the width of the cutting path S / L on new products are gradually reduced to obtain more effective wafers 1 on the wafer 1, so the quality requirements for process flow monitoring are getting higher and higher, and more areas are also needed to accommodate more test element groups TEG, so that only narrowing the cutting path cannot meet the current needs.

[0005] Currently, there is a need to provide a test structure that allows more test element groups TEG to occupy the area within the scribe line when the scribe line is narrowed, thereby increasing the number of tests on the test element group module. Summary of the invention

[0006] The purpose of the present invention is to provide an asymmetric pad structure and a test element group module, which solves the problem in the field of semiconductor technology that when the cutting path is narrowed, more test element groups TEGs need to be allowed to occupy the area within the cutting path, thereby obtaining more test quantities of the test element group module.

[0007] The above-mentioned implementation objectives of the present invention are mainly achieved by the following technical solutions:

[0008] The present invention provides an asymmetric pad structure for use on a cutting path of a wafer. The asymmetric pad structure includes: a test element device, which is electrically connected to a first pad and a second pad respectively. A first spacing between the second pad and the test element device is sufficient to accommodate a second pad of another asymmetric pad structure, and the other asymmetric pad structure has the same structure as the asymmetric pad structure.

[0009] In one embodiment of the present invention, the first distance is greater than a second distance between the first pad and the test device.

[0010] In one embodiment of the present invention, the asymmetric pad structure and the other asymmetric pad structure are arranged crosswise.

[0011] In one embodiment of the present invention, a pitch between the first pad and the second pad of the asymmetric pad structure is the same as a pitch of the other asymmetric pad structure.

[0012] In one embodiment of the present invention, the pitch is defined by a distance between a center line of the first pad and a center line of the second pad.

[0013] In one embodiment of the present invention, the testing element device is located between the first pad and the second pad.

[0014] The present invention further provides a test element group module for use on a cutting path of a wafer, the test element group module comprising: a plurality of asymmetric pad structures, the plurality of asymmetric pad structures are arranged in pairs with each other, and the two paired asymmetric pad structures are arranged crosswise with each other, each of the asymmetric pad structures has: a test element device, electrically connected to a first pad and a second pad respectively and the test element device is located between the two, a first spacing between the test element device and one of the first pad or the second pad is sufficient to accommodate one of the first pad or the second pad, and a second spacing between the test element device and the other of the first pad or the second pad is smaller than the first spacing.

[0015] In one embodiment of the present invention, the plurality of asymmetric pad structures have a same pitch, and the pitch is defined by a distance between a center line of the first pad and a center line of the second pad.

[0016] In one embodiment of the present invention, the test element group modules are arranged in a linear array between the crack-resistance lines within the scribe line.

[0017] In one embodiment of the present invention, the first pad and the second pad have the same size.

[0018] Compared with the prior art, the technical solution of the present invention has the following characteristics and advantages:

[0019] Through an asymmetric pad structure and a test element group module composed of multiple asymmetric pad structures, more test element group modules can be arranged in a reduced cutting path, so that the test structure used for monitoring can adapt to a smaller chip size, solving the problem of a lack of suitable test tools for existing chip sizes. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The features and advantages of the above-described example embodiments and other features and advantages will become more apparent after considering some example embodiments illustrated in the accompanying drawings of the present invention. The drawings of the present invention are not necessarily drawn to scale, but emphasize certain features and principles of the example embodiments. In the drawings and description, the same reference numbers and designations are used to represent similar elements and features. In the drawings:

[0021] Figure 1 The test device assembly module of the prior art shows a top view of a wafer with chips and dicing lanes and a partial enlarged view thereof.

[0022] Figure 2 for Figure 1 A partial enlarged view of a conventional test element group module used in portion B of the cutting lane in FIG.

[0023] Figure 3 FIG. 1 is a schematic diagram of a cross structure formed by a pair of asymmetric pad structures in one embodiment of the asymmetric pad structure and the test element assembly module of the present invention.

[0024] Figure 4 FIG. 1 is a simplified diagram of a test device group module located in a scribe line in one embodiment of the asymmetric pad structure and the test device group module of the present invention.

[0025] Description of Figure Numbers:

[0026] 1. Wafer;

[0027] 100, first asymmetric pad structure; 110, first pad; 120, second pad; 130, test element device;

[0028] 200, second asymmetric pad structure; 210, first pad; 220, second pad; 230, test element device;

[0029] 300, test element group module;

[0030] 400, frame limit;

[0031] 500, cutting path;

[0032] 600, crack resistance line;

[0033] PAD1, pad; PAD2, pad;

[0034] PITCH0, pitch; PITCH1, first pitch; PITCH2, second pitch;

[0035] S / L, cutting path;

[0036] T, test element;

[0037] W1, first spacing; W2, second spacing. DETAILED DESCRIPTION

[0038] Next, an example embodiment of the present invention will be described in detail and illustrated with reference to the accompanying drawings. The purpose of the example embodiment is to make the content of the present invention comprehensive and complete, and to be fully conveyed to those skilled in the art. Since the invention may have various different modified embodiments, multiple embodiments are described in detail in the specification and the drawings to embody the invention. However, this does not limit the present invention to a specific embodiment, and it should be understood that the present invention covers all modifications, equivalent substitutions and replacement embodiments, the scope of which includes the ideas and technical scope of the present invention. In all drawings, the same reference numbers and designations may be used to indicate similar elements and features, and in the drawings, for ease of description, the size and size of each structure may be enlarged or reduced and drawn in the form of a schematic diagram.

[0039] Herein, technical terms such as "first" or "second" may be used to describe various elements, but these elements should not be limited to these technical terms. These technical terms can only be used to distinguish one element from another element.

[0040] It should be understood that although the technical terms such as "first", "second" or "third" are used herein to describe various elements, components, regions and / or parts, these elements, components, regions and / or parts should not be limited by these technical terms. These technical terms are only used to distinguish one element, component, region or part from another element, component, region or part. Therefore, the first element, component, region or part discussed below can be referred to as a second element, component, region or part without departing from the teachings of the example embodiments.

[0041] Please refer to Figure 3, which shows a schematic diagram of a cross structure configured by a pair of asymmetric pad structures according to an embodiment of the present invention. The cross structure includes a first asymmetric pad structure 100 and a second asymmetric pad structure 200 that cross each other. The first asymmetric pad structure 100 has a first pad 110 as an input pad, a second pad 120 as an output pad, and a test element device 130 (test element device), and the test element device 130 is used to test whether the semiconductor element on the wafer 1 is working normally. The test element device 130 is located between the first pad 110 and the second pad 120, and is electrically connected to the first pad 110 and the second pad 120 respectively. There is a first spacing W1 between the second pad 120 and the test element device 130, and there is a second spacing W2 between the first pad 110 and the test element device 130. The distance between the center line of the first pad 110 and the center line of the second pad 120 defines a first pitch PITCH1. Similarly, the second asymmetric pad structure 200 has the same configuration as the first asymmetric pad structure 100, that is, it has a first pad 210, a second pad 220 and a test element device 230. The first pitch PITCH1 between the first pad 110 and the second pad 120 of the first asymmetric pad structure 100 is the same as the second pitch PITCH2 between the first pad 210 and the second pad 220 of the second asymmetric pad structure 200. Therefore, the test probes on the probe card are evenly distributed on the first asymmetric pad structure 100 and the second asymmetric pad structure 200, and the first pad 110, the first pad 210 and the second pad 120, the second pad 220 are aligned with the corresponding test control pins. The technical term "pitch" is usually expressed in distance units such as millimeters or microns, and is determined according to test requirements and process flow technology. A smaller pitch means that the spacing between the first pad 110 and the second pad 120 is smaller, so as to provide higher test coverage and more detailed test capabilities. The specific value of the pitch will vary depending on factors such as the density of components on the wafer 1, test requirements, and limitations of the test equipment. During the design process of the wafer acceptance test (WAT), the test engineer or designer considers these factors to determine the appropriate pitch to achieve the test goals and requirements.

[0042] As shown in the first asymmetric pad structure 100, the first spacing W1 is greater than the second spacing W2 to form an asymmetric structure, so that the first spacing W1 between the second pad 120 and the test element device 130 is sufficient to accommodate the second pad 220 of the second asymmetric pad structure 200. With this structure, the first asymmetric pad structure 100 can be arranged to intersect with the second asymmetric pad structure 200, thereby achieving a compact and dense arrangement in the same area within the dicing street.

[0043] Please refer to Figure 3 and Figure 4 The present invention discloses a plurality of asymmetric pad structures that are paired in pairs, and a cross arrangement in which two asymmetric pad structures in each pair cross each other, for example Figure 3 The first asymmetric pad structure 100 and the second asymmetric pad structure 200 in the wafer 1 are provided. The first asymmetric pad structure 100 and the second asymmetric pad structure 200 can be arranged in a linear array or rows and columns along each cutting road 500 to form a test element group module 300. Specifically, the test element group module 300 is usually arranged between adjacent crack resistance lines 600 located in the cutting road 500. This layout isolates the test element group module 300 from other process flow areas (such as chip boundaries) to minimize interference and interference with the test element group module 300. In addition, the presence of the crack resistance line 600 helps to protect the integrity of the wafer 1 to prevent damage or cracking during the dicing process of cutting the wafer 1 into chips. In the present invention, the test element group module 300 is designed by a design engineer during the design stage of the wafer 1 according to the test requirements, goals, and the layout and structure of the components on the wafer 1. This includes designing the position, quantity, spacing, and interconnection relationship of the test element group, for example Figure 3 and Figure 4 The test element device 130, the test element device 230, etc.

[0044] Compared to Figure 2 Compared with the conventional symmetrical pad structure shown, the first asymmetrical pad structure 100 and the second asymmetrical pad structure 200 can accommodate more asymmetrical pad structures when the dicing road 500 is narrowed. Moreover, each pair of crossed asymmetrical pad structures can be arranged compactly with another pair of crossed asymmetrical pad structures, so that the number of asymmetrical pad structures is increased within the limited space of the dicing road 500 of the wafer 1, thereby improving the test efficiency and the production capacity of semiconductor components on the wafer 1. In addition, the pitch of the test component group module 300 of the present invention can be Figure 2The pitch of the conventional symmetrical pad structure shown is the same to maintain the pitch of the conventional wafer 1 under test (WAT) pads, so that the conventional probe card can still be applied to the test element group module 300. The high-density configuration and optimized design of the test element group module 300 help improve quality control, improve product reliability and increase manufacturing efficiency. Therefore, the asymmetrical pad structure and test element group module of the present invention provide new possibilities for the semiconductor industry, enabling manufacturers to have advanced testing capabilities and provide supporting technical support for chip technology advancement in this field.

[0045] The above embodiments are only examples and do not limit the scope of the present invention. Various changes or modifications can be made without departing from the spirit of the present invention and achieving the same effect, and these changes or modifications should fall within the scope of patent protection of this patent.

Claims

1. An asymmetric pad structure, It is characterized in that The device is arranged on a dicing path of a wafer, comprising: A test element device is electrically connected to a first pad and a second pad respectively; A first distance between the second pad and the testing element device is sufficient to accommodate a second pad of another asymmetric pad structure, and the another asymmetric pad structure has the same structure as the asymmetric pad structure.

2. The asymmetric pad structure according to claim 1, It is characterized in that The first distance is greater than a second distance between the first pad and the test element device.

3. The asymmetric pad structure according to claim 1, It is characterized in that The asymmetric pad structure is arranged crosswise with another asymmetric pad structure.

4. The asymmetric pad structure according to claim 1, It is characterized in that A pitch between the first pad and the second pad of the asymmetric pad structure is the same as the pitch of another asymmetric pad structure.

5. The asymmetric pad structure according to claim 4, It is characterized in that The pitch is defined by a distance between a centerline of the first pad and a centerline of the second pad.

6. The asymmetric pad structure according to claim 1, It is characterized in that The test element device is located between the first pad and the second pad.

7. A test element group module, It is characterized in that The device is arranged on a dicing path of a wafer, comprising: A plurality of asymmetric pad structures, wherein the plurality of asymmetric pad structures are arranged in pairs, and the two paired asymmetric pad structures are arranged crosswise with each other, and each of the asymmetric pad structures has: A test element device is electrically connected to a first pad and a second pad respectively, and the test element device is located between the two; A first distance between the test element device and one of the first pad or the second pad is sufficient to accommodate one of the first pad or the second pad, and a second distance between the test element device and the other of the first pad or the second pad is smaller than the first distance.

8. The test element group module according to claim 7, It is characterized in that The asymmetric pad structures have a same pitch, wherein the pitch is defined by a distance between a center line of the first pad and a center line of the second pad.

9. The test element group module according to claim 7, It is characterized in that The test element group modules are arranged in a linear array between crack-resistance lines within the scribe line.

10. The test element group module according to claim 7, It is characterized in that The first pad and the second pad have a same size.

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