Multi-threshold voltage modulated wide bandgap semiconductor device structure and manufacturing method thereof

Abstract

The invention provides a multi-threshold voltage modulated wide bandgap semiconductor device structure and a manufacturing method thereof. A grid electrode of the device structure is arranged in a middle region of an N + current expansion layer in a penetrating manner along a first direction; the P + masking layer is arranged close to the epitaxial layer and extends to the edge of the first side from the middle area of the N + current expansion layer in the second direction through ion implantation; the second P-well region and the second source N + region are positioned between the grid electrode and the P + masking layer; the second source P + region is arranged on the P + masking layer and is in contact with the edges of the second source N + region and the grid along one side in the second direction; the second source N + region, the second P-well region and the N + current expansion layer form a new current path; the first source P + region is located at the edge of the second side of the N + current expansion layer; and a first P-well region and a first source N + region are superposed between the first source P + region and the grid. The device structure can modulate the device to have low on-resistance at a high temperature, has a better conduction characteristic, and meets more application scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a multi-threshold voltage modulated wide bandgap semiconductor device structure and a manufacturing method thereof. Background Art

[0002] In recent years, silicon carbide SiC and gallium nitride GaN, as third-generation semiconductor materials, have excellent material properties and are more advantageous than traditional Si materials in physical properties such as bandgap width, critical breakdown electric field strength, and electron saturation drift velocity. The power devices prepared, such as diodes and transistors, have better electrical properties and can be used in high-power, high-voltage, high-frequency, and high-temperature applications that silicon-based devices cannot meet. They are also one of the breakthrough paths to surpass Moore's Law. Therefore, they are widely used in the field of new energy and have promoted the development of the "new energy revolution."

[0003] At present, in power switch applications, the Baliga figure of merit BFOM is usually used as an indicator of the applicability of semiconductor materials in power electronics, which is expressed as: BFOM = εμE 3 , where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is roughly positively correlated with the sixth power of the bandgap width Eg. Wide bandgap semiconductors have lower power loss and higher conversion efficiency in the application of power devices, and can be better applied to power electronics.

[0004] However, wide bandgap semiconductor trench MOSFET devices still have some shortcomings in design and practical application: one of the most studied problems is that wide bandgap semiconductor devices cause a very high electric field on the gate dielectric layer during the blocking process, and the device is prone to failure; the needs of the device in different temperature application scenarios also need to be paid attention to. The device channel resistance is negatively correlated with temperature. As the temperature rises, the threshold voltage decreases, and the on-resistance also decreases, but the positive temperature coefficient of other resistances in the device area (JFET area resistance, drift area resistance, etc.) will offset this effect, ultimately resulting in an on-resistance with a positive temperature coefficient at higher temperatures; currently commercially available devices have an on-resistance that is basically a negative temperature coefficient at negative temperatures, and after passing an inflection point of about 0 to 25°C, the positive temperature coefficient is maintained, which results in the device having a lower on-resistance near the inflection point; that is, the current device is more suitable for application scenarios at room temperature, but for some higher temperature application scenarios, it is necessary to design devices with better on-resistance at higher temperatures.

[0005] Therefore, the wide bandgap semiconductor device causes a very high electric field on the gate dielectric layer during the blocking process, especially at the groove corners, which causes the gate dielectric layer to quickly breakdown under high drain voltage, which becomes a problem that needs to be solved. At the same time, it is necessary to design devices with better on-resistance at higher temperatures so that the devices can meet the needs of different temperature application scenarios. In combination with the current development status of the prior art, the present invention provides a new multi-threshold voltage modulated wide bandgap semiconductor device structure and a manufacturing method thereof. Summary of the invention

[0006] Based on the above description, the present invention provides a multi-threshold voltage modulated wide bandgap semiconductor device structure and a manufacturing method thereof, which can improve the conduction characteristics of the device while making the inflection point of the overall on-resistance from a negative temperature coefficient to a positive temperature coefficient controllable, that is, the device can be modulated to have a lower on-resistance at a required higher temperature.

[0007] The technical solution of the present invention to solve the above technical problems is as follows:

[0008] In a first aspect, the present invention provides a wide bandgap semiconductor device structure with multi-threshold voltage modulation, comprising: a substrate, an epitaxial layer, an N+ current spreading layer, a first source N+ region, a second source N+ region, a first source P+ region, a second source P+ region, a first P-well region, a second P-well region, a P+ shielding layer, a gate, a source and a drain;

[0009] The epitaxial layer, the N+ current spreading layer and the source electrode are sequentially arranged on the substrate; the drain electrode is arranged at the bottom of the substrate;

[0010] The gate is arranged along the first direction through the middle area of ​​the N+ current extension layer, the P+ shielding layer is arranged close to the epitaxial layer, and is extended from the middle area of ​​the N+ current extension layer along the second direction to the edge of the first side by ion implantation; the second P-well region and the second source N+ region arranged in sequence along the second direction are located between the gate and the P+ shielding layer; the second source P+ region is arranged on the P+ shielding layer, and is in contact with the edges of the second source N+ region and the gate on one side along the second direction, and is extended to the edge of the first side of the N+ current extension layer on the other side; the second source N+ region, the second P-well region and the N+ current extension layer form a new current path; wherein the first direction and the second direction are arranged vertically;

[0011] The first source P+ region is arranged on the epitaxial layer and located at the edge of the second side of the N+ current spreading layer; the first P-well region and the first source N+ region are superimposed between the first source P+ region and the gate.

[0012] Based on the above technical solution, the present invention can also be improved as follows.

[0013] Further, the middle region of the gate is a split gate;

[0014] The middle region of the split gate is filled with source metal.

[0015] Furthermore, the gate includes a gate trench, a gate dielectric layer and polysilicon;

[0016] The trench is arranged in the N+ current spreading layer along the first direction, the gate dielectric layer is arranged on the inner wall side of the gate trench, and the polysilicon is arranged in a groove formed by the gate dielectric layer.

[0017] Furthermore, the multi-threshold voltage modulated wide bandgap semiconductor device structure further includes an interlayer dielectric layer;

[0018] The interlayer dielectric layer covers the open portion of the groove formed by the gate dielectric layer.

[0019] Furthermore, the stacking of the first P-well region and the first source N+ region specifically includes:

[0020] The first source N+ region is located above the first P-well region, and an upper surface of the first source N+ region contacts a lower surface of the interlayer dielectric layer.

[0021] Furthermore, the multi-threshold voltage modulated wide bandgap semiconductor device structure further includes a source ohmic contact region;

[0022] The source contacts the interlayer dielectric layer, the first source N+ region, the second source N+ region, the first source P+ region, and the second source P+ region through the source ohmic contact region.

[0023] Furthermore, the substrate is a wide bandgap semiconductor material.

[0024] In a second aspect, the present invention further provides a method for manufacturing a wide bandgap semiconductor device structure with multi-threshold voltage modulation as described in the first aspect, comprising:

[0025] An epitaxial layer and an N+ current spreading layer are sequentially grown on the substrate;

[0026] Forming a first P-well region by ion implantation, secondary epitaxy or growing a P-type oxide; forming a first source N+ region by ion implantation;

[0027] forming a first source P+ region and a second source P+ region by ion implantation;

[0028] Forming a P+ masking layer by P-type ion implantation;

[0029] Dry etching to form a gate trench;

[0030] forming a second source N+ region and a second P-well region by ion implantation;

[0031] Growing and etching to form a gate at the gate trench;

[0032] Growing, depositing and etching to form an interlayer dielectric layer at the gate;

[0033] A source metal is deposited on the interlayer dielectric layer to form a source electrode; and a drain metal is deposited at the bottom of the substrate to form a drain electrode, thereby obtaining a wide bandgap semiconductor device structure modulated by multiple threshold voltages.

[0034] Based on the above technical solution, the present invention can also be improved as follows.

[0035] Furthermore, the step of growing and etching the gate at the gate trench specifically includes:

[0036] Gate dielectric layer growth, gate polysilicon growth and etching;

[0037] The gate polysilicon is etched to form a split gate.

[0038] Furthermore, before depositing the source metal on the interlayer dielectric layer, the method further includes:

[0039] An ohmic contact metal is deposited on the first source N+ region, the second source N+ region, the first source P+ region and the second source P+ region to form a source ohmic contact region.

[0040] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0041] The multi-threshold voltage modulated wide bandgap semiconductor device structure provided by the present invention is formed with a substrate, an epitaxial layer, an N+ current spreading layer, a first source N+ region, a second source N+ region, a first source P+ region, a second source P+ region, a first P-well region, a second P-well region, a P+ shielding layer, a gate, a source and a drain;

[0042] The epitaxial layer, the N+ current spreading layer and the source electrode are sequentially arranged on the substrate; the drain electrode is arranged at the bottom of the substrate;

[0043] The gate is arranged in the middle area of ​​the N+ current extension layer along the first direction, the P+ shielding layer is arranged close to the epitaxial layer, and is extended from the middle area of ​​the N+ current extension layer along the second direction to the edge of the first side by ion implantation; the second P-well region and the second source N+ region arranged in sequence along the second direction are located between the gate and the P+ shielding layer; the second source P+ region is arranged on the P+ shielding layer, and is in contact with the edge of the second source N+ region and the gate on one side along the second direction, and is extended to the edge of the first side of the N+ current extension layer on the other side; the second source N+ region, the second P-well region and the N+ current extension layer form a new current path; wherein the first direction and the second direction are arranged vertically;

[0044] The first source P+ region is disposed on the epitaxial layer and is located at the edge of the second side of the N+ current extension layer; a first P-well region and a first source N+ region are superimposed between the first source P+ region and the gate. Compared with the prior art, the present invention has the following beneficial effects:

[0045] (1) The deep masking structure formed by the P+ masking layer, the second P-well region, and the first source P+ region can better protect the gate groove angle and improve the gate oxide reliability of the device; further, the second P-well region is formed by ion implantation at the bottom of the trench after trench etching, and no additional mask is required. The P+ masking layer is formed by ion implantation before trench etching. The P+ masking layer has a high concentration and can better protect the gate groove angle together with the first source P+ region to reduce the groove angle electric field;

[0046] (2) The second source N+ region, the second P-well region and the N+ current extension layer form a new current path, thereby utilizing multiple channels to modulate the trench MOSFET; multi-channel modulation can increase the current density of the device, and more channels and more current paths can improve the conduction characteristics of the device;

[0047] (3) The P+ shielding layer can be kept in a grounded state through the second source P+ region, thereby enhancing the protection effect of the P+ shielding layer on the gate and better improving the dynamic characteristics of the device;

[0048] (4) Multiple channels can be designed with different threshold voltages. Different threshold voltages result in different on-resistances of the channels. Therefore, modulation of the multiple channels can control the on-resistance of the channel region of the device, and further control the part of the positive temperature coefficient in the overall on-resistance of the device, so that the turning point of the overall on-resistance from the negative temperature coefficient to the positive temperature coefficient can be controlled. In other words, the device can be modulated to have a low on-resistance at a higher temperature. This type of device is more suitable for high-temperature application scenarios and can meet more application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1A schematic structural diagram of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided in Embodiment 1 of the present invention;

[0050] Figure 2 The gate polysilicon layout diagram provided in Embodiment 1 of the present invention;

[0051] Figure 3 A schematic diagram of the current path of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided in Embodiment 1 of the present invention;

[0052] Figure 4 A schematic diagram of the manufacturing process of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided in Embodiment 2 of the present invention;

[0053] Figure 5 A schematic structural diagram of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided by Embodiment 3 of the present invention;

[0054] Figure 6 One of the structural schematic diagrams of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided by Embodiment 4 of the present invention;

[0055] Figure 7 The second structural schematic diagram of the wide bandgap semiconductor device structure with multi-threshold voltage modulation provided by Embodiment 4 of the present invention;

[0056] Figure 8 A schematic structural diagram of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided by Embodiment 5 of the present invention;

[0057] Fig. 9 A schematic structural diagram of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided by Embodiment 6 of the present invention;

[0058] Fig.10 A schematic structural diagram of a wide bandgap semiconductor device structure with multi-threshold voltage modulation provided in Embodiment 7 of the present invention;

[0059] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0060] 1. Substrate; 2. Epitaxial layer; 3. N+ current spreading layer; 4. First source N+ region; 5. Second source N+ region; 6. First source P+ region; 7. Second source P+ region; 8. First P-well region; 9. Second P-well region; 10. P+ masking layer; 11. Gate; 1101. Gate dielectric layer, 1102. Polysilicon; 12. Interlayer dielectric layer; 13. Source ohmic contact region; 14. Source; 15. Drain. DETAILED DESCRIPTION

[0061] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0062] In the prior art, in order to better protect the gate oxide layer and relatively excellent conduction characteristics of trench MOSFET, there are two main technical solutions and device structures for wide bandgap semiconductor trench MOSFET in the industry. These include the "P+ semi-wrapped asymmetric trench structure" adopted by Infineon in Germany, which uses a single-side area to ensure device current conduction; and the Japanese Rohm adopts a source double trench structure constructed on both sides of the gate trench to shield the bottom of the middle gate trench, and the middle area to ensure current conduction on both sides of the device. For currently commercially available devices, the on-resistance is basically a negative temperature coefficient at negative temperatures. After passing an inflection point of about 0 to 25°C, it maintains a positive temperature coefficient, which results in the device having a lower on-resistance near the inflection point; that is, the current device is more suitable for application scenarios at room temperature, but for some higher temperature application scenarios, it is necessary to design devices with better on-resistance at higher temperatures.

[0063] The existing technical solutions are prone to damage to the gate dielectric layer under harsh conditions such as avalanche breakdown or short circuit. The main reason is that under extreme electrical stress such as current or voltage surges, the device provides limited protection for the gate dielectric layer in the corners of the trench; the on-resistance has a negative temperature coefficient at negative temperatures, and after passing an inflection point of about 0 to 25°C, it maintains a positive temperature coefficient, which causes the device to have a lower on-resistance near the inflection point; that is, the current devices are more suitable for application scenarios at room temperature, but for some application scenarios with higher temperatures, it is necessary to design devices with better on-resistance at higher temperatures.

[0064] Based on this, the present invention provides a new wide bandgap semiconductor device structure with multi-threshold voltage modulation.

[0065] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0066] It should be noted that the terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0067] Example 1

[0068] like Figure 1As shown, this embodiment provides a wide bandgap semiconductor device structure with multi-threshold voltage modulation, including: a substrate 1, an epitaxial layer 2, an N+ current spreading layer 3, a first source N+ region 4, a second source N+ region 5, a first source P+ region 6, a second source P+ region 7, a first P-well region 8, a second P-well region 9, a P+ masking layer 10, a gate 11, a source 14 and a drain 15.

[0069] The epitaxial layer 2 , the N+ current spreading layer 3 and the source 14 are sequentially arranged on the substrate 1 ; and the drain 15 is arranged at the bottom of the substrate 1 .

[0070] In an optional example, the substrate 1 is a wide bandgap semiconductor material. The wide bandgap semiconductor material may be silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), semiconductor materials such as aluminum nitride (AlN), etc.

[0071] Specifically, the gate 11 is arranged in the middle area of ​​the N+ current expansion layer 3 along the first direction, the P+ masking layer 10 is arranged close to the epitaxial layer 2, and is extended from the middle area of ​​the N+ current expansion layer 3 along the second direction to the edge of the first side through ion implantation; the second P-well region 9 and the second source N+ region 5 arranged in sequence along the second direction are located between the gate 11 and the P+ masking layer 10; the second source P+ region 7 is arranged on the P+ masking layer 10, and is in contact with the edges of the second source N+ region 5 and the gate 11 on one side along the second direction, and is extended to the edge of the first side of the N+ current expansion layer 3 on the other side; the second source N+ region 5, the second P-well region 9 and the N+ current expansion layer 3 form a new current path.

[0072] The first direction and the second direction are arranged vertically.

[0073] The first source P+ region 6 is disposed on the epitaxial layer 2 and is located at an edge of the second side of the N+ current spreading layer 3 .

[0074] Specifically, the deep masking structure formed by the P+ masking layer 10, the second P-well region 9 and the first source P+ region 6 can better protect the groove corner of the gate 11 and improve the gate oxide reliability of the device.

[0075] Furthermore, the second P-well region 9 is formed by ion implantation at the bottom of the trench after trench etching, and no additional mask is required. The P+ masking layer 10 is formed before trench etching. The P+ masking layer 10 has a higher concentration and can better protect the gate 11 trench corner together with the first source P+ region 6, thereby reducing the trench corner electric field.

[0076] The P+ shielding layer 10 can be kept in a grounded state through the second source P+ region 7, thereby enhancing the protection effect of the P+ shielding layer 10 on the gate and better improving the dynamic characteristics of the device.

[0077] A first P-well region 8 and a first source N+ region 4 are superimposed between the first source P+ region 6 and the gate 11 .

[0078] Specifically, the first P-well region 8 and the first source N+ region 4 are stacked and specifically include: the first source N+ region 4 is located above the first P-well region 8 , and the upper surface of the first source N+ region 4 contacts the lower surface of the interlayer dielectric layer 12 .

[0079] In an optional embodiment, the gate 11 includes a gate trench, a gate dielectric layer 1101 and polysilicon 1102 .

[0080] The trench is arranged in the N+ current spreading layer 3 along the first direction, the gate dielectric layer 1101 is arranged on the inner wall side of the gate trench, and the polysilicon 1102 is arranged in the groove formed by the gate dielectric layer 1101 .

[0081] It should be noted that the middle region of the gate 11 is a split gate; the middle region of the split gate is filled with source metal.

[0082] The ion implantation of the second source N+ region 5 is performed at the bottom of the trench, and at the same time, the second P-well region 9 is formed at the bottom of the trench by ion implantation, so that a new channel can be formed at the bottom of the trench. Figure 3 As shown, it is a multi-channel current path diagram. Multi-channel modulation can increase the current density of the device. More channels and more current paths can improve the conduction characteristics of the device.

[0083] like Figure 2 As shown, combined with the gate polysilicon layout, it can be seen that in the first direction, the middle area of ​​the gate 11 is in a hollow state, and the gate 11 is split into a split gate structure.

[0084] The polysilicon gate in the trench is in the form of a split gate, so that a good ohmic contact area can be formed between the two split gates, so that the second source N+ region 5 and the source P+ region are kept in a grounded state at the same time, and the source P+ region can also ensure a good grounding state through the ohmic contact on the surface, so that the second source N+ region 5, the second P-well region 9 and the N+ current expansion layer 3 can also form a new current path, so as to use multiple channels to modulate the trench MOSFET; at the same time, Figure 2 As shown, section B is a complete gate structure, which connects the split gates in section A together, thereby keeping the split gates in section A at the same potential.

[0085] Furthermore, the multi-threshold voltage modulated wide bandgap semiconductor device structure further includes an interlayer dielectric layer 12 ; the interlayer dielectric layer 12 covers the open portion of the groove formed by the gate dielectric layer 1101 .

[0086] In addition, the multi-threshold voltage modulated wide bandgap semiconductor device structure also includes a source ohmic contact region 13; the source 14 contacts the first source N+ region 4, the second source N+ region 5, the first source P+ region 6 and the second source P+ region 7 through the source ohmic contact region 13.

[0087] Compared with the prior art, the multi-threshold voltage modulated wide bandgap semiconductor device structure provided in this embodiment has the following beneficial effects:

[0088] (1) The deep masking structure formed by the P+ masking layer, the second P-well region, and the first source P+ region can better protect the gate groove angle and improve the gate oxide reliability of the device; further, the second P-well region is formed by ion implantation at the bottom of the trench after trench etching, and no additional mask is required. The P+ masking layer is formed by ion implantation before trench etching. The P+ masking layer has a high concentration and can better protect the gate groove angle together with the first source P+ region to reduce the groove angle electric field;

[0089] (2) The second source N+ region, the second P-well region and the N+ current extension layer form a new current path, thereby utilizing multiple channels to modulate the trench MOSFET; multi-channel modulation can increase the current density of the device, and more channels and more current paths can improve the conduction characteristics of the device;

[0090] (3) The P+ shielding layer can be kept in a grounded state through the second source P+ region, thereby enhancing the protection effect of the P+ shielding layer on the gate and better improving the dynamic characteristics of the device;

[0091] (4) Multiple channels can be designed with different threshold voltages. Different threshold voltages result in different on-resistances of the channels. Therefore, modulation of the multiple channels can control the on-resistance of the channel region of the device, and further control the part of the positive temperature coefficient in the overall on-resistance of the device, so that the turning point of the overall on-resistance from the negative temperature coefficient to the positive temperature coefficient can be controlled. In other words, the device can be modulated to have a low on-resistance at a higher temperature. This type of device is more suitable for high-temperature application scenarios and can meet more application scenarios.

[0092] Example 2

[0093] This embodiment provides a method for manufacturing a wide bandgap semiconductor device structure with multi-threshold voltage modulation, such as Figure 4 As shown, the operation is as follows:

[0094] Step S1: (cross section A&B) sequentially growing an epitaxial layer and an N+ current spreading layer on a wide bandgap semiconductor material substrate;

[0095] Step S2: (cross section A & B) forming a first P-well region by ion implantation, secondary epitaxy or growing a P-type oxide; forming a first source N+ region by ion implantation;

[0096] Step S3: (cross section A & B) forming a first source P+ region and a second source P+ region by ion implantation;

[0097] Step S4: (cross section A & B) forming a P+ masking layer by P-type ion implantation;

[0098] Step S5: (cross section A & B) dry etching to form a gate trench;

[0099] Step S6: (cross section A & B) forming a second P-well region by ion implantation;

[0100] Step S7: (cross section A & B) forming a second source N+ region by ion implantation;

[0101] Step S8: (cross section A & B) growing and etching at the gate trench to form a gate;

[0102] Specifically including: gate dielectric layer growth, gate polysilicon growth and etching.

[0103] Step S9: (cross section A) etching the gate polysilicon to form a split gate; growing, depositing and etching at the gate to form an interlayer dielectric layer;

[0104] Step S10: (cross section A and cross section B) depositing an ohmic contact metal on the first source N+ region, the second source N+ region, the first source P+ region and the second source P+ region to form a source ohmic contact region;

[0105] Step S11: (Section A and Section B) deposit source metal to form a source; deposit drain metal at the bottom of the substrate to form a drain, thereby obtaining a wide bandgap semiconductor device structure with multi-threshold voltage modulation.

[0106] Since this manufacturing method is used to manufacture the wide bandgap semiconductor device structure with multi-threshold voltage modulation provided in Example 1, the beneficial effects of the wide bandgap semiconductor device structure with multi-threshold voltage modulation are also applicable to this manufacturing method. For its beneficial effects, please refer to the above-mentioned effect description and will not be repeated here.

[0107] Example 3

[0108] Based on the above-mentioned embodiments 1 and 2, this embodiment can selectively perform ion implantation of the second P-well region 9 before trench etching, so that the width of the second P-well region 9 can be greater than the trench width, and the obtained structure is as follows: Figure 5 As shown, this structure can provide better protection for the gate, reduce the gate oxide electric field, and improve device reliability. For the rest of the same structure, refer to the introduction of embodiment 1, which will not be repeated here.

[0109] Example 4

[0110] Based on the above embodiment 3, this embodiment can also selectively perform ion implantation of the P+ shielding layer 10 before trench etching, so that a wider P+ shielding layer 10 can be formed, such as Figure 6 As shown, the left side width of the P+ shielding layer 10 is equal to the left side width of the trench. Figure 7 As shown, the left width of the P+ shielding layer 10 is greater than the left width of the trench, and this structure can better protect the gate trench corner and improve device reliability. For the rest of the same structure, refer to the introduction of embodiment 1, which will not be repeated here.

[0111] Example 5

[0112] On the basis of the above-mentioned embodiment 1, this embodiment can selectively perform ion implantation of the second source N+ region 5 before trench etching, so that the second source N+ region 5 can form an ohmic contact with the second source P+ region 7 on the surface at the same time, and the ohmic contact at the bottom of the trench can reduce the on-resistance of the second source N+ region 5, and the obtained structure is as follows: Figure 8 As shown, the device structure can also reduce the gate oxide electric field while improving the conduction characteristics of the device. For the rest of the same structure, refer to the introduction of embodiment 1, which will not be repeated here.

[0113] Example 6

[0114] On the basis of the above-mentioned embodiment 1, this embodiment can selectively implant the ions of the first source P+ region 6 and the second source P+ region 7 at the same time deeper, which can better protect the gate, reduce the gate oxide electric field, and improve the reliability of the device; at the same time, the electric field can be modulated to form a super junction effect, and the electrical characteristics of the device can be improved. The obtained structure is as follows Fig. 9 As shown in the figure, the rest of the same structure can be found in the description of Embodiment 1, which will not be described again here.

[0115] Example 7

[0116] On the basis of the above-mentioned embodiment 6, this embodiment can selectively implant the ions of the first source P+ region 6 and the second source P+ region 7 deeper at the same time, and at the same time, the P+ masking layer 10 has a wider implant width, which is larger than the gate trench, so as to better protect the gate, reduce the gate oxide electric field, and improve the reliability of the device; at the same time, the electric field can be modulated to form a super junction effect, and the electrical characteristics of the device can be improved. The obtained structure is as follows Fig.10 As shown. For the rest of the same structure, refer to the introduction of Example 1, which will not be repeated here.

[0117] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wide bandgap semiconductor device structure with multi-threshold voltage modulation, characterized in that: include: Substrate, epitaxial layer, N+ current spreading layer, first source N+ region, second source N+ region, first source P+ region, second source P+ region, first P-well region, second P-well region, P+ shielding layer, gate, source and drain; The epitaxial layer, the N+ current spreading layer and the source electrode are sequentially arranged on the substrate; the drain electrode is arranged at the bottom of the substrate; The gate is arranged along the first direction through the middle area of ​​the N+ current extension layer, the P+ shielding layer is arranged close to the epitaxial layer, and is extended from the middle area of ​​the N+ current extension layer along the second direction to the edge of the first side by ion implantation; the second P-well region and the second source N+ region arranged in sequence along the second direction are located between the gate and the P+ shielding layer; The second source P+ region is disposed on the P+ shielding layer, and one side along the second direction is in contact with the edge of the second source N+ region and the gate, and the other side is extended to the edge of the first side of the N+ current spreading layer; the second source N+ region, the second P-well region and the N+ current spreading layer form a new current path; wherein the first direction and the second direction are arranged perpendicularly; The first source P+ region is arranged on the epitaxial layer and located at the edge of the second side of the N+ current spreading layer; the first P-well region and the first source N+ region are superimposed between the first source P+ region and the gate.

2. The multi-threshold voltage modulated wide bandgap semiconductor device structure according to claim 1, characterized in that: The middle region of the gate is a split gate; The middle region of the split gate is filled with source metal.

3. The multi-threshold voltage modulated wide bandgap semiconductor device structure according to claim 2, characterized in that: The gate comprises a gate trench, a gate dielectric layer and polysilicon; The trench is arranged in the N+ current spreading layer along the first direction, the gate dielectric layer is arranged on the inner wall side of the gate trench, and the polysilicon is arranged in a groove formed by the gate dielectric layer.

4. The multi-threshold voltage modulated wide bandgap semiconductor device structure according to claim 3, characterized in that: The multi-threshold voltage modulated wide bandgap semiconductor device structure further includes an interlayer dielectric layer; The interlayer dielectric layer covers the open portion of the groove formed by the gate dielectric layer.

5. The multi-threshold voltage modulated wide bandgap semiconductor device structure according to claim 4, characterized in that: The stacking of the first P-well region and the first source N+ region specifically includes: The first source N+ region is located above the first P-well region, and an upper surface of the first source N+ region contacts a lower surface of the interlayer dielectric layer.

6. The multi-threshold voltage modulated wide bandgap semiconductor device structure according to claim 5, characterized in that: The multi-threshold voltage modulated wide bandgap semiconductor device structure further includes a source ohmic contact region; The source contacts the interlayer dielectric layer, the first source N+ region, the second source N+ region, the first source P+ region and the second source P+ region through the source ohmic contact region.

7. The multi-threshold voltage modulated wide bandgap semiconductor device structure according to claim 1, characterized in that: The substrate is a wide bandgap semiconductor material.

8. A method for manufacturing a wide bandgap semiconductor device structure with multi-threshold voltage modulation as claimed in any one of claims 1 to 7, characterized in that: include: An epitaxial layer and an N+ current spreading layer are sequentially grown on the substrate; Forming a first P-well region by ion implantation, secondary epitaxy or growing a P-type oxide; forming a first source N+ region by ion implantation; forming a first source P+ region and a second source P+ region by ion implantation; Forming a P+ masking layer by P-type ion implantation; Dry etching to form a gate trench; forming a second source N+ region and a second P-well region by ion implantation; Growing and etching to form a gate at the gate trench; Growing, depositing and etching to form an interlayer dielectric layer at the gate; Depositing source metal on the interlayer dielectric layer to form a source electrode; A drain metal is deposited at the bottom of the substrate to form a drain, thereby obtaining a wide bandgap semiconductor device structure with multi-threshold voltage modulation.

9. The manufacturing method according to claim 8, characterized in that: The step of growing and etching the gate at the gate trench specifically includes: Gate dielectric layer growth, gate polysilicon growth and etching; The gate polysilicon is etched to form a split gate.

10. The manufacturing method according to claim 9, characterized in that: Before depositing the source metal on the interlayer dielectric layer, the method further includes: An ohmic contact metal is deposited on the first source N+ region, the second source N+ region, the first source P+ region and the second source P+ region to form a source ohmic contact region.

Images