Semiconductor memory device

Abstract

This semiconductor memory device is provided with: a plurality of memory layers (ML) arranged in a first direction (Z); a first via wiring (104) extending in the first direction; and a second via wiring (104) extending in the first direction at a position different from that of the first via wiring in a second direction (X). The plurality of memory layers are provided with: a first wiring (120) provided between the first via wiring and the second via wiring and extending in the third direction; a first semiconductor layer electrically connected to the first via wiring; a first gate electrode facing the first semiconductor layer and electrically connected to the first wiring; a first memory unit (130) electrically connected to the first semiconductor layer; a second semiconductor layer electrically connected to the second via wiring; a second gate electrode facing the second semiconductor layer and electrically connected to the first wiring; and a second memory unit (130) electrically connected to the second semiconductor layer.

Description

[0001] [Related applications]

[0002] This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2023-100328 filed on Jun. 19, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various embodiments described herein generally relate to a semiconductor memory device. Background Art

[0004] As semiconductor memory devices become more highly integrated, research into three-dimensional semiconductor memory devices is being conducted. Summary of the invention

[0005] Embodiments of the present invention provide a semiconductor memory device capable of achieving high integration.

[0006] A semiconductor memory device according to one embodiment includes: a substrate; a plurality of memory layers arranged in a first direction intersecting a surface of the substrate; a first through-hole wiring extending in the first direction; and a second through-hole wiring extending in the first direction at a position different from that of the first through-hole wiring in a second direction intersecting the first direction. The plurality of memory layers each include a first wiring, which is provided between the first through-hole wiring and the second through-hole wiring and extends in a third direction intersecting the first direction and the second direction. In addition, the plurality of memory layers each include: a first semiconductor layer electrically connected to the first through-hole wiring; a first gate electrode facing the first semiconductor layer and electrically connected to the first wiring; and a first memory portion provided on the opposite side of the first wiring in the second direction relative to the first semiconductor layer and electrically connected to the first semiconductor layer. In addition, the multiple memory layers respectively include: a second semiconductor layer, electrically connected to a second through-hole wiring; a second gate electrode, opposite to the second semiconductor layer, electrically connected to the first wiring; and a second memory unit, arranged on the opposite side of the first wiring in the second direction relative to the second semiconductor layer, and electrically connected to the second semiconductor layer.

[0007] According to the above configuration, a semiconductor memory device capable of achieving high integration can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a schematic circuit diagram showing a partial configuration of a semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is a schematic perspective view showing a partial configuration of the semiconductor memory device according to the first embodiment.

[0010] Figure 3 This is a schematic perspective view showing a partial configuration of the semiconductor memory device according to the first embodiment.

[0011] Figure 4 This is a schematic perspective view showing a partial configuration of the semiconductor memory device according to the first embodiment.

[0012] Figure 5 It is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device according to the first embodiment.

[0013] Figure 6 It is a schematic plan view showing a partial structure of the semiconductor memory device according to the first embodiment.

[0014] Figure 7 It is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device according to the first embodiment.

[0015] Figure 8 This is a schematic cross-sectional view showing a partial structure of the semiconductor memory device according to the first embodiment.

[0016] Fig. 9 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0017] Fig.10 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0018] Fig.11 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0019] Fig.12 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0020] Fig.13 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0021] Fig.14 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0022] Fig.15 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0023] Fig.16 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0024] Fig.17 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0025] Fig.18 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0026] Fig.19 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0027] Fig. 20 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0028] Fig.21 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0029] Fig. 22 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0030] Fig.23 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0031] Fig.24 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0032] Fig.25 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0033] Fig.26 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0034] Fig. 27 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0035] Fig.28 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0036] Fig.29 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0037] Fig.30This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0038] Fig.31 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0039] Fig.32 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0040] Fig.33 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0041] Fig.34 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0042] Fig.35 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0043] Fig.36 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0044] Fig.37 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0045] Fig.38 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0046] Fig.39 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0047] Fig.40 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0048] Fig.41 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0049] Fig.42 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0050] Fig.43 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0051] Fig.44 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0052] Fig.45 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0053] Fig.46 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0054] Fig.47 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0055] Fig.48 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0056] Fig.49 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0057] Fig.50 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0058] Fig.51 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0059] Fig.52 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0060] Fig.53 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0061] Fig.54 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0062] Fig.55 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0063] Fig.56 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0064] Fig.57This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0065] Fig.58 This is a schematic XY cross-sectional view for explaining the effects of the semiconductor memory device according to the first embodiment.

[0066] Fig.59 This is a schematic XY cross-sectional view for explaining the effects of the semiconductor memory device according to the first embodiment.

[0067] Fig.60 It is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device according to the second embodiment.

[0068] Fig.61 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to the third embodiment.

[0069] Fig.62 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0070] Fig.63 It is a schematic plan view showing a partial structure of a semiconductor memory device according to a fifth embodiment.

[0071] Fig.64 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to a sixth embodiment.

[0072] Fig.65 It is a schematic plan view showing a partial structure of a semiconductor memory device according to a sixth embodiment.

[0073] Fig.66 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to the seventh embodiment.

[0074] Fig.67 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to the eighth embodiment.

[0075] Fig.68 It is a schematic plan view showing a partial structure of a semiconductor storage device according to the eighth embodiment.

[0076] Fig.69 It is a schematic top view showing a partial structure of a semiconductor storage device according to a ninth embodiment.

[0077] Fig.70 It is a schematic XY cross-sectional view showing a partial structure of a semiconductor memory device according to a tenth embodiment.

[0078] Fig.71 It is a schematic plan view showing a partial structure of a semiconductor storage device according to a tenth embodiment.

[0079] Fig.72 This is a schematic circuit diagram showing a partial structure of a semiconductor storage device according to the eleventh embodiment.

[0080] Fig.73 This is a schematic perspective view showing a partial structure of a semiconductor storage device according to the eleventh embodiment.

[0081] Fig.74 It is a schematic plan view showing a partial structure of a semiconductor storage device according to the eleventh embodiment.

[0082] Fig.75 It is a schematic plan view showing a partial structure of a semiconductor storage device according to a twelfth embodiment.

[0083] Fig.76 It is a schematic plan view showing a partial structure of a semiconductor storage device according to a thirteenth embodiment.

[0084] Fig.77 It is a schematic plan view showing a partial structure of a semiconductor storage device according to a fourteenth embodiment.

[0085] Fig.78 It is a schematic top view showing a partial structure of a semiconductor storage device according to a fifteenth embodiment. DETAILED DESCRIPTION

[0086] Next, the semiconductor memory device of the embodiment is described in detail with reference to the accompanying drawings. In addition, the following embodiment is only an example, and the purpose of illustrating them is not to limit the present invention. In addition, the following drawings are schematic, and for the sake of convenience of description, a part of the structure is sometimes omitted. In addition, sometimes the same symbol is marked for the common parts of multiple embodiments, and the description is omitted.

[0087] In addition, in this specification, when the term "semiconductor storage device" is used, it sometimes refers to a memory chip, a memory card, an SSD (Solid State Drive) or other memory system including a controller chip. Furthermore, it sometimes refers to a configuration including a host such as a smartphone, a tablet terminal, or a personal computer.

[0088] In addition, in this specification, when it is expressed that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, even if the second transistor is in the disconnected (OFF) state, the first transistor is still "electrically connected" to the third transistor.

[0089] In addition, in this specification, when it is expressed that the first structure is "electrically connected" "between" the second structure and the third structure, it sometimes means that the first structure, the second structure and the third structure are connected in series, and the second structure is electrically connected to the third structure via the first structure.

[0090] In addition, in this specification, when it is expressed that a circuit or the like makes two wirings or the like "conduct", for example, it sometimes means that the circuit or the like includes a transistor or the like, the transistor or the like is provided in a current path between the two wirings, and the transistor or the like is in a conducting (ON) state.

[0091] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0092] In addition, in this specification, a direction along a predetermined surface is sometimes referred to as a first direction, a direction along the predetermined surface intersecting the first direction is sometimes referred to as a second direction, and a direction intersecting the predetermined surface is sometimes referred to as a third direction. These first direction, second direction, and third direction may correspond to any one of the X direction, the Y direction, and the Z direction, or may not correspond to any of them.

[0093] In addition, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called upper, and the direction close to the substrate along the Z direction is called lower. In addition, when a certain structure is expressed as a lower surface or a lower end, it means the surface or end of the substrate side of the structure, and when it is expressed as an upper surface or an upper end, it means the surface or end of the structure on the opposite side of the substrate. In addition, the surface intersecting the X direction or the Y direction is called a side surface, etc.

[0094] In addition, in this specification, when expressing the "center position" of a certain structure, it may mean, for example, the center position of the circumscribed circle of the structure, or the center of gravity of the figure of the structure on a predetermined plane.

[0095] [First embodiment]

[0096] [Circuit configuration]

[0097] Figure 1FIG. 1 is a schematic circuit diagram showing a part of the structure of the semiconductor memory device according to the first embodiment. Figure 1 As shown, the semiconductor memory device of this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML0 to ML3, a plurality of bit lines BL connected to the plurality of memory layers ML0 to ML3, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL, and a plate line PL connected to the plurality of memory layers ML0 to ML3.

[0098] The memory layers ML0 to ML3 each include a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL"), and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. The memory cells MC each include a transistor TrC and a capacitor CpC. The source electrode of the transistor TrC is connected to the bit line BL. The drain electrode of the transistor TrC is connected to the capacitor CpC. The gate electrode of the transistor TrC is connected to any one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the drain electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to the plate line PL.

[0099] In addition, each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML0 to ML3. In addition, each bit line BL is connected to a global bit line GBL.

[0100] In addition, the memory layers ML0 to ML3 respectively include a plurality of transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b, TrL3a, TrL3b (hereinafter sometimes referred to as "transistor TrL") provided corresponding to the plurality of word lines WL0 to WL2. The drain electrode of the transistor TrL is connected to any one of the word lines WL0 to WL2. The source electrode of the transistor TrL is respectively connected to the word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, LW2b (hereinafter sometimes referred to as "word line selection line LW"). The gate electrode of the transistor TrL is respectively connected to the layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, LL2b, LL3a, LL3b (hereinafter sometimes referred to as "layer selection line LL").

[0101] In addition, the word line selection line LW is connected to a plurality of transistors TrL corresponding to a plurality of memory layers ML0 to ML3. In addition, the layer selection lines LL0a, LL1a, LL2a, and LL3a are respectively commonly connected to all transistors TrL0a, TrL1a, TrL2a, and TrL3a corresponding to the memory layers ML0 to ML3. Similarly, the layer selection lines LL0b, LL1b, LL2b, and LL3b are respectively commonly connected to all transistors TrL0b, TrL1b, TrL2b, and TrL3b corresponding to the memory layers ML0 to ML3.

[0102] [structure]

[0103] Figure 2 and Figure 3 This is a schematic perspective view showing a partial configuration of the semiconductor memory device according to the first embodiment. Figure 3 The figure shows Figure 2 The omitted part of the composition. Figure 4 is a schematic perspective view showing a part of the structure of the semiconductor storage device, and an enlarged view showing Figure 2 part of. Figure 5 It is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device. Figure 6 It is a schematic plan view showing a partial structure of the semiconductor memory device. Figure 7 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device, and an enlarged view showing Figure 5 part of. Figure 8 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device, showing a cross-sectional view taken along line AA' Figure 7 The structure shown is the structure viewed along the direction of the arrow.

[0104] At Figure 2 and Figure 3 Detailed description is given in the figure to illustrate a portion of a semiconductor substrate Sub and a memory cell array MCA disposed above the semiconductor substrate Sub.

[0105] The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). An insulating layer and an electrode layer not shown are provided on the upper surface of the semiconductor substrate Sub. On the upper surface of the semiconductor substrate Sub, the insulating layer and the electrode layer not shown constitute a control circuit for controlling the semiconductor storage device of the first embodiment. For example, a sense amplifier circuit is provided in an area directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the bit line BL. The sense amplifier circuit can read the data stored in the selected memory cell MC by detecting the change in the voltage or current of the bit line BL during the read operation.

[0106] The memory cell array MCA includes a plurality of memory layers ML arranged in the Z direction. In addition, an insulating layer 103 made of silicon oxide (SiO 2 ) or the like is provided between the plurality of memory layers ML.

[0107] In addition, the memory cell array MCA includes a plurality of structures extending in the Z direction through the plurality of memory layers ML, and wiring layers M0 and M1 ( Figure 3 ).

[0108] Hereinafter, a plurality of structures extending in the Z direction through the plurality of memory layers ML, the plurality of memory layers ML, and the wiring layers M0 and M1 will be described in order.

[0109] [Multiple Structures Extending in the Z Direction Penetrating Multiple Memory Layers ML]

[0110] In the memory cell array MCA, a plurality of conductive members 102 are arranged in the X direction. The plurality of conductive members 102 extend in the Y direction and the Z direction, respectively, and divide the memory layer ML in the X direction.

[0111] The conductive member 102 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive member 102 is, for example, a plate line PL ( Figure 1 ) to perform its function.

[0112] In addition, in the memory cell array MCA, a plurality of via wirings 104 arranged in the Y direction are provided in a region between the conductive member 102 and a conductive layer 120 described later. The plurality of via wirings 104 extend in the Z direction through the plurality of memory layers ML, respectively.

[0113] like Figure 4 As shown, the through-hole wiring 104 includes, for example, a conductive oxide film 104a containing a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive component 104c such as tungsten (W). In addition, the through-hole wiring 104 may also include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104a. In addition, the through-hole wiring 104 may only include a conductive oxide, or only include ruthenium (Ru), iridium (Ir), or other metals.

[0114] In this specification, “conductive oxide” includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), or other conductive materials containing oxygen.

[0115] The conductive component 104c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive component 104c. The conductive oxide film 104a has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 104b. The through hole wiring 104 is used as a bit line BL ( Figure 1 ) to perform its function.

[0116] In addition, if Figure 5 As shown, for example, in the first embodiment, a plurality of through-hole wirings 104 are arranged in two columns with different positions in the X direction between two conductive components 102 adjacent in the X direction. When focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive layer 120 described later are substantially consistent with the positions in the Y direction of any one of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive layer 120.

[0117] In the first embodiment, a plurality of through-hole wirings 104 are arranged between two conductive layers 120 adjacent in the X direction in two columns at different positions in the X direction. When focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive component 102 are substantially consistent with the positions in the Y direction of any one of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive component 102.

[0118] In addition, in the region corresponding to the conductive layer 120 described later in the memory cell array MCA, a plurality of insulating components 105 arranged in the Y direction along the conductive layer 120 are provided. The plurality of insulating components 105 respectively penetrate the plurality of memory layers ML and extend in the Z direction. The plurality of insulating components 105 include, for example, silicon oxide (SiO2) and the like. In the illustrated example, the central positions of the plurality of insulating components 105 in the X direction are respectively substantially consistent with the central positions of the conductive layer 120 in the X direction. In addition, in the illustrated example, the positions of the plurality of insulating components 105 in the Y direction correspond to any one of the plurality of insulating components 115 described later.

[0119] [Structure of the memory layer ML]

[0120] like Figure 5As shown, the memory layer ML, for example, comprises: a conductive layer 120, which is arranged between two conductive components 102 adjacent to each other in the X direction and extends in the Y direction; a plurality of transistor structures 110, which are arranged between the conductive component 102 and the conductive layer 120 and arranged in the Y direction corresponding to the plurality of through-hole wirings 104; and a plurality of capacitor structures 130, which are arranged between the conductive component 102 and the plurality of transistor structures 110 and arranged in the Y direction corresponding to the plurality of through-hole wirings 104.

[0121] like Figure 4 As shown, the transistor structure 110 includes, for example: a semiconductor layer 111, which is connected to the outer peripheral surface of the through-hole wiring 104 and extends in the X direction; an insulating layer 112, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the conductive layer 120 side) of the semiconductor layer 111; and a conductive layer 113, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0122] In such Figure 7 In the illustrated XY cross section, the two side surfaces of the semiconductor layer 111 in the X direction may be formed along a circle centered on the center position of the through-hole wiring 104. In addition, the side surfaces of the insulating layer 112 and the conductive layer 113 on one side (the conductive layer 120 side) in the X direction may also be formed along a circle centered on the center position of the through-hole wiring 104. In addition, the two side surfaces of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the Y direction may be formed in a straight line along the side surface of the insulating member 115.

[0123] In addition, the two side surfaces of the semiconductor layer 111 in the X direction may not be formed along a circle. In this case, for example, the two side surfaces of the semiconductor layer 111 in the X direction may be curved when viewed from the Z direction. For example, the length of the semiconductor layer 111 in the X direction may be different depending on the position in the Y direction. For example, the length of the semiconductor layer 111 in the X direction at a position close to the insulating component 115 may be shorter than the length of the semiconductor layer 111 in the X direction at a position far from the insulating component 115.

[0124] The semiconductor layer 111 serves as a transistor TrC ( Figure 1 ) channel region. The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O), or other oxide semiconductors. The plurality of semiconductor layers 111 arranged in the Z direction are commonly connected to the through-hole wiring 104 extending in the Z direction.

[0125] The insulating layer 112 serves as, for example, a transistor TrC ( Figure 1) functions as a gate insulating film. The insulating layer 112 includes, for example, silicon oxide (SiO 2 ) or the like.

[0126] The conductive layer 113 serves as a transistor TrC ( Figure 1 ) functions as a gate electrode. The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). Figure 5 As shown, the plurality of conductive layers 113 arranged in the Y direction are commonly connected to the conductive layer 120 extending in the Y direction. Figure 7 and Figure 8 As shown, the conductive layer 113 is disposed between the insulating layer 112 and faces the upper surface, the lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 .

[0127] In addition, if Figure 5 As shown, an insulating member 115 such as silicon oxide (SiO2) is provided between two semiconductor layers 111 adjacent to each other in the Y direction. The insulating member 115 extends in the Z direction through the plurality of memory layers ML.

[0128] The conductive layer 120 is, for example, a word line WL ( Figure 1 ) to function. As described above, the conductive layer 120 extends in the Y direction. Both side surfaces of the conductive layer 120 in the X direction are respectively connected to the plurality of conductive layers 113 arranged in the Y direction. Figure 7 and Figure 8 As shown, the conductive layer 120 includes a barrier conductive film 121 made of, for example, titanium nitride (TiN) or the like, and a conductive film 122 made of tungsten (W).

[0129] like Figure 5 As shown, the conductive layer 120 includes a plurality of through holes 123 arranged in the Y direction along the plurality of insulating members 105. The inner peripheral surfaces of the plurality of through holes 123 include the insulating members 105, respectively, and are connected to the outer peripheral surfaces of the insulating members 105.

[0130] like Figure 7 and Figure 8As shown, the capacitor structure 130 includes, for example: a conductive layer 131; a conductive layer 132, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface of the conductive layer 131 in the X direction (the transistor structure 110 side); an insulating layer 133, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface of the conductive layer 132 in the X direction (the transistor structure 110 side); a conductive layer 134, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface of the insulating layer 133 in the X direction (the transistor structure 110 side); an insulating layer 135, which is arranged on the upper surface, the lower surface, and the two side surfaces in the Y direction of the conductive layer 134; a conductive layer 136, which is arranged on the upper surface, the lower surface, and the two side surfaces in the Y direction of the insulating layer 135; and a conductive layer 137, which is arranged on the upper surface, the lower surface, and the two side surfaces in the Y direction of the conductive layer 136.

[0131] The conductive layers 131, 132, 136, and 137 serve as capacitors CpC ( Figure 1 ) functions as one electrode. The conductive layers 131 and 137 include, for example, tungsten (W) or the like. The conductive layers 132 and 136 include, for example, titanium nitride (TiN) or the like. The conductive layers 131, 132, 136, and 137 are connected to the conductive member 102.

[0132] The insulating layers 133 and 135 serve as capacitors CpC ( Figure 1 ) function as an insulating layer. The insulating layers 133 and 135 may be, for example, zirconium oxide (ZrO2), aluminum oxide (Al2O3) or other insulating metal oxides. In addition, the insulating layers 133 and 135 may be, for example, a laminated film of a plurality of insulating metal oxides (e.g., a laminated film of zirconium oxide and aluminum oxide).

[0133] The conductive layer 134 serves as a capacitor CpC ( Figure 1 ) functions as another electrode. The conductive layer 134 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 134 is insulated from the conductive layers 131, 132, 136, and 137 via the insulating layers 133 and 135. The conductive layer 134 is connected to the side surface of the semiconductor layer 111 in the X direction.

[0134] [Structure of Wiring Layers M0 and M1]

[0135] like Figure 3 As shown, the memory cell array MCA includes a wiring layer M0 provided above the plurality of memory layers ML and a wiring layer M1 provided above the wiring layer M0.

[0136] The wiring layer M1 includes a plurality of wirings m1. The plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or copper (Cu). At least a portion of the plurality of wirings m1 is used as a global bit line GBL ( Figure 1 The global bit lines GBL are arranged in the Y direction and extend in the X direction.

[0137] The wiring layer M0 includes a plurality of wirings m0. The plurality of wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or copper (Cu). At least a portion of the plurality of wirings m0 electrically connects the through-hole wiring 104 functioning as the bit line BL to the wiring m1 functioning as the global bit line GBL.

[0138] Here, as reference Figure 5 As described above, both side surfaces of the conductive layer 120 in the X direction are connected to the plurality of conductive layers 113 arranged in the Y direction. In this embodiment, in order to realize a 1T1C (One Transistor One Capacitor) type memory cell MC in such a configuration, the transistor structure 110 connected to the side surface of one side of the conductive layer 120 in the X direction and the transistor structure 110 connected to the side surface of the other side of the conductive layer 120 in the X direction are electrically connected to different global bit lines GBL.

[0139] For example, Figure 6 In the example, among the plurality of global bit lines GBL arranged in the Y direction, the even-numbered global bit lines GBLe from the positive side in the Y direction are arranged at positions overlapping with the corresponding plurality of bit lines BL when viewed from the Z direction. Among the plurality of wiring lines m0, the plurality of wiring lines m0e connected to such global bit lines GBLo are arranged at positions overlapping with the global bit lines GBLe and the bit lines BL when viewed from the Z direction. In addition, the through-hole contact electrodes c0e ( Figure 3 ) is electrically connected to the bit line BL, and is electrically connected to the global bit line GBLe via a through-hole contact electrode c1e extending in the Z direction.

[0140] On the other hand, among the plurality of global bit lines GBL arranged in the Y direction, the odd-numbered global bit lines GBLo from the positive side in the Y direction are arranged at positions that do not overlap with the corresponding plurality of bit lines BL when viewed from the Z direction. Among the plurality of wiring lines m0, the plurality of wiring lines m0o connected to such global bit lines GBLo extend from positions overlapping with the global bit lines GBLo to positions overlapping with the bit lines BL in the Y direction when viewed from the Z direction. In addition, at positions overlapping with both the bit lines BL and the wiring lines m0o when viewed from the Z direction, through-hole contact electrodes c0o ( Figure 3). In addition, a through-hole contact electrode c1o extending in the Z direction is provided at a position overlapping both the global bit line GBLo and the wiring m0o when viewed from the Z direction. The wiring m0o is electrically connected to the bit line BL via the through-hole contact electrode c0o, and is electrically connected to the global bit line GBLo via the through-hole contact electrode c1o.

[0141] Furthermore, in the example shown in the figure, the width of the wiring m0o in the Y direction is larger than the width of the wiring m0e in the Y direction.

[0142] [Manufacturing method]

[0143] Figure 9 to Figure 57 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 , Fig.23 , Fig.25 , Fig. 27 , Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 , Fig.39 , Fig.41 , Fig.43 , Fig.45 , Fig.47 , Fig.49 , Fig.51 and Fig.56 Shown with Figure 7 The corresponding cross section. Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig.26 , Fig.28 , Fig.30 , Fig.32 , Fig.34 , Fig.36 , Fig.38 , Fig.40 , Fig.42 , Fig.44 , Fig.46 , Fig.48 , Fig.50 , Fig.52 , Fig.54 and Fig.57 Shown with Figure 8 The corresponding cross section. Fig.55 Shown with Figure 5 The corresponding cross section.

[0144] like Fig.10 As shown, in the manufacturing method, for example, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layer MLA includes, for example, silicon nitride (Si3N4) or the like. This step is performed, for example, by CVD (Chemical Vapor Deposition).

[0145] Secondly, if Fig. 9 As shown, for example, an insulating member 115 is formed. In this step, for example, an opening is formed at a position corresponding to the insulating member 115. The opening extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction. This step is performed, for example, by RIE or the like. After the opening is formed, the insulating member 115 is formed. This step is performed, for example, by CVD or the like.

[0146] Secondly, if Fig.11 and Fig.12 As shown in FIG. 1 , for example, an opening 104A is formed at a position corresponding to the through-hole wiring 104. Fig.12 As shown, the opening 104A extends in the Z direction, penetrating through the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction. This step is performed, for example, by RIE or the like.

[0147] Secondly, if Fig.13 and Fig.14 As shown, for example, an opening 111A is formed at a position corresponding to the semiconductor layer 111. Inside the opening 111A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, a portion of the side surface of the sacrificial layer MLA in the X direction, and a portion of the side surface of the insulating member 115 in the Y direction are exposed. In this step, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 104A. This step is performed, for example, by wet etching or the like. For example, Fig.13 As shown in FIG. 1 , the side surface of the opening 111A in the X direction may be curved when viewed from the Z direction. For example, the length of the opening 111A in the X direction may differ depending on the position in the Y direction. For example, the length of the opening 111A in the X direction may be shorter at a position close to the insulating member 115 than at a position far from the insulating member 115.

[0148] Secondly, if Fig.15 and Fig.16As shown, for example, a conductive layer 113A and a sacrificial layer 111B such as silicon (Si) are formed inside the opening 111A and the opening 104A. The conductive layer 113A forms a portion of the upper surface, a portion of the lower surface, and an exposed surface in the opening 104A of the insulating layer 103, a portion of the side surface of the sacrificial layer MLA in the X direction, and a portion of the side surface of the insulating member 115 in the Y direction. In addition, the opening 111A is embedded with the sacrificial layer 111B, and the opening 104A is not embedded with the sacrificial layer 111B. This step is performed by, for example, CVD. In addition, although not shown in the figure, after the conductive layer 113A and the sacrificial layer 111B are formed, the upper part of the opening 104A is closed with an insulating layer or the like.

[0149] Secondly, if Fig.17 and Fig.18 As shown, for example, an opening 102A is formed at a position corresponding to the conductive component 102. The opening 102A extends in the Y direction and the Z direction, penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction, and the insulating component 115, and divides these components in the X direction. This step is performed, for example, by RIE or the like.

[0150] Secondly, if Fig.19 and Fig. 20 As shown, for example, an opening 130A is formed at a position corresponding to the capacitor structure 130. In this step, the sacrificial layer MLA is removed through the opening 102A. In addition, a portion of the conductive layer 113A that covers the side surface of the sacrificial layer 111B on one side in the X direction (the side surface on the opening 102A side) is removed. In this step, the side surface of the sacrificial layer 111B in the X direction is exposed inside the opening 102A. This step is performed, for example, by wet etching or the like.

[0151] Secondly, if Fig.21 and Fig. 22 As shown, for example, the sacrificial layer 111B is oxidized through the opening 102A and the opening 130A to form the insulating layer 111C. In addition, the sacrificial layer 130B made of silicon (Si) or the like is embedded in the opening 102A and the opening 130A. This step is performed by, for example, CVD or the like.

[0152] Secondly, if Fig.23 and Fig.24 As shown, for example, a conductive layer 113 is formed. In this step, for example, a portion of the sacrificial layer 111B disposed on the inner peripheral surface of the opening 104A is removed. Next, a portion of the conductive layer 113A disposed on the inner peripheral surface of the opening 104A is removed, and the conductive layer 113A is divided in the Z direction. This step is performed, for example, by wet etching or the like.

[0153] Secondly, if Fig.25 and Fig.26As shown, for example, the sacrificial layer 111B is removed. This step is performed by, for example, wet etching or the like.

[0154] Secondly, if Fig. 27 and Fig.28 As shown, for example, a portion of the insulating layer 111C and the sacrificial layer 130B is removed. This step is performed by, for example, wet etching or the like.

[0155] Secondly, if Fig.29 and Fig.30 As shown, for example, an insulating layer 112A and a sacrificial layer 111B are formed inside the opening 111A and the opening 104A. The insulating layer 112A is formed on the upper surface, the lower surface, and the exposed surface in the opening 111A of the conductive layer 113, a part of the upper surface, a part of the lower surface, and the exposed surface in the opening 104A of the insulating layer 103, a part of the side surface in the X direction of the sacrificial layer 130B, and a part of the side surface in the Y direction of the insulating component 115. In addition, the opening 111A is embedded in the sacrificial layer 111B, and the opening 104A is not embedded in the sacrificial layer 111B. This step is performed by, for example, CVD. In addition, although not shown in the figure, after the insulating layer 112A and the sacrificial layer 111B are formed, the upper part of the opening 104A is closed by an insulating layer or the like.

[0156] Secondly, if Fig.31 and Fig.32 As shown, for example, the sacrificial layer 130B is removed. This step is performed, for example, by wet etching or the like.

[0157] Secondly, if Fig.33 and Fig.34 As shown, for example, an insulating layer 112 is formed. In this step, a portion of the insulating layer 112A that covers the side surface of the sacrificial layer 111B on one side in the X direction (the side surface on the opening 102A side) is removed through the opening 102A and the opening 130A. In this step, the side surface of the sacrificial layer 111B in the X direction is exposed inside the opening 102A. This step is performed, for example, by wet etching or the like.

[0158] Secondly, if Fig.35 and Fig.36 As shown, for example, through the opening 102A and the opening 130A, a conductive layer 134A is formed on the side surface of the sacrificial layer 111B on one side in the X direction (the side surface on the opening 102A side), the side surface of the insulating member 115 on one side in the X direction (the side surface on the opening 102A side) and both side surfaces in the Y direction, and the upper surface, the lower surface, and the side surface on one side in the X direction (the side surface on the opening 102A side) of the insulating layer 103. This step is performed, for example, by ALD (Atomic Layer Deposition) or the like.

[0159] Secondly, if Fig.37 and Fig.38 As shown, a sacrificial layer 130C made of silicon (Si) or the like is formed inside the opening 102A. The opening 130A is buried by the sacrificial layer 130C, and the opening 102A is not buried by the sacrificial layer 130C. This step is performed by, for example, CVD or the like.

[0160] Secondly, if Fig.39 and Fig.40 As shown, for example, a portion of the sacrifice layer 130C is removed through the opening 102A. In this step, for example, a portion of the conductive layer 134A provided on the side surfaces of the insulating member 115 and the insulating layer 103 in the X direction is exposed. This step is performed, for example, by wet etching or the like.

[0161] Secondly, if Fig.41 and Fig.42 As shown, for example, a conductive layer 134 is formed. In this step, for example, portions of the conductive layer 134A provided on the side surfaces of the insulating member 115 and the insulating layer 103 in the X direction are removed, and the conductive layer 134A is divided in the Y direction and the Z direction. This step is performed, for example, by wet etching or the like.

[0162] Secondly, if Fig.43 and Fig.44 As shown, for example, the sacrificial layer 130C is removed. This step is performed, for example, by wet etching or the like.

[0163] Secondly, if Fig.45 and Fig.46 As shown in the figure, for example, a part of the insulating member 115 and a part of the insulating layer 103 are removed through the opening 102A to form an opening 130D. In the example shown in the figure, the area inside the conductive layer 134 is shown as the opening 130A, and the area outside the conductive layer 134 is shown as the opening 130D. In this step, the insulating member 115 and the insulating layer 103 are removed within a range that does not expose the conductive layer 113 in the opening 130D. This step is performed by, for example, wet etching or the like.

[0164] Secondly, if Fig.47 and Fig.48 As shown, for example, through the opening 130A, the opening 130D, and the opening 102A, the insulating layers 133 and 135, the conductive layers 132 and 136, the conductive layers 131 and 137, and the conductive member 102 are formed on the upper surface, the lower surface, the side surface on one side in the X direction (the side surface on the opening 102A side), and the both side surfaces in the Y direction of the conductive layer 134. This step is performed by, for example, CVD or the like.

[0165] Secondly, if Fig.49 and Fig.50 As shown, for example, the sacrificial layer 111B is removed. This step is performed by, for example, wet etching or the like.

[0166] Secondly, if Fig.51 and Fig.52 As shown, for example, the semiconductor layer 111 is formed inside the opening 111A and the opening 104A. The opening 111A is buried with the semiconductor layer 111. The opening 104A is not buried with the semiconductor layer 111. This step is performed by ALD or the like, for example.

[0167] Secondly, if Fig.53 and Fig.54 As shown, for example, the via wiring 104 is formed inside the opening 104A. This step is performed by, for example, ALD or CVD.

[0168] Secondly, if Fig.55 As shown, for example, an opening 105A is formed at a position corresponding to the insulating member 105. The opening 105A extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction. This step is performed by, for example, RIE or the like.

[0169] Secondly, if Fig.56 and Fig.57 As shown, for example, an opening 120A is formed at a position corresponding to the conductive layer 120. Inside the opening 120A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, the side surface of the conductive layer 113 in the X direction, and the side surface of the insulating member 115 in the X direction are exposed. In this step, for example, the sacrificial layer MLA is selectively removed through the opening 105A. This step is performed, for example, by wet etching or the like.

[0170] Afterwards, if Figure 7 and Figure 8 As shown, for example, the conductive layer 120 is formed inside the opening 120A. This step is performed by, for example, CVD or the like.

[0171] [Effect]

[0172] Secondly, refer to Fig.58 and Fig.59 , the effects of the semiconductor storage device of the first embodiment are described. Fig.58 and Fig.59 This is a schematic XY cross-sectional view for explaining the effects of the semiconductor memory device according to the first embodiment. Fig.58 A partial configuration of a semiconductor memory device according to the first embodiment is shown. Fig.59 A partial configuration of a semiconductor memory device according to a comparative example is shown.

[0173] As described above, in the memory layer ML ( Fig.58), a conductive layer 120 is disposed between two conductive components 102 adjacent in the X direction. Both side surfaces of the conductive layer 120 in the X direction are connected to a plurality of transistor structures 110 arranged in the Y direction.

[0174] On the other hand, Fig.59 As shown, in the memory layer ML0 of the comparative example, two conductive layers 126 separated in the X direction are provided between two conductive components 102 adjacent in the X direction. The two conductive layers 126 are electrically independent of each other and function as different word lines WL. The side surfaces of the two conductive layers 126 on one side in the X direction (on the conductive component 102 side) are respectively connected to a plurality of transistor structures 116 arranged in the Y direction. On the other hand, the side surfaces of the two conductive layers 126 on the other side in the X direction (on the side opposite to the conductive component 102) are not connected to any transistor structure 116.

[0175] Furthermore, the transistor structure 116 includes a semiconductor layer electrically connected to the via wiring 104 and functioning as a channel region of the transistor, and a gate electrode of the transistor facing the semiconductor layer and electrically connected to the conductive layer 126 .

[0176] Here, in the first embodiment, one conductive layer 120 ( Fig.58 ) to replace the two conductive layers 126 ( Fig.59 ). Therefore, in the X direction, the wiring width of approximately one conductive layer 126 can be reduced. In addition, the width of the insulating layer between two conductive layers 126 can also be reduced. Thus, the memory cell array MCA can be highly integrated.

[0177] In the transistor structure 110 of this embodiment, the conductive layer 113 faces the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111 .

[0178] In this configuration, it is possible to suppress electric field interference between the plurality of semiconductor layers 111 arranged in the Z direction. Therefore, even when the memory cell array MCA is highly integrated in the Z direction, the semiconductor layer 111 can be appropriately controlled to be in an on state or an off state, thereby providing a semiconductor memory device that operates appropriately.

[0179] In addition, when the transistor TrC is turned on, a channel is formed on the upper surface, the lower surface, and the two side surfaces in the Y direction of the semiconductor layer 111. Therefore, the on-current of the transistor TrC can be relatively large, thereby achieving high-speed and stable operation.

[0180] In addition, in this embodiment, the conductive layer 120 that functions as the word line WL is provided on the opposite side of the plate line PL relative to the transistor structure 110, and is provided at a position that does not overlap with the transistor structure 110 when viewed from the Z direction. Therefore, the conductive layer 120 and the transistor structure 110 can be formed independently, so that the manufacturing can be relatively easy. In addition, the width of the memory layer ML in the Z direction can be suppressed, and the wiring resistance of the conductive layer 120 can be made relatively small.

[0181] [Second embodiment]

[0182] As reference Figure 55 to Figure 57 As described above, when manufacturing the semiconductor memory device of the first embodiment, the opening 105A is formed to penetrate the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction, and the sacrificial layers MLA are removed through the opening 105A to form the conductive layer 120. After the conductive layer 120 is formed, the insulating member 105 is formed inside the opening 105A.

[0183] Here, the position, shape, size, etc. of the opening 105A can be adjusted appropriately. Therefore, the position, shape, size, etc. of the structure corresponding to the insulating member 105 can also be adjusted appropriately. Hereinafter, other structural examples of the insulating member 105 will be described as the second to fourth embodiments.

[0184] First, refer to Fig.60 , a semiconductor storage device according to a second embodiment is described. Fig.60 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the first embodiment, and the description thereof will be omitted.

[0185] The semiconductor memory device according to the second embodiment has basically the same configuration as the semiconductor memory device according to the first embodiment.

[0186] However, the semiconductor memory device of the second embodiment includes a plurality of insulating members 205 instead of the plurality of insulating members 105. The insulating members 205 are basically configured in the same manner as the insulating members 105. However, the central positions of the insulating members 205 in the X direction are respectively provided on one side in the X direction (the negative side in the X direction in the example shown in the figure) with respect to the central positions of the conductive layer 120 in the X direction.

[0187] In addition, as referenced Figure 5 As described above, the outer peripheral surface of the insulating member 105 of the first embodiment is surrounded by the conductive layer 120 over the entire circumference and is connected to the conductive layer 120. Fig.60 In the example, the outer peripheral surface of the insulating component 205 is surrounded by the conductive layer 120 and the insulating component 115 and is connected to the conductive layer 120 and the insulating component 115 .

[0188] [Third Embodiment]

[0189] Secondly, refer to Fig.61 , a semiconductor storage device according to a third embodiment is described. Fig.61 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the first embodiment, and the description thereof will be omitted.

[0190] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0191] However, the semiconductor memory device of the third embodiment includes a plurality of insulating members 305 instead of the plurality of insulating members 105. The insulating member 305 is basically configured in the same manner as the insulating member 105. However, the central positions of a part of the insulating member 305 (in the example shown in the figure, the odd-numbered insulating members 305 counted from the positive side in the Y direction) in the X direction are respectively arranged on one side in the X direction (for example, the positive side in the X direction) with respect to the central position of the conductive layer 120 in the X direction. In addition, the central positions of another part of the insulating member 305 (in the example shown in the figure, the even-numbered insulating members 305 counted from the positive side in the Y direction) in the X direction are respectively arranged on the other side in the X direction (for example, the negative side in the X direction) with respect to the central position of the conductive layer 120 in the X direction.

[0192] In addition, Fig.61 In the example, the outer peripheral surface of the insulating component 305 is surrounded by the conductive layer 120 and the insulating component 115 and is connected to the conductive layer 120 and the insulating component 115 .

[0193] [Fourth embodiment]

[0194] Secondly, refer to Fig.62 , a semiconductor storage device according to a fourth embodiment is described. Fig.62 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the first embodiment, and the description thereof will be omitted.

[0195] The semiconductor memory device according to the fourth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0196] However, the semiconductor memory device of the fourth embodiment includes a plurality of insulating members 405 instead of the plurality of insulating members 105. The insulating members 405 are basically configured in the same manner as the insulating members 105. However, the number of the plurality of insulating members 105 arranged in the Y direction is the same as the number of the plurality of insulating members 115 arranged in the Y direction. On the other hand, the number of the plurality of insulating members 405 arranged in the Y direction is less than the number of the plurality of insulating members 115 arranged in the Y direction.

[0197] In addition, the semiconductor memory device of the fourth embodiment includes a conductive layer 420 instead of the conductive layer 120. The conductive layer 420 includes a plurality of portions 421 and portions 422 alternately arranged in the Y direction. The portion 421 is configured in the same manner as the conductive layer 120. The portion 422 is provided at a position corresponding to the insulating member 405. Unlike the portion 421, the portion 422 is not connected to any conductive layer 113. The width of the portion 422 in the X direction is greater than the width of the portion 421 in the X direction. The width of the portion 422 in the Y direction is smaller than the width of the portion 421 in the Y direction. The widths of the portion 422 in the X direction and the Y direction are greater than the widths of the insulating member 405 in the X direction and the Y direction, respectively.

[0198] Here, the conductive layer 420 of the fourth embodiment includes a portion 421 connected to the transistor structure 110 and a portion 422 provided with the insulating member 405. According to this structure, since a structure corresponding to the insulating member 105 is not formed in the portion 421, the width of the portion 421 in the X direction can be reduced, thereby further realizing high integration of the memory cell array MCA.

[0199] In addition, Fig.62 In the example, the outer peripheral surface of the insulating component 405 is surrounded by the conductive layer 420 over the entire circumference and is connected to the conductive layer 420.

[0200] [Fifth embodiment]

[0201] Secondly, refer to Fig.63 , a semiconductor storage device according to a fifth embodiment is described. Fig.63 1 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the first embodiment, and the description thereof will be omitted.

[0202] The semiconductor memory device according to the fifth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0203] However, the semiconductor memory device according to the fifth embodiment includes a wiring layer M5 instead of the wiring layers M0 and M1.

[0204] The wiring layer M5 includes a plurality of wirings m5. The plurality of wirings m5 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or copper (Cu). In addition, at least a portion of the plurality of wirings m5 is used as a global bit line GBL ( Figure 1 ) to perform its function.

[0205] Here, as reference Figure 6 As described above, the plurality of global bit lines GBL in the first embodiment extend in the X direction and are electrically connected to the plurality of via wirings 104 whose positions are substantially aligned in the Y direction.

[0206] On the other hand, Fig.63 As shown, the plurality of global bit lines GBL of the fifth embodiment extend in oblique directions (directions not coinciding with the Y direction and the X direction in the XY plane and the XY cross section) and are electrically connected to a plurality of via wirings 104 at different positions in the Y direction.

[0207] In the fifth embodiment, both global bit lines GBLo and GBLe are provided at positions overlapping with corresponding bit lines BL when viewed from the Z direction. These global bit lines GBLo and GBLe are directly in contact with through-hole contact electrodes c0o and c0e on the bottom surface.

[0208] According to such a configuration, the configuration corresponding to the wiring layer M0 and the plurality of through-hole contact electrodes c1o and c1e can be omitted. Therefore, the manufacturing cost can be reduced compared to the first embodiment.

[0209] In addition, the semiconductor storage device of the fifth embodiment may include a plurality of insulating members 205 ( Fig.60 ), multiple insulating components 305 ( Fig.61 ) or multiple insulating components 405 ( Fig.62 ) instead of the plurality of insulating members 105. In addition, when the semiconductor memory device of the fifth embodiment includes a plurality of insulating members 405, the semiconductor memory device of the fifth embodiment may include a conductive layer 420 ( Fig.62 ) to replace the conductive layer 120.

[0210] [Sixth embodiment]

[0211] Secondly, refer to Fig.64 and Fig.65 , a semiconductor storage device according to a sixth embodiment is described. Fig.64 It is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device. Fig.65 1 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the third embodiment, and the description thereof will be omitted.

[0212] The semiconductor memory device according to the sixth embodiment is basically configured in the same manner as the semiconductor memory device according to the third embodiment.

[0213] Here, as reference Figure 5 As described above, in the semiconductor memory device of the first embodiment, a plurality of through-hole wirings 104 are arranged between two conductive members 102 adjacent in the X direction in two columns at different positions in the X direction. When focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction with respect to the conductive layer 120 are substantially consistent with the positions in the Y direction of any of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction with respect to the conductive layer 120.

[0214] like Fig.64 As shown in FIG. 1 , in the semiconductor memory device of the sixth embodiment, a plurality of through-hole wirings 104 are also arranged between two conductive members 102 adjacent in the X direction in two columns at different positions in the X direction. However, when focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive layer 120 are not consistent with the positions in the Y direction of any of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive layer 120.

[0215] For example, in Fig.64 In the example, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive layer 120 are approximately consistent with the middle positions of any two adjacent through-hole wirings 104 in the Y direction included in the column provided on the other side in the X direction relative to the conductive layer 120. The positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive layer 120 are respectively between the positions in the Y direction of any two adjacent through-hole wirings 104 in the Y direction included in the column provided on the other side in the X direction relative to the conductive layer 120.

[0216] In addition, the semiconductor memory device according to the sixth embodiment does not include the wiring layer M0.

[0217] In the sixth embodiment, Fig.65 As shown, the global bit lines GBLo and GBLe in the wiring layer M1 are arranged at positions overlapping with the corresponding bit lines BL when viewed from the Z direction. These global bit lines GBLo and GBLe are directly connected to the through-hole contact electrodes c0o and c0e on the lower surface.

[0218] According to such a configuration, the configuration corresponding to the wiring layer M0 and the plurality of through-hole contact electrodes c1o and c1e can be omitted. Therefore, the manufacturing cost can be reduced compared to the first embodiment.

[0219] [Seventh embodiment]

[0220] Secondly, refer to Fig.66 , a semiconductor storage device according to a seventh embodiment is described. Fig.66 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are attached to the same structures as those in the sixth embodiment, and the description thereof will be omitted.

[0221] The semiconductor memory device according to the seventh embodiment is basically configured in the same manner as the semiconductor memory device according to the sixth embodiment.

[0222] However, the semiconductor storage device of the seventh embodiment has a reference Fig.62 The plurality of insulating members 405 described above are used instead of the plurality of insulating members 305. The number of the plurality of insulating members 405 arranged in the Y direction is smaller than the number of the plurality of insulating members 115 arranged in the Y direction.

[0223] In addition, the semiconductor storage device of the seventh embodiment includes a reference Fig.62 Conductive layer 420 is illustrated instead of conductive layer 120 .

[0224] In addition, Fig.66 In the example, the outer peripheral surface of the insulating component 405 is surrounded by the conductive layer 420 over the entire circumference and is connected to the conductive layer 420.

[0225] [Eighth embodiment]

[0226] Secondly, refer to Fig.67 and Fig.68 , a semiconductor storage device according to an eighth embodiment is described. Fig.67 It is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device. Fig.68 1 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the third embodiment, and the description thereof will be omitted.

[0227] The semiconductor memory device according to the eighth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0228] Here, as reference Figure 5As described, in the semiconductor memory device of the first embodiment, a plurality of through-hole wirings 104 are arranged in two columns with different positions in the X direction between two conductive layers 120 adjacent in the X direction. When focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction with respect to the conductive member 102 are substantially consistent with the positions in the Y direction of any of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction with respect to the conductive member 102.

[0229] like Fig.67 As shown, in the semiconductor memory device of the eighth embodiment, a plurality of through-hole wirings 104 are also arranged in two columns with different positions in the X direction between two conductive layers 120 adjacent in the X direction. However, when focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive member 102 are not consistent with the positions in the Y direction of any of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive member 102.

[0230] For example, in Fig.67 In the example, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive component 102 are approximately consistent with the middle positions of any two adjacent in the Y direction among the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive component 102. The positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive component 102 are respectively between the positions in the Y direction of any two adjacent in the Y direction among the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive component 102.

[0231] In addition, if Fig.68 As shown, in the eighth embodiment, both global bit lines GBLo and GBLe are arranged at positions that do not overlap with the corresponding plurality of bit lines BL when viewed from the Z direction. Fig.68 In the example, the width of the wiring m0e in the Y direction is substantially the same as the width of the wiring m0o in the Y direction.

[0232] In addition, the semiconductor storage device of the eighth embodiment may include a plurality of insulating members 205 ( Fig.60 ), multiple insulating components 305 ( Fig.61 ) or multiple insulating components 405 ( Fig.62) instead of the plurality of insulating members 105. In addition, when the semiconductor memory device of the eighth embodiment includes a plurality of insulating members 405, the semiconductor memory device of the eighth embodiment may include a conductive layer 420 ( Fig.62 ) to replace the conductive layer 120.

[0233] [Ninth embodiment]

[0234] Secondly, refer to Fig.69 , a semiconductor storage device according to a ninth embodiment is described. Fig.69 1 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the first embodiment, and the description thereof will be omitted.

[0235] The semiconductor memory device according to the ninth embodiment is basically configured in the same manner as the semiconductor memory device according to the eighth embodiment.

[0236] However, the semiconductor storage device of the ninth embodiment has a reference Fig.63 The wiring layer M5 described above replaces the wiring layers M0 and M1.

[0237] In the ninth embodiment, both global bit lines GBLo and GBLe are provided at positions overlapping with corresponding bit lines BL when viewed from the Z direction. These global bit lines GBLo and GBLe are directly connected to through-hole contact electrodes c0o and c0e on the lower surface.

[0238] According to such a configuration, the configuration corresponding to the wiring layer M0 and the plurality of through-hole contact electrodes c1o and c1e can be omitted. Therefore, the manufacturing cost can be reduced compared to the first embodiment.

[0239] In addition, the semiconductor storage device of the ninth embodiment may include a plurality of insulating members 205 ( Fig.60 ), multiple insulating components 305 ( Fig.61 ) or multiple insulating components 405 ( Fig.62 ) instead of the plurality of insulating members 105. In addition, when the semiconductor memory device of the ninth embodiment includes a plurality of insulating members 405, the semiconductor memory device of the ninth embodiment may include a conductive layer 420 ( Fig.62 ) to replace the conductive layer 120.

[0240] [10th embodiment]

[0241] Secondly, refer to Fig.70 and Fig.71 , a semiconductor storage device according to a tenth embodiment is described. Fig.70 It is a schematic XY cross-sectional view showing a partial structure of the semiconductor memory device. Fig.711 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are attached to the same structures as those in the sixth embodiment, and the description thereof will be omitted.

[0242] The semiconductor memory device according to the tenth embodiment is basically configured in the same manner as the semiconductor memory device according to the sixth embodiment.

[0243] Here, if Fig.64 As shown, in the semiconductor memory device of the sixth embodiment, a plurality of through-hole wirings 104 are arranged in two columns with different positions in the X direction between two conductive layers 120 adjacent in the X direction. When focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction with respect to the conductive member 102 are substantially consistent with the positions in the Y direction of any of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction with respect to the conductive member 102.

[0244] like Fig.70 As shown, in the semiconductor memory device of the tenth embodiment, a plurality of through-hole wirings 104 are also arranged in two columns with different positions in the X direction between two conductive layers 120 adjacent in the X direction. However, when focusing on the plurality of through-hole wirings 104, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive member 102 are not consistent with the positions in the Y direction of any of the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive member 102.

[0245] For example, in Fig.70 In the example, the positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive component 102 are approximately consistent with the middle positions of any two adjacent in the Y direction among the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive component 102. The positions in the Y direction of the plurality of through-hole wirings 104 included in the column provided on one side in the X direction relative to the conductive component 102 are respectively between the positions in the Y direction of any two adjacent in the Y direction among the plurality of through-hole wirings 104 included in the column provided on the other side in the X direction relative to the conductive component 102.

[0246] Furthermore, the semiconductor memory device according to the tenth embodiment does not include the wiring layer M0.

[0247] In the tenth embodiment, if Fig.71As shown, the global bit lines GBLo and GBLe in the wiring layer M1 are arranged at positions overlapping with the corresponding bit lines BL when viewed from the Z direction. These global bit lines GBLo and GBLe are directly connected to the through-hole contact electrodes c0o and c0e on the lower surface.

[0248] According to such a configuration, the configuration corresponding to the wiring layer M0 and the plurality of through-hole contact electrodes c1o and c1e can be omitted. Therefore, the manufacturing cost can be reduced compared to the first embodiment.

[0249] [11th embodiment]

[0250] Secondly, refer to Figure 72 to Figure 74 , a semiconductor memory device according to an eleventh embodiment will be described. In the following description, the same reference numerals are given to the same components as those in the first embodiment, and description thereof will be omitted.

[0251] [Circuit configuration]

[0252] Fig.72 This is a schematic circuit diagram showing a partial structure of the semiconductor memory device.

[0253] The semiconductor memory device according to the eleventh embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0254] But, if Fig.72 As shown in FIG. 1 , the memory cell array MCA11 according to the eleventh embodiment includes a transistor layer TL in addition to the configuration included in the memory cell array MCA according to the first embodiment.

[0255] The transistor layer TL includes a plurality of bit line selection lines LB0 to LB2 and a plurality of transistors TrB connected to the plurality of bit line selection lines LB0 to LB2. The source electrode of the transistor TrB is connected to the global bit line GBL. The drain electrode of the transistor TrB is connected to the bit line BL. That is, in the present embodiment, the plurality of bit lines BL are electrically connected to the global bit line GBL via the transistor TrB, respectively. The gate electrode of the transistor TrB is connected to any one of the bit line selection lines LB0 to LB2.

[0256] In addition, the transistor layer TL includes a plurality of transistors TrTa and TrTb (hereinafter sometimes referred to as "transistor TrT") provided corresponding to the plurality of bit line selection lines LB0 to LB2. The drain electrode of the transistor TrT is connected to any one of the bit line selection lines LB0 to LB2. The source electrode of the transistor TrT is connected to the word line selection line LW. The gate electrode of the transistor TrT is connected to the wiring LTa and LTb (hereinafter sometimes referred to as "wiring LT"), respectively.

[0257] Furthermore, the wiring LTa is commonly connected to all transistors TrTa. Similarly, the wiring LTb is commonly connected to all transistors TrTb.

[0258] [structure]

[0259] Fig.73 It is a schematic perspective view showing a partial structure of the semiconductor memory device. Fig.74 It is a schematic plan view showing a partial structure of the semiconductor memory device.

[0260] like Fig.73 As shown, the memory cell array MCA11 includes a plurality of memory layers ML and a transistor layer TL provided between wiring layers M0.

[0261] The transistor layer TL is basically configured in the same manner as the memory layer ML.

[0262] However, the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the transistor layer TL function as the channel region, the gate insulating film, and the gate electrode of the transistor TrB, respectively. In addition, the conductive layer 120 in the transistor layer TL functions as the bit line selection lines LB0 to LB2. In addition, the conductive layer 134 in the transistor layer TL functions as the source electrode of the transistor TrB.

[0263] In the eleventh embodiment, the via contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0264] In addition, the semiconductor storage device of the eleventh embodiment may include a plurality of insulating members 205 ( Fig.60 ), multiple insulating components 305 ( Fig.61 ) or multiple insulating components 405 ( Fig.62 ) instead of the plurality of insulating members 105. In addition, when the semiconductor memory device of the 11th embodiment includes a plurality of insulating members 405, the semiconductor memory device of the 11th embodiment may include a conductive layer 420 ( Fig.62 ) to replace the conductive layer 120.

[0265] [12th embodiment]

[0266] Secondly, refer to Fig.75 , a semiconductor storage device according to a twelfth embodiment is described. Fig.75 1 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are attached to the same structures as those in the sixth embodiment, and the description thereof will be omitted.

[0267] The semiconductor memory device according to the twelfth embodiment is basically configured in the same manner as the semiconductor memory device according to the sixth embodiment.

[0268] However, the memory cell array MCA12 according to the twelfth embodiment further includes a transistor layer TL in addition to the configuration included in the memory cell array MCA according to the sixth embodiment.

[0269] In the twelfth embodiment, similarly to the eleventh embodiment, the through-hole contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0270] [13th embodiment]

[0271] Secondly, refer to Fig.76 , a semiconductor storage device according to a thirteenth embodiment is described. Fig.76 1 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are attached to the same structures as those in the eighth embodiment, and the description thereof is omitted.

[0272] The semiconductor memory device according to the thirteenth embodiment is basically configured in the same manner as the semiconductor memory device according to the eighth embodiment.

[0273] However, the memory cell array MCA13 according to the thirteenth embodiment further includes a transistor layer TL in addition to the configuration included in the memory cell array MCA according to the eighth embodiment.

[0274] In the thirteenth embodiment, similarly to the eleventh embodiment, the through-hole contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0275] In addition, the semiconductor storage device of the thirteenth embodiment may include a plurality of insulating members 205 ( Fig.60 ), multiple insulating components 305 ( Fig.61 ) or multiple insulating components 405 ( Fig.62 ) instead of the plurality of insulating members 105. In addition, when the semiconductor memory device of the thirteenth embodiment includes a plurality of insulating members 405, the semiconductor memory device of the thirteenth embodiment may include a conductive layer 420 ( Fig.62 ) to replace the conductive layer 120.

[0276] [14th embodiment]

[0277] Secondly, refer to Fig.77 , a semiconductor storage device according to a fourteenth embodiment is described. Fig.77 10 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are attached to the same structures as those in the tenth embodiment, and the description thereof will be omitted.

[0278] The semiconductor memory device according to the fourteenth embodiment is basically configured in the same manner as the semiconductor memory device according to the tenth embodiment.

[0279] However, the memory cell array MCA14 according to the fourteenth embodiment further includes a transistor layer TL in addition to the configuration included in the memory cell array MCA according to the tenth embodiment.

[0280] In the fourteenth embodiment, similarly to the eleventh embodiment, the through-hole contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0281] [15th embodiment]

[0282] Secondly, refer to Fig.78 , a semiconductor storage device according to a fifteenth embodiment is described. Fig.78 1 is a schematic plan view showing a part of the structure of the semiconductor memory device. In the following description, the same reference numerals are given to the same structures as those in the first embodiment, and the description thereof will be omitted.

[0283] The semiconductor memory device according to the fifteenth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0284] But, if Fig.78 As shown, in the fifteenth embodiment, a gap G is provided between two conductive layers 120 adjacent to each other in the Z direction.

[0285] The gap G can be formed by, for example, wet etching or the like after performing the step of forming the conductive layer 120 and before performing the step of forming the insulating member 105 .

[0286] According to such a configuration, the electrostatic capacitance between two conductive layers 120 adjacent to each other in the Z direction can be reduced, thereby achieving faster operation.

[0287] In the semiconductor storage devices of the second to fourteenth embodiments, similarly to the semiconductor storage device of the fifteenth embodiment, a gap G may be provided between two conductive layers 120 adjacent to each other in the Z direction.

[0288] [Other embodiments]

[0289] The semiconductor memory devices according to the first to fifteenth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and specific configurations and the like may be appropriately adjusted.

[0290] For example, in the first to fifteenth embodiments, the wiring layers M0 and M1 are disposed above the memory cell arrays MCA, MCA11, MCA12, MCA13, and MCA14 (hereinafter referred to as “memory cell arrays MCA, etc.”) (disposed on the opposite side of the semiconductor substrate Sub relative to the memory cell arrays MCA, etc.). However, the wiring layers M0 and M1 may be disposed below the memory cell arrays MCA, etc. (disposed on the semiconductor substrate Sub side relative to the memory cell arrays MCA, etc.).

[0291] In the eleventh to fourteenth embodiments, when the wiring layers M0 and M1 are provided below the memory cell array MCA or the like, the transistor layer TL may be provided below the plurality of memory layers ML (between the plurality of memory layers ML and the wiring layer M0).

[0292] In the semiconductor memory devices of the first to fifteenth embodiments, the via wiring 104 functioning as a bit line includes a conductive oxide such as indium tin oxide (ITO). However, such a conductive oxide may be included in the transistor structure 110 instead of the via wiring 104 extending in the Z direction. In addition, the via wiring 104 and the transistor structure 110 may include other materials.

[0293] In the semiconductor memory devices of the first to fifteenth embodiments, the conductive layer 113 functioning as the gate electrode of the transistor TrC may face only one of the upper and lower surfaces of the semiconductor layer 111 functioning as the channel region of the transistor TrC.

[0294] In the semiconductor memory devices of the first to fifteenth embodiments, the semiconductor layer functioning as the channel region of the transistor TrC may face the upper and lower surfaces of the conductive layer functioning as the gate electrode of the transistor TrC.

[0295] In addition, in the above description, the capacitor CpC is used as an example of a memory unit connected to the transistor structure 110. However, the memory unit may not be the capacitor CpC. For example, the memory unit may include ferroelectrics, ferromagnets, chalcogenide materials such as GeSbTe, or other materials, and the properties of these materials are used to record data. For example, in any of the structures described above, the insulating layer between the electrodes forming the capacitor CpC may include any of these materials.

[0296] Furthermore, the methods for manufacturing the semiconductor memory device according to the first to fifteenth embodiments may be adjusted as appropriate. For example, the order of any two of the steps may be switched, or any two of the steps may be performed simultaneously.

[0297] [other]

[0298] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the claims and the scope equivalent thereto.

[0299] [Explanation of symbols]

[0300] Sub:Semiconductor Substrate

[0301] ML: Memory Layer

[0302] BL: Bit Line

[0303] WL: Word Line

[0304] PL: Plate Line

[0305] TrC: Transistor

[0306] CpC:Capacitor

[0307] 102: Conductive layer

[0308] 104: Through-hole wiring

[0309] 110: Transistor Construction

[0310] 111: Semiconductor layer

[0311] 112: Insulation layer

[0312] 113: Conductive layer

[0313] 120: Conductive layer

[0314] 130:Capacitor structure.

Claims

1. A semiconductor storage device comprising: substrate; A plurality of memory layers arranged in a first direction intersecting with the surface of the substrate; A first through-hole wiring extending in the first direction; a second through-hole wiring having a position different from that of the first through-hole wiring in a second direction intersecting the first direction and extending in the first direction; The plurality of memory layers respectively include: a first wiring provided between the first through-hole wiring and the second through-hole wiring and extending in a third direction intersecting the first direction and the second direction; a first semiconductor layer electrically connected to the first through-hole wiring; a first gate electrode facing the first semiconductor layer and electrically connected to the first wiring; a first memory portion provided on the opposite side of the first wiring with respect to the first semiconductor layer in the second direction and electrically connected to the first semiconductor layer; a second semiconductor layer electrically connected to the second through-hole wiring; a second gate electrode facing the second semiconductor layer and electrically connected to the first wiring; as well as The second memory portion is provided on the opposite side of the first wiring with respect to the second semiconductor layer in the second direction and is electrically connected to the second semiconductor layer.

2. The semiconductor memory device according to claim 1, wherein The first gate electrode faces the surfaces of the first semiconductor layer on one side and the other side in the first direction, and the surfaces of the first semiconductor layer on one side and the other side in the third direction.

3. The semiconductor memory device according to claim 1, wherein Gaps are provided between the plurality of first wirings arranged in the first direction corresponding to the plurality of memory layers.

4. The semiconductor memory device according to claim 1, wherein The first memory unit comprises: a first electrode electrically connected to the first semiconductor layer; a second electrode, facing the first electrode; and The insulating layer is provided between the first electrode and the second electrode.

5. The semiconductor memory device according to claim 1, wherein The first semiconductor layer includes at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

6. A semiconductor storage device comprising: substrate; A plurality of memory layers arranged in a first direction intersecting with the surface of the substrate; A plurality of through-hole wirings are arranged in a first column and a second column at different positions in a second direction, the second direction being a direction intersecting the first direction; The first row includes a plurality of first through-hole wirings, the plurality of first through-hole wirings are arranged in a third direction intersecting the first direction and the second direction, and extend in the first direction. The second row includes a plurality of second through-hole wirings, the plurality of second through-hole wirings are arranged in the third direction and extend in the first direction, The plurality of memory layers respectively include: a first wiring, provided between the plurality of first through-hole wirings and the plurality of second through-hole wirings, and extending in the third direction; A plurality of first semiconductor layers electrically connected to the plurality of first through-hole wirings; a plurality of first gate electrodes facing the plurality of first semiconductor layers and electrically connected to the first wiring; a plurality of first memory portions provided on the opposite side of the first wiring with respect to the plurality of first semiconductor layers in the second direction and electrically connected to the plurality of first semiconductor layers; a plurality of second semiconductor layers electrically connected to the plurality of second through-hole wirings; a plurality of second gate electrodes facing the plurality of second semiconductor layers and electrically connected to the first wiring; and The plurality of second memory portions are provided on the opposite side of the first wiring with respect to the plurality of second semiconductor layers in the second direction and are electrically connected to the plurality of second semiconductor layers.

7. The semiconductor memory device according to claim 6, wherein In a first cross section extending in the second direction and the third direction and including the first wiring, the semiconductor memory device further includes a plurality of first insulating members arranged in the third direction along the first wiring.

8. The semiconductor memory device according to claim 7, wherein It further comprises a plurality of second insulating members arranged alternately with the plurality of first semiconductor layers in the third direction, wherein positions of the plurality of first insulating members in the third direction correspond to positions of any of the plurality of second insulating members in the third direction.

9. The semiconductor memory device according to claim 7, wherein The center positions of the plurality of first insulating members in the second direction are substantially aligned with the center positions of the first wiring in the second direction.

10. The semiconductor memory device according to claim 7, wherein The plurality of first insulating members are provided on one side in the second direction with respect to a center position of the first wiring in the second direction.

11. The semiconductor memory device according to claim 7, wherein A part of the plurality of first insulating members is provided on one side in the second direction relative to a central position of the first wiring in the second direction. Another portion of the plurality of first insulating members is provided on the other side in the second direction with respect to the center position of the first wiring in the second direction.

12. The semiconductor memory device according to claim 7, wherein Further included are a plurality of second insulating members arranged alternately with the plurality of first semiconductor layers in the third direction, wherein the number of the plurality of first insulating members arranged in the third direction is smaller than the number of the plurality of second insulating members arranged in the third direction.

13. The semiconductor memory device according to claim 6, wherein comprising a first wiring layer provided on one side in the first direction with respect to the plurality of memory layers, and a second wiring layer provided between the plurality of memory layers and the first wiring layer, The first wiring layer includes a plurality of second wirings, and the plurality of second wirings are arranged in the third direction and extend in the second direction. When the second wiring layer is observed from the first direction, the position where any one of the plurality of first through-hole wirings or any one of the plurality of second through-hole wirings overlaps with any one of the plurality of second wirings, includes a plurality of third wirings extending in the third direction.

14. The semiconductor memory device according to claim 6, wherein A first wiring layer is provided, the first wiring layer being provided on one side in the first direction with respect to the plurality of memory layers, The first wiring layer includes a plurality of second wirings, Parts of the plurality of second wirings are respectively provided at positions overlapping with any one of the plurality of first through-hole wirings when viewed from the first direction. The other parts of the plurality of second wirings are respectively provided at positions overlapping with any one of the plurality of second through-hole wirings when viewed from the first direction.

15. The semiconductor memory device according to claim 14, wherein The plurality of second wirings are arranged in the third direction and extend in the second direction.

16. The semiconductor memory device according to claim 14, wherein In a second cross section extending in the second direction and the third direction and including the plurality of second wirings, the plurality of second wirings extend in a direction intersecting the second direction and the third direction.

17. The semiconductor memory device according to claim 6, wherein The positions of the plurality of first through-hole wirings in the third direction are respectively substantially consistent with the position of any one of the plurality of second through-hole wirings in the third direction.

18. The semiconductor memory device according to claim 6, wherein The positions of the plurality of first through-hole wirings in the third direction do not coincide with the positions of any of the plurality of second through-hole wirings in the third direction.

19. The semiconductor memory device according to claim 6, further comprising: a fourth wiring extending in the first direction and the third direction and connected to the plurality of first memory units; and a plurality of third through-hole wirings, which are provided on the opposite side of the plurality of first through-hole wirings in the second direction relative to the fourth wirings, are arranged in the third direction, and extend in the first direction; The plurality of memory layers further include: a fifth wiring provided on the opposite side of the first wiring in the second direction with respect to the plurality of third through-hole wirings and extending in the third direction; A plurality of third semiconductor layers electrically connected to the plurality of third through-hole wirings; a plurality of third gate electrodes facing the plurality of third semiconductor layers and electrically connected to the fifth wiring; and The plurality of third memory portions are provided between the plurality of third semiconductor layers and the fourth wiring, and are electrically connected to the plurality of third semiconductor layers and the fourth wiring.

20. The semiconductor memory device according to claim 19, wherein The positions of the plurality of first through-hole wirings in the third direction are respectively substantially consistent with the position of any one of the plurality of third through-hole wirings in the third direction.

21. The semiconductor memory device according to claim 19, wherein The positions of the plurality of first through-hole wirings in the third direction do not coincide with the positions of any of the plurality of third through-hole wirings in the third direction.

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