A silicon epitaxial wafer without cracks and edge collapse for power devices and a preparation method thereof

Abstract

The invention relates to a silicon epitaxial wafer without cracks and broken edges for power devices and a preparation method thereof; the method comprises the following steps: cleaning a silicon epitaxial furnace reaction chamber and a graphite base inside the silicon epitaxial furnace, introducing trichlorosilane gas into the silicon epitaxial furnace reaction chamber with hydrogen as a carrier gas, and growing a polysilicon coating layer on the graphite base; cooling the silicon epitaxial furnace, placing a silicon substrate sheet into a sheet pit of the graphite base, introducing hydrogen, heating the silicon epitaxial furnace, maintaining the temperature, introducing trichlorosilane gas into the silicon epitaxial furnace with hydrogen as a carrier gas, and then heating the silicon epitaxial furnace. A silicon epitaxial layer is grown on a silicon substrate. When the thickness of the silicon epitaxial layer reaches 25-30 μm, the temperature is lowered to obtain a silicon epitaxial wafer. By proposing a method for preparing a silicon epitaxial wafer without cracks and edge collapse for power devices, the technical problem that the 25-30 μm thick silicon epitaxial wafer in the prior art cannot be continuously mass-produced due to the long high-temperature growth time and the easy adhesion or collision of the edge with the graphite base, which significantly increases the probability of cracks or edge collapse defects.

Description

Technical Field

[0001] The invention relates to the technical field of silicon epitaxial wafer preparation, in particular to a silicon epitaxial wafer without cracks or edge collapse for power devices and a preparation method thereof. Background Art

[0002] Silicon epitaxial wafer refers to a silicon epitaxial layer prepared on the polished surface of a silicon substrate using the chemical vapor deposition (CVD) method. The parameters such as doping type, resistivity, thickness, uniformity, etc. need to meet the use requirements of the device. For 250V-300V medium and high voltage power devices, the target silicon epitaxial layer thickness requirement is 25-30μm, which belongs to thick silicon epitaxial wafers. Because the device application field has strict requirements on the uniformity and consistency of the silicon epitaxial wafers, this type of silicon epitaxial wafer needs to be grown using a flat-plate single-wafer silicon epitaxial furnace equipment, which is 8-10 times the growth time of conventional 5μm thin silicon epitaxial wafers. It faces greater difficulty in controlling mechanical and thermal stresses, and is prone to the risk of material deformation such as warping and bending. In addition, due to the long high-temperature growth time, the edges of such 25-30μm thick silicon epitaxial wafers are prone to adhesion or collision with the graphite base, and the probability of cracks or edge collapse defects will also increase significantly. Because the appearance of a crack or edge collapse defect will determine that the silicon epitaxial wafer is unqualified, it is difficult for the industry to continuously mass-produce thick silicon epitaxial wafers, seriously affecting the industrialized continuous production and delivery capabilities of silicon epitaxial wafers. In the industrial field, the key technical problem of solving the crack and edge collapse problems of silicon epitaxial wafers in a stable, effective and low-cost manner for growing silicon epitaxial wafers with a target silicon epitaxial layer thickness of 25-30μm in a flat-plate single-wafer silicon epitaxial furnace is becoming increasingly important.

[0003] The traditional process methods used to solve the problems of cracks and edge collapse of silicon epitaxial wafers are: 1) The extremely thick epitaxial wafers for high-voltage power devices disclosed in ZL201310240216.0 use a two-step heating method to significantly extend the heating time, reduce the deformation of the silicon epitaxial wafer, and realize the preparation method of silicon epitaxial wafers; 2) The preparation method of 8-inch silicon epitaxial wafers for IGBT disclosed in ZL 202410108386.1 grows silicon epitaxial wafers by variable temperature and variable flow, first using high temperature and large flow for rapid growth, then using low temperature and large flow for medium speed growth, and then using low temperature and small flow for speed growth to reduce the risk of cracks; 3) The graphite base for silicon epitaxy disclosed in ZL202220023958.2 has a plurality of exhaust holes on the bottom of the groove, which can be completely bonded to the substrate after thermal expansion and deformation, ensuring that the substrate is heated evenly. However, the above patent has the defect of complicated process steps. The graphite base with exhaust holes designed on the bottom has a market price 2-3 times that of the non-porous graphite base due to the difficulty in processing, which ultimately causes a serious increase in the cost of silicon epitaxial wafer preparation, which is not conducive to the promotion and use of silicon epitaxial wafers.

[0004] Therefore, in view of the above problems, the present invention urgently needs to provide a silicon epitaxial wafer without cracks and edge collapse for power devices and a preparation method thereof. Summary of the invention

[0005] The object of the present invention is to provide a silicon epitaxial wafer without cracks and edge collapse for power devices and a preparation method thereof, and to solve the technical problem in the prior art that the silicon epitaxial wafer with a thickness of 25-30 μm is prone to adhesion or collision with the graphite base due to the long high-temperature growth time, and the probability of cracks or edge collapse defects will also be significantly increased, and thick silicon epitaxial wafers cannot be continuously mass-produced.

[0006] The present invention provides a method for preparing a crack-free and edge-collapsed silicon epitaxial wafer for a power device, wherein the thickness of the silicon epitaxial layer of the silicon epitaxial wafer is 25-30 μm, and the preparation method comprises the following steps:

[0007] S1) cleaning the silicon epitaxial furnace reaction chamber and the graphite base inside it;

[0008] S2) introducing trichlorosilane gas into the reaction chamber of the silicon epitaxial furnace using hydrogen as a carrier gas to grow a polysilicon coating layer on the graphite susceptor, the flow rate of the trichlorosilane gas is 10-12 g / min, the growth time is 2-3 min, and the thickness of the polysilicon coating layer reaches 5-6 μm;

[0009] S3) The silicon epitaxial furnace is cooled down, a silicon substrate is placed into the sheet pit of the graphite base, the graphite base is rotated, hydrogen is introduced, and air is exhausted. The silicon epitaxial furnace is heated up to 1130-1150°C, and trichlorosilane gas is introduced into the silicon epitaxial furnace using hydrogen as a carrier. The flow rate of trichlorosilane gas is set to 2-4g / min; the growth rate is set to 1-2μm / min. When the thickness of the silicon epitaxial layer reaches the target, the temperature is lowered to obtain a silicon epitaxial wafer.

[0010] Preferably, in step S3, when trichlorosilane gas is introduced into the silicon epitaxial furnace using hydrogen as a carrier, the flow rate of hydrogen is set to 45-50 L / min.

[0011] Preferably, the rotation rate of the graphite susceptor in step S3 is 30-40 r / min.

[0012] Preferably, in step S3, the silicon epitaxial furnace is cooled, a silicon substrate sheet is placed into a sheet pit of a graphite base, the graphite base is rotated, hydrogen is introduced, air is exhausted, and the silicon epitaxial furnace is heated to 1130-1150° C. and kept warm for 3-5 minutes.

[0013] Preferably, the hydrogen flow rate in step S2 is 45-50 L / min.

[0014] Preferably, the step of cleaning the silicon epitaxial furnace reaction chamber and the graphite susceptor therein comprises:

[0015] The reaction chamber of the silicon epitaxial furnace is heated to 1160-1180°C. After heating, hydrogen chloride gas is introduced using hydrogen as a carrier gas to clean the reaction chamber of the silicon epitaxial furnace and the graphite base inside it; wherein the hydrogen flow rate is set to 3-5 L / min, the hydrogen chloride gas flow rate is set to 15-20 L / min, and the cleaning time is set to 125-150s.

[0016] Preferably, in step S3, the reaction chamber is cooled to 600-650° C., and the silicon substrate is placed into the sheet pit of the graphite base.

[0017] Preferably, the silicon substrate has a diameter of 125-200 mm, a resistivity of 0.001-0.005 Ω·cm, an N-type conductivity, and a mirror-polished front surface.

[0018] Preferably, the silicon epitaxial furnace is a 5200 flat-plate single-wafer silicon epitaxial furnace; and there is no exhaust hole at the bottom of the graphite base.

[0019] The present invention also provides a silicon epitaxial wafer obtained based on the method for preparing a silicon epitaxial wafer free of cracks and edge collapse for power devices as described in any one of the above.

[0020] The present invention provides a silicon epitaxial wafer for power devices without cracks or edge collapse and a preparation method thereof, which has the following improvements compared with the prior art:

[0021] The invention provides a method for preparing a silicon epitaxial wafer without cracks and edge collapse for a power device. Before growing a silicon epitaxial layer, a reaction chamber of a silicon epitaxial furnace and a graphite base are etched, and a polysilicon coating layer of a certain thickness is grown on the graphite base, thereby avoiding the problem of cracks and edge collapse of the silicon epitaxial wafer caused by the edge easily adhering to or colliding with the graphite base during the long-term growth of the silicon epitaxial wafer in a traditional flat-plate monolithic silicon epitaxial furnace, effectively blocking impurities released by the graphite base, reducing pollution to the silicon epitaxial layer, and limiting the thickness of the polysilicon coating layer. If the polysilicon coating layer is too thin or too thick, it will also affect the problem of cracks and edge collapse of the silicon epitaxial wafer. Furthermore, the growth conditions of the silicon epitaxial layer are adjusted, and the growth rate and growth temperature are controlled so that the formed silicon epitaxial layer does not generate cracks, thereby improving the stability and repeatability of the process, and realizing the mass production of silicon epitaxial wafers with a thickness of 25-30 μm in a flat-plate monolithic silicon epitaxial furnace. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the thickness distribution of the silicon epitaxial wafer obtained in Example 1;

[0024] Figure 2 A schematic diagram of the thickness distribution of the silicon epitaxial wafer obtained in Example 2;

[0025] Figure 3 Schematic diagram of thickness distribution of silicon epitaxial wafer obtained in Example 3;

[0026] Figure 4 Schematic diagram of thickness distribution of silicon epitaxial wafer obtained in Example 4;

[0027] Figure 5 Schematic diagram of thickness distribution of silicon epitaxial wafer obtained in Example 5;

[0028] Figure 6 Schematic diagram of edge cracks and edge collapse of the silicon epitaxial wafer obtained in Comparative Example 1;

[0029] Figure 7 Schematic diagram of edge cracks and edge collapse of the silicon epitaxial wafer obtained in Comparative Example 2;

[0030] Figure 8 Schematic diagram of edge cracks and edge collapse of the silicon epitaxial wafer obtained in Comparative Example 3;

[0031] Fig. 9 Schematic diagram of edge cracks and edge collapse of the silicon epitaxial wafer obtained in Comparative Example 4;

[0032] Fig.10 Schematic diagram of edge cracks and edge collapse of the silicon epitaxial wafer obtained in Comparative Example 5. DETAILED DESCRIPTION

[0033] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The present invention provides a method for preparing a crack-free and edge-break-free silicon epitaxial wafer for a power device, wherein the thickness of the silicon epitaxial layer of the silicon epitaxial wafer is 25-30 μm, and the preparation method comprises the following steps:

[0035] S1) cleaning the silicon epitaxial furnace reaction chamber and the graphite base inside it;

[0036] S2) introducing trichlorosilane gas into the reaction chamber of the silicon epitaxial furnace using hydrogen as a carrier gas to grow a polysilicon coating layer on the graphite susceptor, the flow rate of the trichlorosilane gas is 10-12 g / min, the growth time is 2-3 min, and the thickness of the polysilicon coating layer reaches 5-6 μm;

[0037] S3) The silicon epitaxial furnace is cooled down, a silicon substrate is placed into the sheet pit of the graphite base, the graphite base is rotated, hydrogen is introduced, and air is exhausted. The silicon epitaxial furnace is heated up to 1130-1150°C, and trichlorosilane gas is introduced into the silicon epitaxial furnace using hydrogen as a carrier. The flow rate of trichlorosilane gas is set to 2-4g / min; the growth rate is set to 1-2μm / min. When the thickness of the silicon epitaxial layer reaches the target, the temperature is lowered to obtain a silicon epitaxial wafer.

[0038] The invention provides a method for preparing a silicon epitaxial wafer without cracks and edge collapse for a power device. Before growing a silicon epitaxial layer, a reaction chamber of a silicon epitaxial furnace and a graphite base are etched, and a polysilicon coating layer of a certain thickness is grown on the graphite base, thereby avoiding the problem of cracks and edge collapse of the silicon epitaxial wafer caused by the edge easily adhering to or colliding with the graphite base during the long-term growth of the silicon epitaxial wafer in a traditional flat-plate monolithic silicon epitaxial furnace, effectively blocking impurities released by the graphite base, reducing pollution to the silicon epitaxial layer, and limiting the thickness of the polysilicon coating layer. If the polysilicon coating layer is too thin or too thick, it will also affect the problem of cracks and edge collapse of the silicon epitaxial wafer. Furthermore, the growth conditions of the silicon epitaxial layer are adjusted, and the growth rate and growth temperature are controlled so that the formed silicon epitaxial layer does not generate cracks, thereby improving the stability and repeatability of the process, and realizing the mass production of silicon epitaxial wafers with a thickness of 25-30 μm in a flat-plate monolithic silicon epitaxial furnace.

[0039] Specifically, in step S3, when trichlorosilane gas is introduced into the silicon epitaxial furnace using hydrogen as a carrier, the flow rate of hydrogen is set to 45-50 L / min.

[0040] Specifically, the rotation rate of the graphite susceptor in step S3 is 30-40 r / min.

[0041] Specifically, in step S3, the silicon epitaxial furnace is cooled, a silicon substrate is placed in a sheet pit of a graphite base, the graphite base is rotated, hydrogen is introduced, air is exhausted, and the silicon epitaxial furnace is heated to 1130-1150° C. and kept warm for 3-5 minutes.

[0042] Specifically, the hydrogen flow rate in step S2 is 45-50 L / min.

[0043] Preferably, the step of cleaning the silicon epitaxial furnace reaction chamber and the graphite susceptor therein comprises:

[0044] The reaction chamber of the silicon epitaxial furnace is heated to 1160-1180°C. After heating, hydrogen chloride gas is introduced using hydrogen as a carrier gas to clean the reaction chamber of the silicon epitaxial furnace and the graphite base inside it; wherein the hydrogen flow rate is set to 3-5 L / min, the hydrogen chloride gas flow rate is set to 15-20 L / min, and the cleaning time is set to 125-150s.

[0045] Specifically, in step S3, the reaction chamber is cooled to 600-650° C., and the silicon substrate is placed into the sheet pit of the graphite base.

[0046] Specifically, the silicon substrate has a diameter of 125-200 mm, a resistivity of 0.001-0.005 Ω·cm, an N-type conductivity, and a front surface mirror-polished.

[0047] Specifically, the silicon epitaxial furnace is a 5200 flat-plate single-wafer silicon epitaxial furnace; and there is no exhaust hole at the bottom of the graphite base.

[0048] The present invention provides a silicon epitaxial wafer obtained by the method for preparing a silicon epitaxial wafer free of cracks and edge collapse for power devices as described in any one of the above.

[0049] Embodiment 1

[0050] A method for preparing a crack-free and edge-collapse-free silicon epitaxial wafer for power devices comprises the following steps:

[0051] 101) heating the reaction chamber of the silicon epitaxial furnace to 1180° C., and after heating, introducing hydrogen chloride gas with hydrogen as carrier gas to clean the reaction chamber of the silicon epitaxial furnace and the graphite susceptor therein; wherein the hydrogen flow rate is set to 5 L / min, the hydrogen chloride flow rate is set to 20 L / min, and the cleaning time is set to 150 s;

[0052] 102) After cleaning, trichlorosilane gas was introduced into the reaction chamber of the silicon epitaxial furnace using hydrogen as a carrier gas to grow a polysilicon coating layer on the graphite base, wherein the hydrogen flow rate was 50 L / min, the trichlorosilane gas flow rate was 12 g / min, the growth time was 3 min, and the thickness of the polysilicon coating layer was 6 μm;

[0053] 103) The silicon epitaxial furnace is cooled down, the reaction chamber is cooled down to 650°C, a silicon substrate is placed in a sheet pit of a graphite base, hydrogen is introduced, air is exhausted, the silicon epitaxial furnace is heated up to 1150°C, and kept warm for 3 min, trichlorosilane gas is introduced into the silicon epitaxial furnace with hydrogen as a carrier, a silicon epitaxial layer is grown on the silicon substrate, and when the thickness of the silicon epitaxial layer reaches 25 μm, the temperature is reduced to 650°C to obtain a silicon epitaxial wafer; wherein, the flow rate of hydrogen is set to 50 L / min, the flow rate of trichlorosilane gas is set to 4 g / min; the growth rate is set to 2 μm / min; the rotation rate of the graphite base is 30 r / min.

[0054] The silicon substrate of the present invention has a diameter of 200 mm, a resistivity of 0.005 Ω·cm, an N-type conductivity, and a front surface mirror-polished.

[0055] The silicon epitaxial furnace of the present invention is a 5200 flat-plate single-chip silicon epitaxial furnace; the bottom of the graphite base has no exhaust holes.

[0056] The five test positions for the thickness of the silicon epitaxial wafer are the center point with the main reference facing upward and four points 6 mm above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer is calculated based on the five test positions, such as Figure 1 As shown, the thickness of the silicon epitaxial layer is 25.042μm, 25.125μm, 25.094μm, 25.213μm, and 25.176μm, respectively, with an average value of 25.13μm, and there are no cracks or edge collapse defects on the edges.

[0057] The above method can realize large-scale mass production of silicon epitaxial wafers without cracks and edge collapse for power devices.

[0058] Embodiment 2

[0059] A method for preparing a crack-free and edge-collapse-free silicon epitaxial wafer for power devices comprises the following steps:

[0060] 201) The reaction chamber of the silicon epitaxial furnace is heated to 1160° C. After heating, hydrogen chloride gas is introduced with hydrogen as carrier gas to clean the reaction chamber of the silicon epitaxial furnace and the graphite susceptor inside thereof; wherein the hydrogen flow rate is set to 3 L / min, the hydrogen chloride flow rate is set to 15 L / min, and the cleaning time is set to 125 s;

[0061] 202) After cleaning, trichlorosilane gas is introduced into the reaction chamber of the silicon epitaxial furnace using hydrogen as a carrier gas to grow a polysilicon coating layer on the graphite base, wherein the hydrogen flow rate is 45 L / min, the trichlorosilane gas flow rate is 10 g / min, the growth time is 2 min, and the thickness of the polysilicon coating layer is 5 μm;

[0062] 203) The silicon epitaxial furnace is cooled down, the reaction chamber is cooled down to 600°C, a silicon substrate is placed in a sheet pit of a graphite base, hydrogen is introduced, air is exhausted, the silicon epitaxial furnace is heated up to 1130°C, and kept warm for 5 min, trichlorosilane gas is introduced into the silicon epitaxial furnace with hydrogen as a carrier, a silicon epitaxial layer is grown on the silicon substrate, and when the thickness of the silicon epitaxial layer reaches 25 μm, the temperature is lowered to obtain a silicon epitaxial wafer; wherein, the flow rate of hydrogen is set to 45 L / min, the flow rate of trichlorosilane gas is set to 2 g / min; the growth rate is set to 1 μm / min; the rotation rate of the graphite base is 30 r / min.

[0063] The silicon substrate of the invention has a diameter of 125 mm, a resistivity of 0.001-0.005 Ω·cm, an N-type conductivity, and a mirror-polished front surface.

[0064] The silicon epitaxial furnace of the present invention is a 5200 flat-plate single-chip silicon epitaxial furnace; the bottom of the graphite base has no exhaust holes.

[0065] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested in the same manner as in the first embodiment. Figure 2 As shown, the thickness of the silicon epitaxial layer is 25.116μm, 25.287μm, 25.225μm, 25.109μm, and 25.205μm, respectively, with an average value of 25.19μm, and there are no cracks or edge collapse defects on the edges.

[0066] The above method can realize large-scale mass production of silicon epitaxial wafers without cracks and edge collapse for power devices.

[0067] Embodiment 3

[0068] A method for preparing a crack-free and edge-collapse-free silicon epitaxial wafer for power devices comprises the following steps:

[0069] 301) The reaction chamber of the silicon epitaxial furnace is heated to 1170° C. After heating, hydrogen chloride gas is introduced with hydrogen as carrier gas to clean the reaction chamber of the silicon epitaxial furnace and the graphite susceptor inside; wherein the hydrogen flow rate is set to 4 L / min, the hydrogen chloride flow rate is set to 17 L / min, and the cleaning time is set to 140 s;

[0070] 302) After cleaning, trichlorosilane gas is introduced into the reaction chamber of the silicon epitaxial furnace using hydrogen as a carrier gas to grow a polysilicon coating layer on the graphite base, wherein the hydrogen flow rate is 47 L / min, the trichlorosilane gas flow rate is 11 g / min, the growth time is 3 min, and the thickness of the polysilicon coating layer is 5 μm;

[0071] 303) The silicon epitaxial furnace is cooled down, the reaction chamber is cooled down to 630°C, a silicon substrate is placed in the sheet pit of the graphite base, hydrogen is introduced, and air is exhausted. The silicon epitaxial furnace is heated up to 1140°C and kept warm for 4 min. Trichlorosilane gas is introduced into the silicon epitaxial furnace with hydrogen as a carrier to grow a silicon epitaxial layer on the silicon substrate. When the thickness of the silicon epitaxial layer reaches 25μm, the temperature is lowered to obtain a silicon epitaxial wafer. The flow rate of hydrogen is set to 45-50L / min, and the flow rate of trichlorosilane gas is set to 3g / min. The growth rate is set to 2μm / min. The rotation rate of the graphite base is 40r / min.

[0072] The silicon substrate of the present invention has a diameter of 125 mm, a resistivity of 0.001 Ω·cm, an N-type conductivity, and a front surface mirror-polished.

[0073] The silicon epitaxial furnace of the present invention is a 5200 flat-plate single-chip silicon epitaxial furnace; the bottom of the graphite base has no exhaust holes.

[0074] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested in the same manner as in the first embodiment. Figure 3 As shown, the thickness of the silicon epitaxial layer is 25.335μm, 25.187μm, 25.165μm, 25.206μm, and 25.209μm, respectively, with an average value of 25.22μm, and there are no cracks or edge collapse defects on the edges.

[0075] The above method can realize large-scale mass production of silicon epitaxial wafers without cracks and edge collapse for power devices.

[0076] Embodiment 4

[0077] The difference between this embodiment and the first embodiment is only in step 103. In this embodiment, the flow rate of hydrogen is set to 48 L / min, the flow rate of trichlorosilane gas is set to 3 g / min; the growth rate is set to 1.4 μm / min; and the rotation rate of the graphite base is 35 r / min.

[0078] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested in the same manner as in the first embodiment. Figure 4 As shown, the thickness of the silicon epitaxial layer is 25.242μm, 25.198μm, 25.176μm, 25.232μm, and 25.336μm, respectively, with an average value of 25.24μm, and there are no cracks or edge collapse defects on the edges.

[0079] The above method can realize large-scale mass production of silicon epitaxial wafers without cracks and edge collapse for power devices.

[0080] Example 5

[0081] The difference between this embodiment and the first embodiment is only in step 103. In this embodiment, the flow rate of hydrogen is set to 45 L / min, the flow rate of trichlorosilane gas is set to 2 g / min; the growth rate is set to 1.0 μm / min; and the rotation rate of the graphite base is 40 r / min.

[0082] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested in the same manner as in the first embodiment. Figure 5 As shown, the thickness of the silicon epitaxial layer is 29.009μm, 29.108μm, 29.043μm, 29.165μm, and 29.176μm, respectively, with an average value of 29.10μm, and there are no cracks or edge collapse defects on the edges.

[0083] Example 6

[0084] The difference between this embodiment and the first embodiment is that when the thickness of the silicon epitaxial layer reaches 30 μm, the temperature is lowered to obtain a silicon epitaxial wafer.

[0085] The silicon epitaxial wafer obtained in this embodiment was tested for thickness using the same testing method as in Embodiment 1. The average thickness of the silicon epitaxial layer was 30.10 μm, and no cracks or edge collapse defects occurred at the edge.

[0086] Comparative Example 1

[0087] The difference between this comparative example and the first embodiment is that in step 102, the flow rate of trichlorosilane gas is 12 g / min, the growth time is 1 min, and the thickness of the polysilicon coating layer is 4 μm;

[0088] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested. Figure 6 As shown, the average thickness of the silicon epitaxial layer is 25.10 μm, and cracks and edge collapse defects appear at the edge.

[0089] Comparative Example 2

[0090] The only difference between this comparative example and step 103 in Example 1 is that the flow rate of trichlorosilane gas is 5 g / min and the growth rate is set to 2.5 μm / min.

[0091] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested. Figure 7 As shown, the average thickness of the silicon epitaxial layer is 27.20 μm, and cracks and edge collapse defects appear at the edge.

[0092] Comparative Example 3

[0093] The difference between this comparative example and step 103 in Example 1 is that the flow rate of trichlorosilane gas is 1 g / min and the growth rate is set to 1 μm / min.

[0094] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested. Figure 8 As shown, the average thickness of the silicon epitaxial layer is 24.25 μm, and cracks and edge collapse defects appear at the edge.

[0095] Comparative Example 4

[0096] The difference between this comparative example and step 103 in embodiment 1 is that the temperature of the silicon epitaxial furnace is raised to 1200°C.

[0097] The thickness of the silicon epitaxial wafer obtained in this embodiment is tested. Fig. 9 As shown, the average thickness of the silicon epitaxial layer is 26.32 μm, and cracks and edge collapse defects appear at the edge.

[0098] Comparative Example 5

[0099] The difference between this comparative example and step 103 in embodiment 1 is that the temperature of the silicon epitaxial furnace is raised to 1600°C.

[0100] like Fig.10 As shown, the silicon epitaxial wafer obtained in this embodiment was tested for thickness, and the average thickness of the silicon epitaxial layer was 24.52 μm, with cracks and edge collapse defects on the edges.

[0101] The above-mentioned Examples 1 to 6, as well as Comparative Examples 1 to 5, are all prepared in batches. It can be seen that, in Examples 1 to 6, through the improvement of the preparation process, the regulation of the thickness of the polysilicon coating layer, the regulation of the growth rate and the growth temperature of the silicon epitaxial layer, the prepared silicon epitaxial layers will not produce microcracks, and industrial batch preparation of silicon epitaxial wafers with a thickness of 25-30μm can be achieved.

[0102] In Comparative Example 1, the thickness of the polysilicon coating layer is too thin, the flow rate and growth rate of trichlorosilane in Comparative Example 2 and Comparative Example 3 are set too large or too small, and the growth temperature in Comparative Example 4 and Comparative Example 5 is too low or too high. Microcracks are generated in the obtained silicon epitaxial layers, which cannot meet the current requirements for industrial mass production of silicon epitaxial wafers.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a crack-free and edge-collapse-free silicon epitaxial wafer for power devices, characterized in that: The thickness of the silicon epitaxial layer of the silicon epitaxial wafer is 25-30 μm, and the preparation method comprises the following steps: S1) cleaning the silicon epitaxial furnace reaction chamber and the graphite base inside it; S2) introducing trichlorosilane gas into the reaction chamber of the silicon epitaxial furnace using hydrogen as a carrier gas to grow a polysilicon coating layer on the graphite susceptor, the flow rate of the trichlorosilane gas is 10-12 g / min, the growth time is 2-3 min, and the thickness of the polysilicon coating layer reaches 5-6 μm; S3) cooling the silicon epitaxial furnace, placing the silicon substrate into the sheet pit of the graphite base, rotating the graphite base, introducing hydrogen, exhausting the air, heating the silicon epitaxial furnace to 1130-1150°C, introducing trichlorosilane gas into the silicon epitaxial furnace with hydrogen as a carrier, and setting the flow rate of trichlorosilane gas to 2-4g / min; setting the growth rate to 1-2μm / min, and when the silicon epitaxial layer thickness reaches the target, cooling to obtain a silicon epitaxial wafer; In step S3, the reaction chamber is cooled to 600-650°C, and the silicon substrate is placed into the sheet pit of the graphite base; The rotation rate of the graphite base in step S3 is 30-40 r / min; The steps of cleaning the silicon epitaxial furnace reaction chamber and the graphite base therein include: The reaction chamber of the silicon epitaxial furnace is heated to 1160-1180°C. After heating, hydrogen chloride gas is introduced with hydrogen as carrier gas to clean the reaction chamber of the silicon epitaxial furnace and the graphite susceptor inside. The hydrogen flow rate is set to 3-5 L / min, the hydrogen chloride flow rate is set to 15-20 L / min, and the cleaning time is set to 125-150s. In step S3, when trichlorosilane gas is introduced into the silicon epitaxial furnace using hydrogen as a carrier, the flow rate of hydrogen is set to 45-50 L / min; The silicon epitaxial furnace is a 5200 flat-plate single-wafer silicon epitaxial furnace; there is no exhaust hole at the bottom of the graphite base.

2. The method for preparing a crack-free and edge-collapse-free silicon epitaxial wafer for power devices according to claim 1, characterized in that: In step S3, the silicon epitaxial furnace is cooled down, a silicon substrate is placed into a sheet pit of a graphite base, the graphite base is rotated, hydrogen is introduced, air is exhausted, and the silicon epitaxial furnace is heated to 1130-1150° C. and kept warm for 3-5 minutes.

3. The method for preparing a crack-free and edge-collapse-free silicon epitaxial wafer for power devices according to claim 1, characterized in that: The hydrogen flow rate in step S2 is 45-50 L / min.

4. The method for preparing a crack-free and edge-collapse-free silicon epitaxial wafer for power devices according to claim 1, characterized in that: The silicon substrate has a diameter of 125-200 mm, a resistivity of 0.001-0.005 Ω·cm, an N-type conductivity, and a front surface mirror-polished.

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