Gyro accelerometer output system based on photoelectric encoder

Abstract

The invention discloses a gyro accelerometer output system based on a photoelectric encoder, which is characterized in that photoelectric signals of the photoelectric encoder are converted into pulses with polarity in positive and negative directions and counting is carried out when a gyro accelerometer carries out precession, so that measured apparent acceleration is obtained; in-situ replacement of an original variable magnetoresistive sensor output system is realized. The invention provides a new technical scheme for obtaining the apparent acceleration, the output precision limitation of the original variable magnetoresistive sensor is broken through, the precision of the pendulum gyroscope accelerometer is improved, and the anti-electromagnetic interference capability is strong.

Description

Technical Field

[0001] The invention relates to the field of inertial navigation, in particular to a gyro accelerometer output system based on a photoelectric encoder. Background Art

[0002] As a high-precision inertial instrument, the pendulum-type integrating gyro accelerometer (hereinafter referred to as gyro accelerometer) reflects the measured apparent acceleration through the precession angle or angular velocity of the outer ring. It is used to measure the apparent acceleration information of the carrier in the inertial navigation system. It is an irreplaceable core measurement instrument in the inertial navigation platform system. Its performance and accuracy directly affect the navigation position accuracy of the carrier. Therefore, improving the performance accuracy of the gyro accelerometer is of great significance to the accuracy of the carrier.

[0003] Gyro accelerometers currently use variable reluctance sensors as outer ring angle sensors. They output sine and cosine signals when the gyro accelerometer precesses. The output system refers to the excitation signal, converts the sine and cosine signals into pulses with positive and negative polarities and counts them. The number of pulses can represent the magnitude of the apparent acceleration. The machining accuracy of the variable reluctance sensor determines the quality of the sine and cosine signals and affects the accuracy of the gyro accelerometer. At present, the machining accuracy of the variable reluctance sensor has reached its limit. It is quite difficult to improve the measurement accuracy of the gyro accelerometer by improving the machining accuracy of the variable reluctance sensor. It is difficult to continue to improve the accuracy by this means. At the same time, as a magnetic sensitive element, the variable reluctance sensor is easily disturbed in complex electromagnetic environments such as vibration tables. These all limit the continuous improvement of the accuracy of the gyro accelerometer. In order to improve the accuracy of the gyro accelerometer, a new gyro accelerometer output system is constructed. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide a gyro accelerometer output system based on a photoelectric encoder, through which the system can replace the system with a variable reluctance sensor as the output device in situ, solve the problem of limited accuracy of the gyro accelerometer, and finally achieve the goal of improving the accuracy of the gyro accelerometer.

[0005] The technical solution of the present invention is: a gyro accelerometer output system based on a photoelectric encoder, comprising:

[0006] The photoelectric encoder is connected to the gyro accelerometer, rotates with the outer ring shaft of the gyro accelerometer, converts the mechanical displacement of the outer ring shaft into differential sine signals and differential cosine signals through photoelectric conversion, and outputs them to the signal conversion circuit;

[0007] The signal conversion circuit converts the differential sine signal and the differential cosine signal into a single-channel sine signal and a single-channel cosine signal respectively, and after determining the direction of the two single-channel positive and cosine signals by phase, converts any of the single-channel positive / cosine signals into a positive pulse signal and a negative pulse signal, and then divides the positive pulse signal and the negative pulse signal and transmits them to the counting circuit;

[0008] The counting circuit counts the positive pulse and negative pulse signals to obtain the apparent acceleration measured by the gyro accelerometer.

[0009] Further, the signal conversion circuit comprises:

[0010] A differential signal conversion module, used to convert the differential signal input to the module into a single-channel signal and transmit it to the signal level conversion module;

[0011] A signal level conversion module, used to realize the level conversion of signals between the differential signal conversion module and the FPGA controller module;

[0012] The FPGA controller module is used to determine the direction of the single-channel positive and cosine signals transmitted from the signal level conversion module through the phase, convert any single-channel positive / cosine signal into a positive pulse or negative pulse signal, and divide the frequency of the positive pulse or negative pulse signal and output it to the output bus module;

[0013] Output bus module, realizing level conversion of signals between FPGA controller module and external cables;

[0014] The power circuit module is used to receive external power supply, perform power conversion, and supply power to each module of the signal conversion circuit;

[0015] The external cable is arranged between the signal conversion circuit and the counting circuit, receives the positive and negative pulse signals output by the output bus module, and transmits them to the counting circuit.

[0016] Furthermore, the direction of the single-channel sine and cosine signals is determined by phase, and the sine signal is converted into positive pulse and negative pulse signals.

[0017] Furthermore, the specific method of converting the sinusoidal signal into positive pulse and negative pulse signals is:

[0018] When the phase difference between the sine signal and the cosine signal is 90°, it means that the gyro accelerometer is in positive precession, the direction signal is positive polarity, the rising edge of the sine signal is recorded as the rising edge of the positive pulse, and the falling edge of the sine signal is recorded as the falling edge of the positive pulse; when the phase difference between the sine signal and the cosine signal is 270°, it means that the gyro accelerometer is in reverse precession, the direction signal is negative polarity, the rising edge of the sine signal is recorded as the rising edge of the negative pulse, and the falling edge of the sine signal is recorded as the falling edge of the negative pulse;

[0019] Driven by the clock and direction signals, the rising edge of the positive pulse, the falling edge of the positive pulse and the holding level are synthesized to obtain a positive pulse, and the rising edge of the negative pulse, the falling edge of the negative pulse and the holding level are synthesized to obtain a negative pulse.

[0020] Furthermore, the frequency division method of the positive pulse and negative pulse signals is: the frequency division is reversed once every 15 pulse signals, the frequency of the positive pulse signal is reduced to 1 / 30 before the frequency division, and the frequency of the negative pulse signal is reduced to 1 / 30 before the frequency division.

[0021] Furthermore, the FPGA controller module adopts XC6SLX9; the differential signal conversion module includes two MAX485ESA chips, which convert the differential sine signal and the differential cosine signal into two single-channel signals in a simplex form and transmit them to the signal level conversion module.

[0022] Furthermore, the signal level conversion module and the output bus module both use the SM164245 chip. The signal level conversion module converts the 5V level of the output signal of the differential signal conversion module into a 3.3V level; the output bus module converts the 3.3V level of the output signal of the FPGA controller module into a 5V level.

[0023] Furthermore, the power circuit module adopts LPS70302 chip to convert 5V power supply into 3.3V and 2.5V power supply, and adopts LM1117DT chip to convert 5V power supply into 1.2V power supply; 5V driving voltage is provided to the differential signal conversion module through internal printed lines; 5V and 3.3V driving voltage are provided to the signal level conversion module and the output bus module through internal printed lines; 3.3V, 2.5V and 1.2V voltages are provided to the FPGA controller module through internal printed lines.

[0024] Furthermore, the output of the photoelectric encoder also includes a differential zero-position signal and a differential fault signal. The FPGA controller module controls the on and off of four LED lights to indicate the status of the differential sine signal, differential cosine signal, differential zero-position signal and differential fault signal respectively.

[0025] Furthermore, in an inertial navigation system, the gyro accelerometer adopts a pendulum gyro accelerometer, and the photoelectric encoder adopts an incremental photoelectric encoder or an absolute photoelectric encoder.

[0026] The advantages of the present invention compared with the prior art are:

[0027] (1) The present invention designs a gyro accelerometer output system based on a photoelectric encoder, innovatively uses a photoelectric encoder as an outer ring precession angle sensor to replace the traditional variable reluctance sensor, and replaces the RDC shaft angle conversion circuit of the prior art by designing a signal conversion circuit, thereby solving the problem of large angle measurement error (4 arc minutes) of the RDC shaft angle conversion circuit and key component problems. The signal conversion circuit uses the method of direction recognition, pulse synthesis and frequency division to convert the sine and cosine signals output by the photoelectric encoder into positive and negative pulse signals, and transmits them to the counting circuit. The counting circuit calculates the precession angle of the pendulum gyro accelerometer according to the number of positive and negative pulses to obtain the apparent acceleration. The present invention provides an innovative technical solution for obtaining apparent acceleration, which improves the outer ring angle measurement accuracy of the gyro accelerometer, which is more than 10 times the resolution of the prior art, and achieves an effect better than angle grading.

[0028] (2) The present invention adopts the technical solution of replacing the variable reluctance sensor in situ with the photoelectric encoder, and at the same time improves the anti-electromagnetic interference capability of the output system, thereby improving the reliability of the gyro accelerometer output compared with the prior art.

[0029] (3) The present invention provides an optimal chip selection, adopts the high-speed differential serial communication MAX485ESA to process the high-frequency differential sine and cosine signals of the photoelectric encoder, adopts the bus driver chip SM164245 to realize the level conversion of the high-frequency signal of the photoelectric encoder, and adopts the FPGA controller to realize the direction and frequency division processing of the signal, thereby achieving the effect of low cost, high performance and high precision of the photoelectric encoder signal processing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is an overall functional block diagram of a gyro accelerometer output system based on a photoelectric encoder in an embodiment of the present invention;

[0031] Figure 2 is a principle block diagram of a signal conversion circuit in an embodiment of the present invention;

[0032] Figure 3 is a block diagram of an FPGA control module of a signal conversion circuit in an embodiment of the present invention;

[0033] Figure 4 It is a block diagram of the embedded software supporting the FPGA control module of the signal conversion circuit in the embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] This embodiment provides a gyro accelerometer output system based on a photoelectric encoder, such as Figure 1As shown, it includes: a photoelectric encoder 1, a signal conversion circuit 9, an external cable 7, and a counting circuit 8.

[0036] The photoelectric encoder 1 is connected to the gyro accelerometer, rotates with the outer ring shaft of the gyro accelerometer, and converts the mechanical displacement of the outer ring shaft into differential sine signals and differential cosine signals through photoelectric conversion, and outputs them to the signal conversion circuit; the phase difference of the two signals represents the precession direction of the outer ring, and the signal frequency represents the precession speed of the outer ring; the signal conversion circuit 9 converts the differential sine signal and the differential cosine signal into a single sine signal and a single cosine signal respectively, and after judging the direction of the two single positive and cosine signals by phase, any single positive / cosine signal is converted into a positive pulse and a negative pulse signal, and then the positive pulse and negative pulse signals are divided and transmitted to the counting circuit 8 through the external cable 7; the counting circuit 8 counts the number of positive pulses and negative pulses to obtain the precession angle or angular velocity of the gyro accelerometer, thereby obtaining the apparent acceleration. The photoelectric encoder has a compact structure and can be directly installed at the original variable reluctance sensor. The system has the advantages of compact structure, high precision and strong anti-electromagnetic interference ability.

[0037] In a preferred implementation, the signal conversion circuit 9 includes a signal input interface, a differential signal conversion module 2, a signal level conversion module 3, an FPGA controller module 4, an output bus module 5, a power circuit module 6, a pulse output interface, and an indicator light. Specifically, Figure 2 As shown:

[0038] The photoelectric encoder 1 rotates with the outer ring shaft of the gyro accelerometer. The reading head converts the mechanical displacement into two differential signals through photoelectric conversion, differential sine signals A﹢, A﹣ and differential sine signals B﹢, B﹣. The apparent acceleration measured by the pendulum gyro accelerometer will be reflected in the two differential sine and cosine signals output by the photoelectric encoder, which are obtained through subsequent calculation. In addition, the photoelectric encoder also outputs a differential zero position signal R﹢, R﹣ and a differential fault signal E﹢, E﹣. These four pairs of differential signals are input to the differential signal conversion module 2 of the signal conversion circuit 9 through the signal input interface.

[0039] The differential signal conversion module 2 converts the four pairs of differential signals into four single-channel signals A, B, R, and E in a simplex form and transmits them to the signal level conversion module 3; the control signals RT and DI of the transmission process are output by the FPGA controller module 4 to control the on and off of the signal transmission of the differential signal conversion module 2.

[0040] The signal level conversion module 3 converts the four 5V level signals transmitted from the differential signal conversion module 2 into four 3.3V level signals, and transmits them to the FPGA controller module 4; the FPGA controller module 4 controls the signal transmission direction of the signal level conversion module 3 through OE1 and DIR1.

[0041] The FPGA controller module 4 includes a driver control unit, a signal direction division unit, and an LED unit. The driver control unit controls the on and off of the signal transmission of the differential signal conversion module 2, and controls the signal transmission direction of the signal level conversion module 3 and the output bus module 5; the signal direction division unit determines the direction of the two sine signals A and cosine signals B transmitted from the signal level conversion module 3 by phase, converts the sine signal A or cosine signal B into positive pulse and negative pulse signals, and divides the positive pulse and negative pulse signals and outputs them to the output bus module 5; the LED unit controls the on and off of four LED lights, indicating the status of the differential sine signal, differential cosine signal, differential zero position signal, and differential fault signal respectively.

[0042] Specifically, this embodiment provides a method of determining the direction of the sine signal A and the cosine signal B by phase, and converting the sine signal A into a positive pulse and a negative pulse signal as follows:

[0043] When the phase difference between the sine signal and the cosine signal is 90°, it means that the gyro accelerometer is in positive precession, the direction signal is positive polarity, the rising edge of the sine signal is recorded as the rising edge of the positive pulse, and the falling edge of the sine signal is recorded as the falling edge of the positive pulse; when the phase difference between the sine signal and the cosine signal is 270°, it means that the gyro accelerometer is in reverse precession, the direction signal is negative polarity, the rising edge of the sine signal is recorded as the rising edge of the negative pulse, and the falling edge of the sine signal is recorded as the falling edge of the negative pulse.

[0044] Driven by the clock and direction signals, the rising edge of the positive pulse, the falling edge of the positive pulse and the holding level are combined to obtain a positive pulse (ie, "pulse +"), and the rising edge of the negative pulse, the falling edge of the negative pulse and the holding level are combined to obtain a negative pulse (ie, "pulse -").

[0045] Preferably, the frequency division method of the positive pulse and the negative pulse is:

[0046] The frequency is reversed and divided every 15 pulse signals, and the frequency of the positive pulse signal is reduced to 1 / 30 before the frequency division, and the frequency of the negative pulse signal is reduced to 1 / 30 before the frequency division.

[0047] The output bus module 5 converts the 7-way 3.3V level signals transmitted from the FPGA controller module 4 into 7-way 5V level signals, namely "polarity", "pulse +", "pulse -", A, B, R, E; the FPGA controller module 4 controls the signal transmission direction of the output bus module 5 through OE2 and DIR2. These 7-way signals are connected to the external cable 7 through the pulse output interface and output to the counting circuit 8.

[0048] The power circuit module 6 receives external power supply, performs power conversion, and provides the required power for the sub-signal conversion module 2, the signal level conversion module 3, the FPGA controller module 4, and the output bus module 5 of the signal conversion circuit.

[0049] The counting circuit 8 counts the pulse signal in a fixed-count timing or fixed-time counting mode.

[0050] Timing counting means that the timer of the circuit accumulates positive and negative pulses according to the positive and negative channels respectively. The timing signal comes from the timing interrupt signal of the host computer. When the falling edge of the interrupt signal arrives, the pulse increment is locked and the pulse number is output.

[0051] Fixed-number timing means that the host computer sets the number of pulses. After starting the counting, the circuit's timer accumulates the pulse value. When the timing pulse reaches the set value, it no longer changes. The host computer queries the fixed-number timing result.

[0052] In a preferred implementation, the chip selection of each module of the signal conversion circuit 9 is:

[0053] The differential signal conversion module 2 adopts RS-485 communication mode and uses four MAX485ESA chips to convert the differential signal into a single-channel signal in a simplex form and transmit it to the signal level conversion module 3.

[0054] The signal level conversion module 3 and the output bus module 5 each use a bus driver chip SM164245 chip. The signal level conversion module 3 converts the 5V level of the output signal of the differential signal conversion module into a 3.3V level; the output bus module 5 converts the 3.3V level of the output signal of the FPGA controller module into a 5V level.

[0055] FPGA controller module 4, using XC6SLX9-2TQG1441; Figure 3 As shown, RO1, RO2, RO3, and RO4 are common IO ports, which function as input pins and receive 4 signals output by SM164245 of signal level conversion module 3. GRESET is a common IO port, which receives the reset control signal output from the outside of the circuit board. This signal is controlled by the operator and can realize the manual reset function of FPGA. GCLK is a common IO port, which receives the crystal oscillator signal.

[0056] OE1, DIR1, OE2, and DIR2 are common IO ports, and their functions are output pins. They control the data transmission direction of two SM164245s. RT1, DI1, RT2, DI2, RT3, DI3, RT4, and DI4 are common IO ports, and their functions are output pins. They control four MAX485ESAs to transmit four-way serial communication signals. DIR, BUSY﹢, BUSY﹣, A, B, R, and E are all common IO ports, and their functions are output pins. They output pulse signals.

[0057] The FPGA controller uses the JTAG mode to burn the control program. The program is solidified in the PROM chip, and the programming interfaces TDI, TDO, TCK, and TMS are connected to the fixed function pins of the FPGA.

[0058] The power circuit module 6 adopts the LPS70302 chip to convert the 5V power supply into 3.3V and 2.5V power supplies, and adopts the LM1117DT chip to convert the 5V power supply into 1.2V power supply; provides a 5V driving voltage to the differential signal conversion module 2 through the internal printed wires; provides a 5V and 3.3V driving voltage to the signal level conversion module 3 and the output bus module 5 through the internal printed wires; provides 3.3V, 2.5V and 1.2V voltages to the FPGA controller module 4 through the internal printed wires.

[0059] Furthermore, this embodiment also provides a block diagram of the embedded software supporting the FPGA control module 4, such as Figure 4 The software is divided into three sub-functions, namely, control differential signal conversion module, input bus input module, output bus output module function (corresponding to the driver control unit, hereinafter referred to as the control function), direction division, separation synthesis pulse, frequency division function (corresponding to the signal direction division unit, hereinafter referred to as the frequency division function), control indicator light function (corresponding to the LED unit).

[0060] The control function has no input variables and outputs RT, DI, OE, and DIR series variables. These variables are output to the pins of the FPGA control module to control the four MAX485ESAs of the differential signal conversion module 2 and the two SM164245s of the signal level conversion module 3 and the signal level conversion module 5.

[0061] The frequency division function works on the rising edge of the global clock variable clk according to the enable variable rst. The input variables are A-in, B-in, R-in, and E-in. Among them, A-in and B-in generate the DIR-pulse variable after the direction division function. The phase difference between A-in and B-in is 90° or 270°.

[0062] Driven by the rising edge of the clock, a 2-bit register Areg is used to record the high and low level states of the sine signal A-in (the digital circuit defaults to high level as 1 and low level as 0). The low bit of Areg records the A-in level at the current clock rising edge, and the high bit of Areg records the A-in level at the previous clock rising edge. Similarly, a 2-bit register Breg is used to record the high and low level states of the sine signal B-in. The low bit of Breg records the B-in level at the current clock rising edge, and the high bit of Breg records the B-in level at the previous clock rising edge. In this way, the sine signal A-in and the cosine signal are converted from analog (high level, low level) to digital (0, 1) with the clock as the time axis.

[0063] Use the 1-bit register DIR-pulse to record the direction signal, and the 2-bit register Areg1 to record Areg synchronously. Driven by the rising edge of the clock, when Areg is equal to 2'b01 (2'b01 represents the rising edge), if Breg is equal to 2'b00 (2'b00 represents a low level of 2 clock widths), it means that the gyro accelerometer is moving in the positive direction, and DIR-pulse is assigned a value of 1 to indicate that the direction signal is positive, and Areg1 is assigned a value of Areg to indicate that Areg1 records the rising edge of the positive pulse; if Breg is equal to 2'b11 (2'b11 represents a high level of 2 clock widths), it means that the gyro accelerometer is moving in the negative direction, and DIR-pulse is assigned a value of 0 to indicate that the direction signal is negative, and Areg Areg value 1 indicates that Areg1 records the rising edge of the negative pulse; when Areg is equal to 2'b10 (2'b10 represents the falling edge), if Breg is equal to 2'b00, it represents the negative precession of the gyro accelerometer, DIR-pulse value 0 indicates that the direction signal is negative, Areg1 value Areg indicates that Areg1 records the falling edge of the negative pulse; if Breg is equal to 2'b11, it represents the positive precession of the gyro accelerometer, DIR-pulse value 1 indicates that the direction signal is positive, and Areg1 value Areg indicates that Areg1 records the falling edge of the positive pulse. In this way, the recognition of direction, positive pulse rising edge, positive pulse falling edge, negative pulse rising edge, and negative pulse falling edge is realized, that is, direction and pulse separation.

[0064] Use 1-bit register busy_pos to record positive pulses. Driven by the rising edge of the clock, when Areg1 is equal to 2'b01, if DIR-pulse is equal to 1, busy_pos is equal to 1, otherwise busy_pos remains unchanged. When Areg1 is equal to 2'b10, if DIR-pulse is equal to 1, busy_pos is equal to 0, otherwise busy_pos remains unchanged. When Areg1 is equal to 2'b11 or 2'b00, busy_pos remains unchanged. This realizes the synthesis of positive pulses.

[0065] Use 1-bit register busy_neg to record negative pulses. Driven by the rising edge of the clock, when Areg1 is equal to 2'b01, if DIR-pulse is equal to 0, busy_neg is equal to 1, otherwise busy_neg remains unchanged. When Areg1 is equal to 2'b10, if DIR-pulse is equal to 0, busy_neg is equal to 0, otherwise busy_neg remains unchanged. When Areg1 is equal to 2'b11 or 2'b00, busy_neg remains unchanged. This realizes the synthesis of negative pulses.

[0066] The two positive and negative pulse signals are flipped once every 15 pulses, that is, when 15 positive pulses appear, the positive frequency-divided pulse POS-pulse continues to be 1, and the subsequent 15 positive pulses, the positive frequency-divided pulse POS-pulse continues to be 0, and the next 15 positive pulses POS-pulse become 1 again, and the cycle repeats. The negative pulse NEG-pulse is the same. Thus, two variables of positive frequency-divided pulse POS-pulse and negative frequency-divided pulse NEG-pulse are formed, and the frequency of the positive frequency-divided pulse signal is reduced to 1 / 30 before the frequency division, and the frequency of the negative frequency-divided pulse signal is reduced to 1 / 30 before the frequency division.

[0067] The input variables of the indicator light control function come from the input R-in and E-in of the main function and the output A-out and B-out of the frequency division function. The A-LED, B-LED, R-LED, and E-LED variables are output to the control module pins to control the on and off of the four indicator lights.

[0068] It is to be understood that the present invention is described by way of embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and embodiments that can fall within the scope of the claims of this application all fall within the scope protected by the present invention.

[0069] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A gyro accelerometer output system based on a photoelectric encoder, characterized in that: include: The photoelectric encoder is connected to the gyro accelerometer, rotates with the outer ring shaft of the gyro accelerometer, converts the mechanical displacement of the outer ring shaft into differential sine signals and differential cosine signals through photoelectric conversion, and outputs them to the signal conversion circuit; The signal conversion circuit converts the differential sine signal and the differential cosine signal into a single-channel sine signal and a single-channel cosine signal respectively, and after determining the direction of the two single-channel positive and cosine signals by phase, converts any of the single-channel positive / cosine signals into a positive pulse signal and a negative pulse signal, and then divides the positive pulse signal and the negative pulse signal and transmits them to the counting circuit; The counting circuit counts the positive pulse and negative pulse signals to obtain the apparent acceleration measured by the gyro accelerometer.

2. The gyro accelerometer output system based on photoelectric encoder according to claim 1, characterized in that: The signal conversion circuit includes: A differential signal conversion module, used to convert the differential signal input to the module into a single-channel signal and transmit it to the signal level conversion module; A signal level conversion module, used to realize the level conversion of signals between the differential signal conversion module and the FPGA controller module; The FPGA controller module is used to determine the direction of the single-channel positive and cosine signals transmitted from the signal level conversion module through the phase, convert any single-channel positive / cosine signal into a positive pulse or negative pulse signal, and divide the frequency of the positive pulse or negative pulse signal and output it to the output bus module; Output bus module, realizing level conversion of signals between FPGA controller module and external cables; The power circuit module is used to receive external power supply, perform power conversion, and supply power to each module of the signal conversion circuit; The external cable is arranged between the signal conversion circuit and the counting circuit, receives the positive and negative pulse signals output by the output bus module, and transmits them to the counting circuit.

3. The gyro accelerometer output system based on photoelectric encoder according to claim 1, characterized in that: The direction of a single-channel sine and cosine signal is determined by the phase, and the sine signal is converted into positive pulse and negative pulse signals.

4. The gyro accelerometer output system based on photoelectric encoder according to claim 3, characterized in that: The specific method of converting a sinusoidal signal into a positive pulse and a negative pulse signal is: When the phase difference between the sine signal and the cosine signal is 90°, it means that the gyro accelerometer is in positive precession, the direction signal is positive polarity, the rising edge of the sine signal is recorded as the rising edge of the positive pulse, and the falling edge of the sine signal is recorded as the falling edge of the positive pulse; when the phase difference between the sine signal and the cosine signal is 270°, it means that the gyro accelerometer is in reverse precession, the direction signal is negative polarity, the rising edge of the sine signal is recorded as the rising edge of the negative pulse, and the falling edge of the sine signal is recorded as the falling edge of the negative pulse; Driven by the clock and direction signals, the rising edge of the positive pulse, the falling edge of the positive pulse and the holding level are synthesized to obtain a positive pulse, and the rising edge of the negative pulse, the falling edge of the negative pulse and the holding level are synthesized to obtain a negative pulse.

5. The gyro accelerometer output system based on photoelectric encoder according to claim 4, characterized in that: The frequency division method of the positive pulse and negative pulse signals is: the frequency division is reversed once every 15 pulse signals, the frequency of the positive pulse signal is reduced to 1 / 30 before the frequency division, and the frequency of the negative pulse signal is reduced to 1 / 30 before the frequency division.

6. The gyro accelerometer output system based on photoelectric encoder according to claim 2, characterized in that: The FPGA controller module uses XC6SLX9; the differential signal conversion module includes two MAX485ESA chips, which convert the differential sine signal and the differential cosine signal into two single-channel signals in a simplex form and transmit them to the signal level conversion module.

7. The gyro accelerometer output system based on photoelectric encoder according to claim 6, characterized in that: The signal level conversion module and the output bus module both use the SM164245 chip. The signal level conversion module converts the 5V level of the output signal of the differential signal conversion module into a 3.3V level; the output bus module converts the 3.3V level of the output signal of the FPGA controller module into a 5V level.

8. The gyro accelerometer output system based on photoelectric encoder according to claim 7, characterized in that: The power circuit module uses the LPS70302 chip to convert the 5V power supply into 3.3V and 2.5V power supplies, and uses the LM1117DT chip to convert the 5V power supply into 1.2V power supply; 5V driving voltage is provided to the differential signal conversion module through the internal printed lines; 5V and 3.3V driving voltages are provided to the signal level conversion module and the output bus module through the internal printed lines; 3.3V, 2.5V and 1.2V voltages are provided to the FPGA controller module through the internal printed lines.

9. The gyro accelerometer output system based on photoelectric encoder according to claim 2, characterized in that: The output of the photoelectric encoder also includes a differential zero-position signal and a differential fault signal. The FPGA controller module controls the on and off of four LED lights to indicate the status of the differential sine signal, differential cosine signal, differential zero-position signal and differential fault signal respectively.

10. The gyro accelerometer output system based on photoelectric encoder according to claim 1, characterized in that: Applied to inertial navigation system, the gyro accelerometer adopts a pendulum gyro accelerometer, and the photoelectric encoder adopts an incremental photoelectric encoder or an absolute photoelectric encoder.

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