Display panel and display device
By setting pads larger than the pin size on the array substrate and adjusting their spacing, the bonding problem caused by changes in the integrated circuit size is solved, and compatibility with multiple sizes of ICs is achieved, and cost and time costs are reduced.
Patent Information
- Application Number
- CN202411520817.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2024-12-27
AI Technical Summary
As the size of the integrated circuit decreases, the bump position on the IC changes, resulting in the inability to bond with the array substrate. Multiple mold opening designs are required to adapt to array substrates of different sizes, which increases cost and time.
Design the display panel to set up multiple pads on the array substrate, whose size is larger than the pins of the integrated circuit, and the distance between adjacent pads is greater than the preset distance, so as to be compatible with integrated circuits of different sizes and ensure that the pins and pads are Corresponding connections to achieve bonding.
It effectively reduces the adaptation cost for integrated circuits of different sizes, simplifies the design process, reduces product verification time, and achieves compatibility with ICs of multiple sizes.
Smart Images
Figure CN119200290A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art
[0002] Electronic paper is an ultra-thin, ultra-light display screen with the advantages of high contrast and wide viewing angle, low power consumption, flexibility and portability. It is widely used in various display devices.
[0003] Electronic paper includes flexible printed lamination (FPL), integrated circuit (IC) and array substrate. FPL is attached to the array substrate, and IC is arranged on the array substrate except FPL. When the bump on IC is connected to the pad on the array substrate in a one-to-one correspondence, IC is bonded to the array substrate.
[0004] However, with the development of technology, the size of ICs continues to decrease. The change in IC size causes the position of the bump on the IC to change, making it impossible to connect with the corresponding pad of the substrate, resulting in the inability to bond the IC and the substrate. Summary of the invention
[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a display panel and a display device that can avoid designing a variety of array substrates for adapting to integrated circuit molds of different sizes, thereby effectively reducing the cost of the display panel.
[0006] In a first aspect, the present application provides a display panel. The display panel includes an array substrate and an integrated circuit, wherein a plurality of pads are disposed on one side of the array substrate, the integrated circuit is disposed opposite to the plurality of pads, the integrated circuit includes a plurality of input pins and a plurality of output pins arranged on both sides, the pads correspond to the pins of the integrated circuit one by one, in a first direction, the size of the pads is larger than the size of the pins, and the distance between two adjacent pads in the first direction is larger than a preset distance; the first direction is a direction perpendicular to the arrangement direction of the input pins or the output pins, and the preset distance is the minimum distance between two adjacent pads in the first direction in the case of avoiding a short circuit.
[0007] In combination with the first aspect, in a possible implementation manner, in the first direction, the sum of the sizes of two adjacent pads is greater than or equal to the size of the integrated circuit.
[0008] In combination with the first aspect, in a possible implementation, the array substrate includes a first switch unit, a second switch unit and a pixel unit, one end of the first switch unit is connected to the first test signal, and the other end is connected to the data line of the pixel unit, one end of the second switch unit is connected to the second test signal, and the other end is connected to the gate line of the pixel unit, and at most one of the first switch unit and the second switch unit is located in the array substrate area corresponding to the integrated circuit.
[0009] In combination with the first aspect, in a possible implementation, the first switch unit is located in the array substrate area corresponding to the integrated circuit, and the second switch unit is located in the non-display area of the display panel, except for the array substrate area corresponding to the integrated circuit.
[0010] In combination with the first aspect, in a possible implementation, the second switch unit is located in the array substrate area corresponding to the integrated circuit, and the first switch unit is located in the non-display area of the display panel, except for the array substrate area corresponding to the integrated circuit.
[0011] In combination with the first aspect, in a possible implementation manner, the first switch unit and the second switch unit are both located in a non-display area of the display panel, excluding an area of the array substrate corresponding to the integrated circuit.
[0012] In combination with the first aspect, in a possible implementation, the display panel also includes an electronic ink film, which is attached to one side of the array substrate where the integrated circuit is set, and the second switch unit is located in the non-display area of the display panel, the area covered by the electronic ink film; the display area of the display panel is within the area covered by the electronic ink film.
[0013] In combination with the first aspect, in a possible implementation, the display panel includes an electronic ink film, which is attached to one side of the array substrate where an integrated circuit is set, and the first switch unit is located in a non-display area of the display panel, an area excluding an area covered by the electronic ink film and an area corresponding to the integrated circuit; the display area of the display panel is within the area covered by the electronic ink film.
[0014] In combination with the first aspect, in a possible implementation manner, the first switch unit includes a plurality of switch transistors, and the plurality of switch transistors are located in a wiring region of a data line of the pixel unit and are distributed alternately between the data lines.
[0015] In a second aspect, the present application further provides a display device, which includes the display panel as described in the first aspect.
[0016] The embodiment of the present application provides a display panel and a display device, wherein the display panel includes an array substrate and an integrated circuit, wherein a plurality of pads are provided on one side of the array substrate, the integrated circuit is arranged opposite to the plurality of pads, the integrated circuit includes a plurality of input pins and a plurality of output pins arranged on both sides, the pads correspond to the pins of the integrated circuit one by one, and in a direction perpendicular to the arrangement direction of the input pins or the output pins, the size of the pads is larger than the size of the pins, and the distance between two adjacent pads in the first direction is larger than a preset distance. In the display panel provided by the embodiment of the present application, the size of the pads corresponding to the input pins and / or the output pins of the integrated circuit on the array substrate is larger than the input pins and / or the output pins, so that for an integrated circuit of any size, when the integrated circuit is opposite to the array substrate, the input pins and the output pins can be located within the range of the pads, corresponding to the positions of the pads, so as to realize the bonding of the array substrate with integrated circuits of different sizes, avoid the need to design a variety of array substrates for adaptation for integrated circuits of different sizes, and effectively reduce the cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 is a cross-sectional schematic diagram of an IC and an array substrate of a display panel in one embodiment; Figure 2 A schematic diagram of the distribution of pads of an array substrate in a display panel in an embodiment; Figure 3 Another schematic diagram of the distribution of pads on the array substrate of a display panel in one embodiment; Figure 4 Another schematic diagram of the distribution of pads on the array substrate of a display panel in one embodiment; Figure 5 Another schematic diagram of the distribution of pads on the array substrate of a display panel in one embodiment; Figure 6 A schematic diagram of the distribution of test circuits in an array substrate in the prior art; Figure 7 A schematic diagram of the distribution of the test circuit in the array substrate in one embodiment; Figure 8 is another schematic diagram of the distribution of the test circuit in the array substrate in one embodiment; Fig. 9 is another schematic diagram of the distribution of the test circuit in the array substrate in one embodiment; Fig.10 is another schematic diagram of the distribution of the test circuit in the array substrate in one embodiment; Fig.11is another schematic diagram of the distribution of the test circuit in the array substrate in one embodiment; Fig.12 is a schematic cross-sectional view of a display panel in one embodiment; Fig.13 FIG. 4 is another schematic diagram of the distribution of the test circuit in the array substrate in one embodiment. DETAILED DESCRIPTION
[0018] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.
[0019] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. In addition, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone.
[0020] In the description of the present invention, it should be understood that the terms "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.
[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0022] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0023] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0024] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.
[0025] Electronic paper is an ultra-thin, ultra-light display screen with the advantages of high contrast and wide viewing angle, low power consumption, flexibility and portability. It is widely used in various display devices.
[0026] The electronic paper includes FPL, IC and array substrate, the FPL is attached to the array substrate, and the IC is arranged in the area of the array substrate except the FPL. Figure 1 As shown in FIG. 1 , a cross-sectional schematic diagram of an IC and an array substrate is shown. When the pins (bumps in the figure) on the IC are connected one-to-one with the pads (IC pads in the figure) on the array substrate (array substrate in the figure), the IC is bonded to the array substrate. The IC and the array substrate can be connected through an anisotropic conductive film (ACF), and the ACF realizes the electrical connection between the IC and the array substrate through conductive particles.
[0027] However, with the development of technology, the size of ICs has been continuously reduced. The change in IC size has caused the bump position on the IC to change, making it impossible to connect with the pad on the substrate, resulting in the IC and substrate being unable to bond. In order to adapt to ICs of various sizes, it is necessary to open molds and design multiple array substrates multiple times to adapt to ICs of various sizes, which increases costs, prolongs the product verification cycle, and increases time costs.
[0028] Based on this, an embodiment of the present application provides a display panel that can be compatible with ICs of various sizes while avoiding increasing costs such as materials and time.
[0029] In one embodiment, Figure 2 As shown, a display panel is provided, which includes an array substrate 10 and an integrated circuit 20. A plurality of solder pads 30 are arranged on one side of the array substrate 10. The integrated circuit 20 is arranged opposite to the plurality of solder pads 30. The integrated circuit 20 includes a plurality of input pins 21 and a plurality of output pins 22 respectively arranged on both sides. The solder pads 30 correspond one-to-one with the pins of the integrated circuit. In a first direction, the size of the solder pad 30 is larger than the size of the pin and the distance between two adjacent solder pads 30 in the first direction is larger than a preset distance.
[0030] The first direction is a direction perpendicular to the arrangement direction of the input pins 21 or the output pins 22. For example, the direction indicated by the arrow in the figure.
[0031] First of all, it should be noted that the dimensions of the array substrate and IC shown in the figure do not indicate the actual dimensions. The figure is only for illustrating the position and size relationship between the IC and the pads on the array substrate.
[0032] In the embodiment of the present application, when the pad 30 is arranged on the side of the array substrate 10 where the integrated circuit 20 is placed, the pad 30 is elongated in the first direction so that the size of the pad 30 is larger than the size of the pin. Figure 2 As shown, the size of the pad 30 corresponding to the input pin 21 may be larger than the size of the input pin 21, and the size of the pad 30 corresponding to the output pin 22 may be larger than the size of the output pin 22. Thus, for an integrated circuit 20 of any size, when the integrated circuit 20 is opposite to the array substrate 10, both the input pin 21 and the output pin 22 may be located within the range of the pad 30, corresponding to the position of the pad 30, so as to achieve bonding between the integrated circuit 20 and the array substrate 10.
[0033] like Figure 3As shown, the size of the pad 30 corresponding to the input pin 21 may match the size of the input pin 21, and the size of the pad 30 corresponding to the output pin 22 may be larger than the size of the output pin 22. Thus, for an integrated circuit 20 of any size, when the integrated circuit 20 is opposite to the array substrate 10 and the input pin 21 of the integrated circuit 20 corresponds to the position of the pad 30, the output pin 22 may also be located within the range of the pad 30 and corresponds to the position of the pad 30, thereby achieving bonding between the integrated circuit 20 and the array substrate 10.
[0034] like Figure 4 and Figure 5 As shown, the size of the pad 30 corresponding to the input pin 21 may be larger than the size of the input pin 21, and the size of the pad 30 corresponding to the output pin 22 may match the size of the output pin 22. Thus, for an integrated circuit 20 of any size, when the integrated circuit 20 is opposite to the array substrate 10 and the output pin 22 of the integrated circuit 20 corresponds to the position of the pad 30, the input pin 21 may also be located within the range of the pad 30 and correspond to the position of the pad 30, thereby achieving bonding between the integrated circuit 20 and the array substrate 10.
[0035] by Figure 5 Take an example for specific description, wherein IC A, IC B, and IC C are integrated circuits 20 of three different sizes. In a first direction, the size of IC A is larger than that of IC B, and the size of IC B is larger than that of IC C. The dotted box is a pad 30 corresponding to the input pin of the integrated circuit 20.
[0036] When IC A is opposite to the array substrate, the output pin 22 of IC A is aligned with the position of the pad 30 corresponding to the output pin, and the input pin 21 of IC A is located in the IC A bump area within the range of the pad 30 corresponding to the input pin. When IC B is opposite to the array substrate, the output pin 22 of IC B is aligned with the position of the pad 30 corresponding to the output pin, and the input pin 21 of IC B is located in the IC B bump area within the range of the pad 30 corresponding to the input pin. When IC C is opposite to the array substrate, the output pin 22 of ICC is aligned with the position of the pad 30 corresponding to the output pin, and the input pin 21 of IC C is located in the IC C bump area within the range of the pad 30 corresponding to the input pin.
[0037] That is, the array substrate 10 is adaptable to integrated circuits 20 of various sizes and can be bonded to integrated circuits 20 of various sizes.
[0038] In one embodiment, the distance between two adjacent pads 30 in the first direction should be greater than a preset distance, wherein the preset distance is the minimum distance between two adjacent pads 30 in the first direction while avoiding a short circuit.
[0039] That is, the distance between the pad 30 corresponding to the input pin 21 and the pad 30 corresponding to the output pin 22 in the first direction should be large enough to avoid contact between the two pads 30 and to avoid short circuit of the integrated circuit 20 after the integrated circuit 20 and the array substrate 10 are bonded.
[0040] In one embodiment, in the first direction, the sum of the sizes of two adjacent pads 30 is greater than or equal to the size of the integrated circuit 20 .
[0041] The size of the pads 30 on the array substrate 10 in the first direction should take into account the integrated circuits 20 of various sizes, that is, the sum of the sizes of the pads 30 corresponding to the input pins 21 and the pads 30 corresponding to the output pins 22 in the first direction is greater than or equal to the integrated circuit 20. For example, when the size of the integrated circuit 20 is relatively large, the size of the pads 30 on the array substrate 10 in the first direction is adapted to the size of the integrated circuit 20; for the integrated circuit 20 whose size is reduced with the development of technology, the size of the pads 30 on the array substrate 10 in the first direction is greater than the size of the integrated circuit 20, and due to the enlarged setting of the range of the pads 30, the pins of the integrated circuit 20 can all be located within the range of the pads 30, ensuring the normal bonding of the integrated circuit 20 and the array substrate 10.
[0042] The display panel provided by the embodiment of the present application includes an array substrate and an integrated circuit, a plurality of pads are provided on one side of the array substrate, the integrated circuit is arranged opposite to the plurality of pads, the integrated circuit includes a plurality of input pins and a plurality of output pins arranged on both sides respectively, the pads correspond to the pins of the integrated circuit one by one, in the vertical direction of the arrangement direction of the input pins or the output pins, the size of the pads is larger than the size of the pins, and the distance between two adjacent pads in the first direction is larger than the preset distance. In the display panel provided by the embodiment of the present application, the size of the pads corresponding to the input pins and / or the output pins of the integrated circuit on the array substrate is larger than the input pins and / or the output pins, so that for any size of the integrated circuit, when the integrated circuit is opposite to the array substrate, the input pins and the output pins can be located within the range of the pads, corresponding to the positions of the pads, so as to realize the bonding of the array substrate with the integrated circuits of different sizes, avoid the need to design a variety of array substrates for adaptation for the integrated circuits of different sizes, and effectively reduce the cost of the display panel.
[0043] like Figure 6As shown, in the prior art, the pads on the array substrate are often set at the edge of the area corresponding to the integrated circuit, and a test circuit is often set in the central area of the array substrate area corresponding to the integrated circuit to test the pixel units in the array substrate. Among them, the test circuit includes a scan signal test unit (Gate SW unit in the figure) and a data signal test unit (Data SW unit in the figure), and is often set to a layout in which the Data SW unit is located in the middle of the two parts of the Gate SW unit. The Data SW unit and the Gate SW unit are composed of a switch transistor (Switch Thin Film Transistor, SW TFT).
[0044] The input and output of the SW TFT in the Gate SW unit are connected to the test signal GO / GE and the scan signal Gate, respectively. For example, the input and output of the Gate SW unit in the odd rows are connected to the test signal GO (GateOdd) and the odd row scan signal Gate, respectively, and the input and output of the Gate SW unit in the even rows are connected to the test signal GE (Gate Even) and the even row scan signal Gate, respectively.
[0045] The input and output of the SW TFT in the Data SW unit are connected to the test signal DO / DE and the data signal Data, respectively. For example, the input and output of the Data SW unit in the odd row are connected to the test signal DO (Data Odd) and the odd row data signal Data, respectively, and the input and output of the Data SW unit in the even row are connected to the test signal DE (Data Even) and the even number data signal Data, respectively.
[0046] Among them, the operable area (Active Area, AA) of the display panel is located within the FPL range. However, since the pad area on the array substrate is enlarged in the present application, the setting area reserved for the test circuit in the array substrate area corresponding to the integrated circuit is greatly reduced. Therefore, it is necessary to rearrange the position of the test circuit on the array substrate.
[0047] In one embodiment, Figure 7As shown, the array substrate 10 includes a first switch unit 11, a second switch unit 12 and a pixel unit 13, one end of the first switch unit 11 is connected to the first test signal, and the other end is connected to the data line of the pixel unit 13, one end of the second switch unit 12 is connected to the second test signal, and the other end is connected to the gate line of the pixel unit 13, and at most one of the first switch unit 11 and the second switch unit 12 is located in the array substrate area corresponding to the integrated circuit 20.
[0048] The first test signal includes a DO signal and / or a DE signal; the second test signal includes a GO signal and / or a GE signal.
[0049] The pixel unit 13 is distributed in the AA area of the display panel, and the first switch unit 11 and the second switch unit 12 are distributed in the non-display area of the display panel, which is subsequently referred to as the frame area in the embodiment of the present application.
[0050] In the embodiment of the present application, after the area of the pad 30 on the array substrate 10 is expanded, at most one group of switch units can be set in the array substrate area corresponding to the integrated circuit 20. Therefore, at most one switch unit of the first switch unit 11 and the second switch unit 12 is located in the array substrate area corresponding to the integrated circuit 20.
[0051] For example, Figure 7 and Figure 8 As shown, the second switch unit 12 can be arranged in the array substrate area corresponding to the integrated circuit 20, and the first switch unit 11 can be arranged outside the array substrate area corresponding to the integrated circuit 20. That is, the first switch unit 11 is located in the array substrate area corresponding to the integrated circuit 20, and the second switch unit 12 is located in the non-display area of the display panel, except for the array substrate area corresponding to the integrated circuit.
[0052] The first switch unit 11 may also be disposed in the array substrate region corresponding to the integrated circuit 20, and the second switch unit 12 may be disposed outside the array substrate region corresponding to the integrated circuit 20. That is, the second switch unit 12 is located in the array substrate region corresponding to the integrated circuit 20, and the first switch unit 11 is located in the non-display region of the display panel, excluding the array substrate region corresponding to the integrated circuit 20.
[0053] When the remaining area of the array substrate area corresponding to the integrated circuit is small, such as Fig. 9 , Fig.10 and Fig.11 As shown, the first switch unit 11 and the second switch unit 12 can be arranged outside the array substrate area corresponding to the integrated circuit. That is, the first switch unit 11 and the second switch unit 12 are both located in the non-display area of the display panel, except the area outside the array substrate area corresponding to the integrated circuit 20.
[0054] It can be understood that the first switch unit 11 and the second switch unit 12 are both located outside the AA area, that is, located in the frame area.
[0055] In the display panel provided in the embodiment of the present application, the array substrate includes a first switch unit, a second switch unit and a pixel unit, one end of the first switch unit is connected to the first test signal, and the other end is connected to the data line of the pixel unit, one end of the second switch unit is connected to the second test signal, and the other end is connected to the gate line of the pixel unit, and at most one of the first switch unit and the second switch unit is located in the array substrate area corresponding to the integrated circuit. That is, the embodiment of the present application can re-layout the test circuit based on the size of the remaining area in the array substrate area corresponding to the integrated circuit, and set part of the test circuit in the array substrate area corresponding to the integrated circuit as much as possible, avoid excessive modification of the array substrate layout, ensure the orderly wiring method between the pixel unit and the test circuit in the original layout, and ensure the structural stability of the test circuit.
[0056] In one embodiment, Figure 7 As shown, the display panel further includes an electronic ink film 40 , which is attached to one side of the array substrate 10 where the integrated circuit 20 is disposed. The second switch unit 12 is located in the non-display area of the display panel, which is the area covered by the electronic ink film 40 .
[0057] In the embodiment of the present application, the electronic ink film 40 is used to display images under the action of the array substrate 10 and the integrated circuit 20 , so the display area of the display panel is within the area covered by the electronic ink film 40 .
[0058] Therefore, when the second switch unit 12 is located in the non-display area of the display panel, the second switch unit 12 may be located in the area covered by the electronic ink film 40 in the non-display area, for example, Fig. 9 , Fig.10 , Fig.11 Specifically, the second switch unit 12 can be distributed in the extension direction of the gate line (ie, the scanning signal line Gate) of the pixel unit 13, so as to ensure the orderliness of the wiring between the pixel unit 13 and the second switch unit 12 and the stability of the second switch unit 12.
[0059] The second switch unit 12 may also be located in a region outside the electronic ink film 40 (and outside the array substrate region corresponding to the integrated circuit 20 ).
[0060] Preferably, the second switch unit 12 is located in the non-display area of the display panel, which is the area covered by the electronic ink film 40. Fig.12As shown, in this case, the electronic ink film 40 has a light shielding effect relative to the second switch unit 12, which can prevent the channel region of the transistor in the second switch unit 12 from being irradiated by light, thereby preventing the transistor performance from being affected. Wherein, a-Si is the oxide semiconductor layer of the transistor, TFT channel is the channel region, M1 is the gate metal wiring layer, GI is the gate insulation layer, M2 is the source and drain metal wiring layer, and PVX is the passivation layer.
[0061] When the display panel is a liquid crystal display (LCD), the test circuit may be disposed in an area covered by a color filter (CF).
[0062] In one embodiment, Figure 7 As shown, the display panel also includes an electronic ink film 40, which is attached to one side of the array substrate 10 on which the integrated circuit 20 is set. The display panel includes the electronic ink film 40, which is attached to one side of the array substrate 10 on which the integrated circuit 20 is set. The first switch unit 11 is located in the non-display area of the display panel, excluding the area covered by the electronic ink film 40 and the area corresponding to the integrated circuit 20.
[0063] In the embodiment of the present application, the electronic ink film 40 is used to display images under the action of the array substrate 10 and the integrated circuit 20 , so the display area of the display panel is within the area covered by the electronic ink film 40 .
[0064] Therefore, when the first switch unit 11 is located in the non-display area of the display panel, the first switch unit 11 may be located in the area covered by the electronic ink film 40 in the non-display area, for example, Fig. 9 , Fig.10 Specifically, the first switch units 11 may be distributed in the extension direction of the data line (ie, Data) of the pixel unit 13 , thereby ensuring the orderliness of the wiring between the pixel unit 13 and the first switch unit 11 and ensuring the stability of the first switch unit 11 .
[0065] like Fig.11 As shown, the first switch unit 11 may also be located in the non-display area of the display panel, excluding the area covered by the electronic ink film 40 and the area corresponding to the integrated circuit 20 .
[0066] Preferably, the first switch unit 11 is located in the array substrate region between the electronic ink film 40 and the integrated circuit 20 .
[0067] In the display panel provided in the embodiment of the present application, when the first switch unit 11 and / or the second switch unit 12 are located in the non-display area of the display panel, the first switch unit 11 and / or the second switch unit 12 can be set in the area covered by the electronic ink film 40 to shield the first switch unit 11 and / or the second switch unit 12 from light, thereby preventing the channel area of the transistor in the first switch unit 11 and / or the second switch unit 12 from being exposed to light and affecting the performance of the transistor.
[0068] In one embodiment, when the first switch unit 11 is located in the non-display area of the display panel, the first switch unit 11 may be disposed in the array substrate area between the electronic ink film 40 and the integrated circuit 20 .
[0069] Specifically, the first switch unit 11 includes a plurality of switch transistors 111 . The plurality of switch transistors 111 are located in a wiring region of a data line of the pixel unit 13 and are staggeredly distributed between the data lines.
[0070] In the embodiment of the present application, there is a wiring area of a data line between the integrated circuit 20 and the pixel unit 13, and the integrated circuit 20 provides a data signal Data to the pixel unit 13 through the data line to control parameters such as the brightness of the pixel.
[0071] The first switch unit 11 may be arranged in the wiring area. Specifically, the plurality of switch transistors 111 included in the first switch unit 11 may be staggered and distributed between the data lines, that is, one switch transistor 111 is arranged between two data lines, and one data line is arranged between the two switch transistors 111. The first switch unit 11 is arranged in the gap of the wiring area of the data line, which can effectively save the space occupied by the array substrate, and at the same time, can ensure the orderliness of the wiring between the first switch unit 11 and the pixel unit 13, and ensure the functional stability of the first switch unit.
[0072] In one embodiment, a display device is provided, which includes the display panel described in the above embodiment. The display panel includes an array substrate 10 and an integrated circuit 20, a plurality of pads 30 are provided on one side of the array substrate 10, the integrated circuit 20 is arranged opposite to the plurality of pads 30, the integrated circuit 20 includes a plurality of input pins 21 and a plurality of output pins 22 arranged on both sides, the pads 30 correspond to the pins of the integrated circuit one by one, in a first direction, the size of the pads 30 is larger than the size of the pins and the distance between two adjacent pads 30 in the first direction is larger than a preset distance. The first direction is a direction perpendicular to the arrangement direction of the input pins 21 or the output pins 22.
[0073] In the embodiment of the present application, when the pad 30 is provided on the side of the array substrate 10 where the integrated circuit 20 is placed, the pad 30 is elongated in the first direction so that the size of the pad 30 is larger than the size of the pin. The size of the pad 30 corresponding to the input pin 21 may be larger than the size of the input pin 21, and the size of the pad 30 corresponding to the output pin 22 may be larger than the size of the output pin 22. Thus, for an integrated circuit 20 of any size, when the integrated circuit 20 is opposite to the array substrate 10, the input pin 21 and the output pin 22 may both be located within the range of the pad 30, corresponding to the position of the pad 30, so as to achieve bonding between the integrated circuit 20 and the array substrate 10.
[0074] The size of the pad 30 corresponding to the input pin 21 may match the size of the input pin 21, and the size of the pad 30 corresponding to the output pin 22 may be larger than the size of the output pin 22. Thus, for an integrated circuit 20 of any size, when the integrated circuit 20 is opposite to the array substrate 10 and the input pin 21 of the integrated circuit 20 corresponds to the position of the pad 30, the output pin 22 may also be located within the range of the pad 30 and corresponds to the position of the pad 30, thereby achieving bonding between the integrated circuit 20 and the array substrate 10.
[0075] Alternatively, the size of the pad 30 corresponding to the input pin 21 may be larger than the size of the input pin 21, and the size of the pad 30 corresponding to the output pin 22 may match the size of the output pin 22. Thus, for an integrated circuit 20 of any size, when the integrated circuit 20 is opposite to the array substrate 10 and the output pin 22 of the integrated circuit 20 is aligned with the pad 30, the input pin 21 may also be located within the pad 30 and aligned with the pad 30, thereby achieving bonding between the integrated circuit 20 and the array substrate 10.
[0076] For example, there are three integrated circuits 20 of different sizes, IC A, IC B, and IC C. In the first direction, the size of IC A is larger than that of IC B, and the size of IC B is larger than that of IC C. The dotted box is the pad 30 corresponding to the input pin of the integrated circuit 20.
[0077] When IC A is opposite to the array substrate, the output pin 22 of IC A is aligned with the position of the pad 30 corresponding to the output pin, and the input pin 21 of IC A is located in the IC A bump area within the range of the pad 30 corresponding to the input pin. When IC B is opposite to the array substrate, the output pin 22 of IC B is aligned with the position of the pad 30 corresponding to the output pin, and the input pin 21 of IC B is located in the IC B bump area within the range of the pad 30 corresponding to the input pin. When IC C is opposite to the array substrate, the output pin 22 of ICC is aligned with the position of the pad 30 corresponding to the output pin, and the input pin 21 of IC C is located in the IC C bump area within the range of the pad 30 corresponding to the input pin.
[0078] That is, the array substrate 10 is adaptable to integrated circuits 20 of various sizes and can be bonded to integrated circuits 20 of various sizes.
[0079] In one embodiment, the distance between two adjacent pads 30 in the first direction should be greater than a preset distance, wherein the preset distance is the minimum distance between two adjacent pads 30 in the first direction while avoiding a short circuit.
[0080] That is, the distance between the pad 30 corresponding to the input pin 21 and the pad 30 corresponding to the output pin 22 in the first direction should be large enough to avoid contact between the two pads 30 and to avoid short circuit of the integrated circuit 20 after the integrated circuit 20 and the array substrate 10 are bonded.
[0081] In one embodiment, in the first direction, the sum of the sizes of two adjacent pads 30 is greater than or equal to the size of the integrated circuit 20 .
[0082] The size of the pads 30 on the array substrate 10 in the first direction should take into account the integrated circuits 20 of various sizes, that is, the sum of the sizes of the pads 30 corresponding to the input pins 21 and the pads 30 corresponding to the output pins 22 in the first direction is greater than or equal to the integrated circuit 20. For example, when the size of the integrated circuit 20 is relatively large, the size of the pads 30 on the array substrate 10 in the first direction is adapted to the size of the integrated circuit 20; for the integrated circuit 20 whose size is reduced with the development of technology, the size of the pads 30 on the array substrate 10 in the first direction is greater than the size of the integrated circuit 20, and due to the enlarged setting of the range of the pads 30, the pins of the integrated circuit 20 can all be located within the range of the pads 30, ensuring the normal bonding of the integrated circuit 20 and the array substrate 10.
[0083] The display device provided by the embodiment of the present application includes a display panel, the display panel includes an array substrate and an integrated circuit, a plurality of pads are arranged on one side of the array substrate, the integrated circuit is arranged opposite to the plurality of pads, the integrated circuit includes a plurality of input pins and a plurality of output pins arranged on both sides, the pads correspond to the pins of the integrated circuit one by one, in the vertical direction of the arrangement direction of the input pins or the output pins, the size of the pads is larger than the size of the pins, and the distance between two adjacent pads in the first direction is larger than the preset distance. In the display device provided by the embodiment of the present application, the size of the pads corresponding to the input pins and / or output pins of the integrated circuit on the array substrate of the display panel is larger than the input pins and / or the output pins, so that for any size of the integrated circuit, when the integrated circuit is opposite to the array substrate, the input pins and the output pins can be located within the pad range, corresponding to the pad position, so as to realize the bonding of the array substrate with the integrated circuits of different sizes, avoid the need to open molds and design a variety of array substrates for adaptation for integrated circuits of different sizes, effectively reduce the cost of the display panel, and further reduce the cost of the display device.
[0084] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.
Claims
1. A display panel, characterized in that: The display panel includes an array substrate and an integrated circuit, a plurality of pads are arranged on one side of the array substrate, the integrated circuit is arranged opposite to the plurality of pads, the integrated circuit includes a plurality of input pins and a plurality of output pins arranged on both sides, the pads correspond to the pins of the integrated circuit one by one, In the first direction, the size of the pad is larger than the size of the pin and the distance between two adjacent pads in the first direction is larger than a preset distance; the first direction is a direction perpendicular to the arrangement direction of the input pin or the output pin, and the preset distance is the minimum distance between two adjacent pads in the first direction while avoiding a short circuit.
2. The display panel according to claim 1, characterized in that: In the first direction, the sum of the sizes of two adjacent pads is greater than or equal to the size of the integrated circuit.
3. The display panel according to claim 1, characterized in that: The array substrate comprises a first switch unit, a second switch unit and a pixel unit, wherein one end of the first switch unit is connected to a first test signal, and the other end is connected to a data line of the pixel unit, one end of the second switch unit is connected to a second test signal, and the other end is connected to a gate line of the pixel unit, At most one of the first switch unit and the second switch unit is located in an array substrate region corresponding to the integrated circuit.
4. The display panel according to claim 3, characterized in that: The first switch unit is located in an array substrate region corresponding to the integrated circuit, and the second switch unit is located in a non-display region of the display panel, excluding the array substrate region corresponding to the integrated circuit.
5. The display panel according to claim 3, characterized in that: The second switch unit is located in an array substrate region corresponding to the integrated circuit, and the first switch unit is located in a non-display region of the display panel, excluding an array substrate region corresponding to the integrated circuit.
6. The display panel according to claim 3, characterized in that: The first switch unit and the second switch unit are both located in a non-display area of the display panel, excluding an array substrate area corresponding to the integrated circuit.
7. The display panel according to claim 4 or 6, characterized in that: The display panel further comprises an electronic ink film, and the electronic ink film is attached to a side of the array substrate on which the integrated circuit is arranged. The second switch unit is located in the non-display area of the display panel, which is the area covered by the electronic ink film; the display area of the display panel is within the area covered by the electronic ink film.
8. The display panel according to claim 5 or 6, characterized in that: The display panel includes an electronic ink film, and the electronic ink film is attached to a side of the array substrate where the integrated circuit is arranged. The first switch unit is located in a non-display area of the display panel, except for an area covered by the electronic ink film and an area corresponding to the integrated circuit; the display area of the display panel is within the area covered by the electronic ink film.
9. The display panel according to claim 8, characterized in that: The first switch unit includes a plurality of switch transistors, and the plurality of switch transistors are located in a wiring region of a data line of the pixel unit and are staggeredly distributed between the data lines.
10. A display device, characterized in that: The display device includes a display panel as described in any one of claims 1-9.