Chip verification method, device and medium

Abstract

The present invention provides a chip verification method, device and medium, belonging to the field of data processing. The present invention can verify the functions of the modules by dividing the modules in the design under test DUT, improve the completeness of data path verification, reduce the dependence of verification between data path levels, and accelerate the verification rate of the data path in parallel. By instantiating a general verification component in the verification environment Env in the test platform, the reusability of the verification environment Env is improved. The method adopts the method of verifying the output of the data path module in the design under test DUT and verifying the module data write-back, which accelerates the verification progress, improves the completeness of verification, and is also conducive to the problem location and debugging of the design under test DUT and the verification environment Env.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of data processing, and in particular to a chip verification method, device and medium. Background Art

[0002] Chip functional verification usually involves placing the design under test (DUT) into the testbench and verifying it through test cases. At present, the mainstream verification language is SystemVerilog, and the verification methodology is the Universal Verification Methodology (UVM). A testbench usually consists of two parts: the verification environment Env and the design under test DUT. The input and output interfaces of the design under test DUT are connected to the verification environment ENV. Usually, the design under test DUT is functionally tested as a whole, and there is no separate or combined testing for each module in the design under test DUT. This will increase the difficulty of verification, reduce verification efficiency, and extend the verification cycle.

[0003] Therefore, how to improve the efficiency of chip function verification is an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a chip verification method, device and medium, so as to at least partially solve the above-mentioned problems.

[0005] According to one aspect of the present invention, a chip verification method is provided, comprising:

[0006] The DUT is divided into multiple data paths, and each data path is divided into multiple modules that are cascaded in sequence.

[0007] The input interface of each data path of the design DUT to be tested is connected to the corresponding universal verification component UVC.

[0008] Connect the output interface of the module to be tested to the corresponding universal verification component UVC, generate stimulus through the sequence verification component of the universal verification component UVC corresponding to the data path input interface, and verify the data of the output interface of the module.

[0009] The output interface may be an output interface of a module Module on a data path, or an output interface of a module Module where data generated by modules Modules in different data paths are combined into data of one data path through a first multiplexer MUX.

[0010] In some embodiments, the method further includes, before the overall functional design of the design DUT to be tested is completed, connecting the corresponding universal verification component UVC through the output interface of the module Module in the data path to perform functional verification on the output of the module in the data path.

[0011] In some embodiments, the method also includes that the sequence verification component of the universal verification component UVC corresponding to the data path input interface generates stimulus, and the generation of stimulus can be the sequence verification component of the universal verification component UVC of one data path generating stimulus, or the sequence verification components of the universal verification components UVC of different data paths generating stimulus at the same time.

[0012] In some embodiments, the method also includes setting a write-back point inside the module or at the output of each data path, and writing data back to the test platform verification environment through the write-back point. The test platform verification environment can perform functional verification of the completed functional design module through the written-back data.

[0013] In some embodiments, the method further includes selecting a write-back point for data write-back by selecting a channel through a second multiplexer at the write-back point of each data path.

[0014] In some embodiments, the method also includes that the write-back points of different data paths can select channels through a third multiplexer to select a write-back point for data write-back, or the write-back points of different data channels can independently perform data write-back.

[0015] In some embodiments, the method further includes, the output universal verification component UVC connected to the design under test DUT, instantiating a universal verification component for each data path output, including at least a reference model and a scoreboard verification component.

[0016] In some embodiments, the method further includes performing functional verification on the entire data path of the design DUT under test by connecting a universal verification component UVC of the design DUT under test.

[0017] In some embodiments, the method further includes performing functional verification on the entire data path of the DUT under test, and performing functional verification on the DUT under test in a test mode defined by an application scenario.

[0018] In some embodiments, the method also includes that each data path can be output independently of each other, or can be combined into one data path inside the DUT to be tested and then output.

[0019] In some embodiments, the method further includes, among the multiple cascade modules, data output of the preceding module is data input of the succeeding module.

[0020] In some embodiments, the method further includes that each data path of the design DUT to be tested may be a data path with consistent design logic or a data path with different design logic.

[0021] In some embodiments, the method further includes that each data path of the design DUT to be tested can be set to a bypass mode, and a module Module in each data path can also be set to a bypass mode.

[0022] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the steps in the method of any of the above embodiments by calling the computer program stored in the memory.

[0023] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program executes the steps in any of the above method embodiments when executed by a processor.

[0024] The present invention provides a chip verification method, device and medium. By dividing the modules in the design under test DUT, the functions of the modules can be verified, the completeness of the data path verification is improved, the dependence of the verification between the data path levels is reduced, and the verification rate of the data path is accelerated in parallel. By instantiating the universal verification components (UVC) in the verification environment Env in the test platform, the reusability of the verification environment Env is improved. The method adopts the method of verifying the output of the data path module in the design under test DUT and verifying the module data write-back, which accelerates the verification progress, improves the completeness of the verification, and is also conducive to the problem location and debugging of the design under test DUT and the verification environment Env. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a chip verification method provided in an embodiment of the present application.

[0026] Figure 2 A schematic diagram of the structure of the DUT designed to be tested provided in an embodiment of the present application.

[0027] Figure 3 A schematic diagram of data output verification of the DUT module under test provided in an embodiment of the present application.

[0028] Figure 4 A schematic diagram of the verification of the data write-back channel of the DUT module under test provided in an embodiment of the present application.

[0029] Figure 5 A schematic diagram of the data path verification of the design under test (DUT) provided in an embodiment of the present application.

[0030] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] It should be noted that, in the description of the present invention, the directions or positional relationships indicated by the terms "up", "down", "left", "right", "front", "back", etc. are descriptions of the structure of the present invention based on the accompanying drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0033] The "first" and "second" in this technical solution are only used to distinguish the names of the same or similar structures, or corresponding structures with similar functions, and are not an arrangement of the importance of these structures, nor do they have a ranking, comparison of size, or other meanings.

[0034] In addition, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be a connection between the two structures. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood based on the overall idea of ​​the present invention and the specific context of the present solution.

[0035] The present application embodiment provides a chip verification method. Specifically, please refer to Figure 1 The basic implementation process of this embodiment is as follows:

[0036] Step S1, dividing the design DUT to be tested into multiple data paths, and dividing each data path into multiple modules cascaded in sequence.

[0037] like Figure 2As shown in the figure, the DUT under test of the test platform includes multiple data paths, and each data path includes multiple modules. Among them, each data path can output independently from each other, or it can be combined into one data path inside the DUT under test and then output; each data path includes multiple modules, and the data output of the previous module is the data input of the next module.

[0038] In some embodiments, each data path of the DUT under test in the test platform can be a data path with consistent design logic or a data path with different design logic. Each data path can be set to bypass mode, and the module in each data path can also be set to bypass mode, and the data can be directly output without any functional verification logic. Different data path outputs can be selected to be output from one data path alone, or different data paths can be selected to be output alone, or multiple data paths can be output simultaneously.

[0039] like Figure 2 As shown, the test platform design DUT to be tested includes M data paths {data path 1, data path 2, …, data path m, …, data path M}, where data path m is the mth data path, and the value range of m is 1 to M; each data path includes N modules Module {module Modulem_1, module Mdulem_2, …, module Modulem_n, …, module Modulem_N}, where module Modulem_n is the mth module Module of the mth path, and the value range of n is 1 to N.

[0040] Step S2, the input interface of each data path of the design DUT to be tested is connected to the corresponding universal verification component UVC.

[0041] The data input interface of the module Module1_1 of the data path 1 is connected to the universal verification component UVC of the data path 1, and the sequence Sequence of the universal verification component UVC of the data path 1 generates data to the input of the module Module1_1 of the data path 1.

[0042] Step S3, connecting the output interface of the module to be tested to the corresponding universal verification component UVC, generating a stimulus through the sequence verification component of the universal verification component UVC corresponding to the data path input interface, and verifying the data of the output interface of the module Module.

[0043] In some embodiments, the sequence Sequence verification component of the universal verification component UVC of the data path input interface generates excitation, which can be the sequence Sequence verification component of the universal verification component UVC of one data path, or the sequence Sequence verification components of the universal verification components UVC of different data paths generate excitation at the same time. The sequence Sequence data generated by the universal verification component UVC of data path M can be given to the module ModuleM_1 of data path M, or it can be given to the module Modulem_1 of data path m through MUX selection, and m≠M. At the same time, the sequence Sequence verification components of the universal verification components UVC of multiple data paths generate excitations at the same time and give them to the corresponding data path modules Modulem_1, m=1~M.

[0044] Taking image processing as an example, the designed DUT to be tested includes M image data processing data paths, and each data path includes N modules.

[0045] As a specific embodiment, the number of data paths of the design DUT to be tested is M=4, and the number of modules contained in each data path is N=4, that is, the input image data can be processed in four ways. Among them, module ModuleM_1 performs normalization processing on the image data; module ModuleM_2 performs convolution multiplication processing on the image data; module ModuleM_3 performs convolution addition processing on the image data; module ModuleM_4 performs format conversion processing on the image data. Each data path can be output independently of each other, or it can be output after being merged into one data path inside the design DUT to be tested; each data path contains multiple modules, and the data output of the previous module Module is the data input of the next module Module. The four data paths can be independent of each other, and each data path can be output independently after being processed by the four modules Module. The image data of data path 1 is processed by modules Module1_1, Module1_2, Module1_3, and Module1_4 of data path 1 and then output from Module1_4; similarly, the image data of data path 2 is finally output from Module2_4; the image data of data path 3 is finally output from Module3_4; and the image data of data path 4 is finally output from Module4_4. The image data of data paths 1 and 2 can be merged inside the design DUT to be tested and finally output from module Module1_4 of data path 1; the image data of data paths 3 and 4 can be merged inside the design DUT to be tested and finally output from module Module2_4 of data path 2. The four modules in each data path input the image data to module ModuleM_1 of data path M for processing and output, transmit it to module ModuleM_2 for processing and output, transmit it to module ModuleM_3 for processing and output, and finally transmit it to module ModuleM_4 for processing and output.

[0046] In some embodiments, each data path of the design DUT to be tested in the test platform can be a data path with consistent design logic or a data path with different design logic. The four data paths can be data paths with consistent design logic, each of which includes four modules, and the design logic of each module is exactly the same. For the sake of usage scenarios, each data path of the design DUT to be tested can also be a data path with different design logic. As a specific embodiment, data path 1 and data path 2 of the four data paths each include four modules, while data path 3 and data path 4 include less than four modules, for example, only one module, module Module3_4 and module Module4_4.

[0047] Each data path can be set to bypass mode, and the modules in each data path can also be set to bypass mode, and choose to output the data directly without any functional logic. Bypass mode means that when the data passes through a module, the input format of the module is directly maintained, no functional operation is performed on it, and it is directly output from the module to the next module. For example, when the image data of data path 1 enters module Module1_1, it is not normalized and is directly output from module Module1_1 to module Module1_2; module Module1_2 and module Module1_3 perform convolution multiplication and convolution addition operations and then output to module Module1_4; module Module1_4 does not perform format conversion processing and is directly output to the next stage.

[0048] In some embodiments, different data path outputs can be selected to be outputted from one data path alone, or different data paths can be selected to be outputted from different data paths alone, or multiple data paths can be outputted simultaneously. For example, the image data of data path 1 is processed by module Module1_1, module Module1_2, module Module1_3, and module Module1_4 of data path 1, and finally outputted from module Module1_4 to the next stage. As a flexible configuration, the image data of data path 1 can be selected to be outputted from one of module Module2_4 of data path 2, module Module3_4 of data path 3, or module Module4_4 of data path 4 to the next stage after being processed by module Module1_4. The different data path outputs can be selected to be outputted from multiple data paths simultaneously. Usually, the image data of data path 1 can be selected to be outputted from four modules Module, namely, module Module1_4 of data path 1, module Module2_4 of data path 2, module Module3_4 of data path 3, and module Module4_4 of data path 4 simultaneously after being processed by module Module1_4.

[0049] In some embodiments, Figure 3As shown, the data output verification block diagram of the DUT module to be tested. Before the overall functional design of the DUT to be tested is completed, the output interface of the module Module in the data path is connected to the corresponding universal verification component UVC, and the output of the module in the data path is functionally verified. The sequence Sequence of the universal verification component UVC of the data path M generates data to the module ModuleM_1 of the data path M. The output interface of the module ModuleM_N of the data path M is connected to the universal verification component UVC of the module ModuleM_N of the test platform Test Bench to check the correctness of the data function.

[0050] Take the number of data paths of the design DUT to be tested as M=4 as an example. The data input interface of the module Module1_1 of the data path 1 is connected to the universal verification component UVC of the data path 1, and the sequence Sequence of the universal verification component UVC of the data path 1 generates image data to the input of the module Module1_1 of the data path 1. The output interfaces of the modules Module1_1 and Module1_3 of the data path 1 are respectively connected to the universal verification components UVC of the modules Module1_1 and UVC of the module Module1_3 of the test platform Test Bench, so as to check the correctness of the normalization processing function of the module Module1_1 of the data path 1 and the correctness of the convolution multiplication and addition operation processing functions.

[0051] The stimulus generated by the sequence verification component of the universal verification component UVC of data path 1 can be given to the module Module1_1 of data path 1, and can also be given to the module Module2_1 of data path 2, the module Module3_1 of data path 3, and the module Module4_1 of data path 4 through MUX. When the sequence verification components of the universal verification components UVC of the four data paths generate stimulus at the same time, the universal verification component UVC of data path 1 is connected to the module Module1_1 of data path 1; the universal verification component UVC of data path 2 is connected to the module Module2_1 of data path 2; the universal verification component UVC of data path 3 is connected to the module Module3_1 of data path 3; and the universal verification component UVC of data path 4 is connected to the module Module4_1 of data path 4. At this time, the stimulus generated by the sequence verification component of the universal verification component UVC of data path 1 is given to the module Module1_1 of data path 1; the stimulus generated by the sequence verification component of the universal verification component UVC of data path 2 is given to the module Module2_1 of data path 2; the stimulus generated by the sequence verification component of the universal verification component UVC of data path 3 is given to the module Module3_1 of data path 3; the stimulus generated by the sequence verification component of the universal verification component UVC of data path 4 is given to the module Module4_1 of data path 4.

[0052] In some embodiments, the data of the output interface of the module Module is verified, which can be the output interface of the module Module on a data path, or the output interface of the module Module generated by the module Module between different data paths and merged into the data of a data path. The output interface of the module Modulem_n of the data path m is connected to the universal verification component UVC of the module Modulem_n for data verification; or the output interface of the module Modulex_y of the data path x is merged to the output interface of the module Modulem_n of the data path m by MUX, and connected to the universal verification component UVC of the module Modulem_n for data verification. For example, the output interface of the module Module1_3 of the data path 1 is connected to the universal verification component UVC of the module Module1_3 to verify the data after the convolution addition operation. The output interface of the module Module2_3 of the data path 2 can be merged to the output interface of the module Module1_3 of the data path 1 through MUX, and connected to the universal verification component UVC of the module Module1_3 to perform the convolution addition operation on the data of the module Module2_3 of the data path 2.

[0053] In some embodiments, the test platform verification environment can perform functional verification of the completed functional design module through the write-back data function of the module in the design DUT to be tested. The functional verification diagram of the write-back channel is shown in FIG. Figure 4 As shown. The write-back data function of the module in the design under test DUT can set a write-back point inside or at the output of a module Module of a data path to write data back to the test platform verification environment. The internal data of the module Modulem_n of the data path m can be selected not to be output to the subsequent module Module through the output interface, but to be written back to the universal verification component UVC of the data path m through the debug channel for data inspection.

[0054] For example, taking the number of data paths as M=4, the result of the convolution addition operation of the module Module1_3 of the data path 1 is not output to the subsequent module Module1_4 through the output interface of the module Module1_3, but is directly written back to the universal verification component UVC of the data path 1 through the debug write-back path for data inspection. In this data write-back path, the software can debug the function of the module Module.

[0055] In some embodiments, the write-back point inside or output of a module of a data path will select a write-back point for data write-back through the MUX selection channel, and multiple write-back points will select a write-back point for data write-back. The write-back points of different data paths can select a write-back point for data write-back through the MUX selection channel; or the write-back points of different data channels can independently write data back. There are multiple modules Module in the data path m, and the module Modulem_n can be selected as the data write-back. The module Modulem_y in the data path m can also be used as the data write-back. The data write-back of the module Modulem_n and the module Modulem_y will be selected through the MUX selection channel for write-back. The data write-back of the module Module in the data path x can choose to perform MUX selection write-back with the module Module of the data path m, or it can be written back from the write-back path of the data path x without MUX selection. For example, both modules Module1_1 and Module1_3 of data path 1 need to write back data. The data write back of modules Module1_1 and Module1_3 will select one module for data write back through data MUX. For example, module Module1_3 is selected for data write back. At this time, module Module1_1 will not be able to write back data. Module2_1 and module Module2_3 of data path 2 also need to write back data. The data of modules Module2_1 and module Module2_3 can be selected with the data write back of modules Module1_1 and module1_3 of data path 1 through MUX to select one module for data write back, or can be selected by MUX to write back data independently from the debug write back path of data path 2.

[0056] In some embodiments, the data of the data path write-back point is written back to the data path universal verification component UVC, and then the written-back data is compared with the reference data Golden Data to check the correctness of the data path function. The data written back by the debug write-back path will be stored in the cache model Memory Model of the data path universal verification component UVC. The test platform reads the data from the backdoor of the cache model Memory Model of the data path universal verification component UVC and compares it with the reference data Golden Data to verify the correctness of the data path module Module function.

[0057] In some embodiments, by connecting the universal verification component UVC of the design DUT to be tested, the entire data path of the design DUT to be tested is functionally verified. The schematic diagram of the data path verification of the design DUT to be tested is shown in FIG. Figure 5After the overall function of the design DUT to be tested is completed, the data path m universal verification component UVC is connected through the data path m module Modulem_1 input interface, and the data path m module Modulem_N output interface is connected to the data path m universal verification component UVC.

[0058] For example, taking the number of data paths as M=4, the module Module1_1 input interface and the module Module1_4 output interface of data path 1 are connected to the data path 1 universal verification component UVC; the module Module2_1 input interface and the module Module2_4 output interface of data path 2 are connected to the data path 2 universal verification component UVC; the module Module3_1 input interface and the module Module3_4 output interface of data path 3 are connected to the data path 3 universal verification component UVC, and the module Module4_1 input interface and the module Module4_4 output interface of data path 4 are connected to the data path 4 universal verification component UVC.

[0059] Accordingly, an embodiment of the present application further provides an electronic device, which may be a terminal or a server. Figure 6 As shown, Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0060] The electronic device 600 includes a processor 601 having one or more processing cores, a memory 602 having one or more computer-readable storage media, and a computer program stored in the memory 602 and executable on the processor. The processor 601 is electrically connected to the memory 602. Those skilled in the art will appreciate that the electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0061] The processor 601 is the control center of the electronic device 600. It uses various interfaces and lines to connect various parts of the entire electronic device 600, and executes various functions of the electronic device 600 and processes data by running or loading software programs (computer programs) and / or units stored in the memory 602, and calling data stored in the memory 602, thereby monitoring the electronic device 600 as a whole.

[0062] In an embodiment of the present application, the processor 601 in the electronic device 600 will load the instructions corresponding to the processes of one or more applications into the memory 602 according to the following steps, and the processor 601 will run the applications stored in the memory 602 to implement various functions.

[0063] Optional, such as Figure 6As shown, the electronic device 600 further includes: a chip verification module 603, a communication module 604, an input unit 605 and a power supply 606. The processor 601 is electrically connected to the chip verification module 603, the communication module 604, the input unit 605 and the power supply 606 respectively. Those skilled in the art can understand that Figure 6 The electronic device structure shown in the figure does not constitute a limitation of the electronic device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0064] The chip verification module 603 may be used to implement functional verification of the chip.

[0065] The communication module 604 may be used to communicate with other devices.

[0066] The input unit 605 may be used to receive input numbers, character information or user feature information (such as fingerprint, iris, facial information, etc.), and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control.

[0067] The power supply 606 is used to supply power to various components of the electronic device 600. Optionally, the power supply 606 can be logically connected to the processor 601 through a power management system, so that the power management system can manage charging, discharging, and power consumption. The power supply 606 can also include one or more DC or AC power supplies, recharging systems, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0068] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0069] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0070] To this end, an embodiment of the present application provides a computer-readable storage medium, in which multiple computer programs are stored, and the computer program can be loaded by a processor to execute the steps of a chip verification method provided in an embodiment of the present application. For example, the computer program can execute the following steps:

[0071] The DUT is divided into multiple data paths, and each data path is divided into multiple modules that are cascaded in sequence.

[0072] The input interface of each data path of the design DUT to be tested is connected to the corresponding universal verification component UVC.

[0073] Connect the output interface of the module to be tested to the corresponding universal verification component UVC, generate stimulus through the sequence verification component of the universal verification component UVC corresponding to the data path input interface, and verify the data of the output interface of the module.

[0074] The output interface may be an output interface of a module Module on a data path, or an output interface of a module Module where data generated by modules Modules in different data paths are combined into data of one data path through a first multiplexer MUX.

[0075] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0076] The computer-readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0077] Since the computer program stored in the storage medium can execute the steps in any one of the methods for locating an error in a test program based on the Emulation platform provided in the embodiments of the present application, the beneficial effects that can be achieved by any one of the methods for locating an error in a test program based on the Emulation platform provided in the embodiments of the present application can be achieved. For details, please refer to the previous embodiments and will not be repeated here.

[0078] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0079] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0080] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0081] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A chip verification method, characterized in that: The method comprises: The DUT is divided into multiple data paths, and each data path is divided into multiple modules that are cascaded in sequence. The input interface of each data path of the design DUT to be tested is connected to the corresponding universal verification component UVC. Connect the output interface of the module to be tested to the corresponding universal verification component UVC, generate stimulus through the sequence verification component of the universal verification component UVC corresponding to the data path input interface, and verify the data of the output interface of the module. The output interface is an output interface of a module Module on a data path, or an output interface of a module Module in which data generated by modules Modules in different data paths are combined into data of one data path through a first multiplexer MUX; The sequence verification component of the universal verification component UVC corresponding to the data path input interface generates excitation, and the excitation generation means that the sequence verification component of the universal verification component UVC of one data path generates excitation, or the sequence verification components of the universal verification components UVC of different data paths generate excitation at the same time.

2. The method according to claim 1, characterized in that: Before the overall functional design of the design DUT to be tested is completed, the output interface of the module Module in the data path is connected to the corresponding universal verification component UVC to perform functional verification on the output of the module in the data path.

3. The method according to claim 1, characterized in that: A write-back point is set inside the module or at the output of each data path, and data is written back to the test platform verification environment through the write-back point. The test platform verification environment performs functional verification of the completed functional design module through the written-back data.

4. The method according to claim 3, characterized in that: The write-back point of each data path selects a channel through a second multiplexer, and selects a write-back point for data write-back.

5. The method according to claim 3, characterized in that: The write-back points of different data paths select channels through a third multiplexer, and select a write-back point to write data back, or the write-back points of different data paths write data back independently.

6. The method according to claim 1, characterized in that: The output universal verification component UVC connected to the design under test DUT instantiates the universal verification component output by each data path, and at least includes a reference model and a scoreboard verification component.

7. The method according to claim 1, characterized in that: By connecting the universal verification component UVC of the design DUT to be tested, the entire data path of the design DUT to be tested is functionally verified.

8. The method according to claim 7, characterized in that: The entire data path of the design DUT under test is functionally verified, and the design DUT under test is functionally verified in a test mode defined by an application scenario.

9. The method according to any one of claims 1 to 7, characterized in that: Each data path is output independently of each other, or is combined into one data path within the DUT and then output.

10. The method according to any one of claims 1 to 7, characterized in that: For the plurality of modules cascaded in sequence, the data output of the preceding module serves as the data input of the succeeding module.

11. The method according to any one of claims 1 to 7, characterized in that: Each data path of the design DUT to be tested is a data path with consistent design logic, or a data path with different design logic.

12. The method according to any one of claims 1 to 7, characterized in that: Each data path of the design DUT to be tested is set to the bypass mode, and each module in the data path is set to the bypass mode.

13. An electronic device, characterized in that: It comprises a memory storing executable program code and a processor coupled to the memory; wherein the processor calls the executable program code stored in the memory to execute the method according to any one of claims 1-12.

14. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 12 is performed.

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