Data processing system and method for interconnection of FPGA (Field Programmable Gate Array) and MCU (Microprogrammed Control Unit)

Abstract

The invention is suitable for the technical field of MCU and FPGA communication, and provides an FPGA and MCU interconnection data processing system and method, and the system comprises an MCU, an FPGA device, and a DDR memory. Wherein the address space of the MCU is mapped with the data address of the DDR memory, the MCU is connected and communicated with the FPGA equipment through a Localbus, the MCU controls the FPGA to work and operate, and the FPGA equipment is connected and communicated with the DDR memory through a DDR interface; and the MCU performs data reading operation on the DDR memory through the FPGA equipment. The communication between the FPGA equipment and the MCU is realized through the Localbus of the MCU, the MCU controls the FPGA to work and run, and the storage address of the DDR memory is mapped to the storage address space of the MCU, so that the FPGA equipment can operate the data of the DDR memory by using the address mapping mode of the MCU, the operation is simple and convenient, the flexibility is high, the data operation of the DDR memory can be realized on the basis of the existing system architecture, and the cost is low. Therefore, the data processing efficiency is improved, and the application space of the FPGA and the MCU can be expanded.

Description

Technical Field

[0001] The present invention relates to the technical field of MCU and FPGA communication, and in particular to a data processing system and method. Background Art

[0002] Double Data Rate (DDR) memory is known for its double data rate, which can significantly improve data transmission efficiency. With the rapid development of DDR memory technology, higher requirements are put forward for the microcontroller (MCU) control field, especially in the field of image processing, which requires MCU to access the data of DDR memory.

[0003] However, there is no dedicated DDR interface in the traditional MCU architecture, and a control chip is required to access the DDR memory. For example, in order to facilitate access to the data of the DDR memory, the MCU and programmable logic devices, such as Field Programmable Gate Array (FPGA), need to be integrated into a System on Chip (SoC). The System on Chip uses programmable hardware resources to enable the MCU to access the data of its external DDR memory. However, this type of method must change the existing architecture. Currently, most of the FPGA and MCU are integrated into the System on Chip SoC to access the FPGA's DDR memory, which is less flexible and difficult to apply to the existing independent system architecture, making it difficult for the MCU to access the FPGA's DDR memory, resulting in a limited application range of the system. Summary of the invention

[0004] The present invention provides a data processing system and method for interconnecting FPGA and MCU, so as to solve the problem that the existing integrated on-chip system accesses DDR memory in a way that is less flexible and difficult to be applied to the existing mutually independent system architecture, resulting in a limited application range of the system.

[0005] In a first aspect, an embodiment of the present application provides a data processing system in which an FPGA and an MCU are interconnected, including an MCU, an FPGA device, and a DDR memory, wherein the address space of the MCU is mapped with a data address of the DDR memory;

[0006] The MCU communicates with the FPGA device through the Localbus bus, and the FPGA device communicates with the DDR memory through the DDR interface;

[0007] The MCU reads data from the DDR memory through the FPGA device.

[0008] Optionally, the FPGA device includes an SRAM, and the SRAM is used to synchronize data of the DDR memory;

[0009] After writing data to the DDR memory, the FPGA device stores the data written in the DDR memory to the SRAM when the MCU has a read request, and keeps the data address and content of the DDR memory consistent with that of the SRAM.

[0010] Optionally, performing a data reading operation on the DDR memory through the FPGA device includes:

[0011] MCU sends a data read signal to the FPGA device via the Localbus;

[0012] After receiving the data read signal sent by the MCU through the Localbus bus, the FPGA device performs a data read operation on the DDR memory according to the data read address of the data read signal, and feeds back the read target data to the MCU through the Localbus bus.

[0013] Optionally, performing a data reading operation on the DDR memory according to the data reading address of the data reading signal, and feeding back the read target data to the MCU via the Localbus bus, including:

[0014] When the data at the data read address is not stored in the SRAM of the FPGA device, the data of the DDR memory is stored in the SRAM of the FPGA device by burst writing, and the data address and content of the DDR memory and the SRAM are kept consistent;

[0015] When the data at the data read address is stored in the SRAM, the data corresponding to the data read address in the SRAM is directly read to obtain the target data, and the target data is fed back to the MCU through the Localbus bus.

[0016] Optionally, the FPGA device includes generating some registers, and the address space of the MCU is mapped with data addresses of the registers on the FPGA device to perform read and write operations on the registers;

[0017] The MCU accesses the registers of the FPGA device through the Localbus bus and performs data operations on the registers by address mapping to achieve the purpose of controlling some peripheral devices implemented on the FPGA device.

[0018] Optionally, the data processing system in which the FPGA and MCU are interconnected further includes at least one peripheral device. Some peripheral devices are generated on the FPGA, and the FPGA is connected to specific chips, such as an Rx / Txsensor chip, through these peripheral device buses; the FPGA device writes the data generated by the peripheral device into the DDR memory, so that the MCU performs data read operations on the DDR memory through the FPGA device.

[0019] Optionally, the peripheral device is a SPI device.

[0020] Optionally, the register stores configuration parameters of the peripheral device;

[0021] The MCU performs data operations on the configuration parameters of the peripheral devices in the registers of the FPGA device through the Localbus bus to control multiple peripheral devices generated by the FPGA.

[0022] In a second aspect, an embodiment of the present application provides a data processing method for interconnecting an FPGA and an MCU, which is applied to an FPGA device in a data processing system for interconnecting an FPGA and an MCU, wherein the data processing system for interconnecting an FPGA and an MCU further includes an MCU and a DDR memory, wherein the address space of the MCU is mapped with a data address of the DDR memory, the MCU is connected to and communicates with the FPGA device via a Localbus bus, and the FPGA device is connected to and communicates with the DDR memory via a DDR interface; the method includes:

[0023] After receiving the data read signal from the MCU through the Localbus bus, a data read operation is performed on the DDR memory according to the data read address of the data read signal, and the read target data is fed back to the MCU through the Localbus bus.

[0024] In a third aspect, an embodiment of the present application provides a data processing method for interconnecting an FPGA and an MCU, which is applied to an MCU in a data processing system for interconnecting an FPGA and an MCU, wherein the data processing system for interconnecting an FPGA and an MCU further includes an FPGA device and a DDR memory, wherein the address space of the MCU is mapped with a data address of the DDR memory, the MCU is connected to and communicates with the FPGA device via a Localbus bus, and the FPGA device is connected to and communicates with the DDR memory via a DDR interface; the method includes:

[0025] Sending a data read signal to the FPGA device via the Localbus bus, so that the FPGA device performs a data read operation on the DDR memory according to the data read address of the data read signal, and feeds back the read target data;

[0026] Receive the target data sent by the FPGA device through the Localbus bus.

[0027] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a memory, an FPGA, and an FPGA program stored in the memory and executable on the FPGA. When the FPGA executes the FPGA program, the functions of the data processing system for interconnecting the FPGA and the MCU, or the steps of the data processing method for interconnecting the FPGA and the MCU, are implemented.

[0028] In one solution provided by the data processing system and method for interconnecting FPGA and MCU, the data processing system for interconnecting FPGA and MCU includes MCU, FPGA device and DDR memory; wherein the address space of MCU is mapped with the data address of DDR memory, MCU is connected and communicated with FPGA device through Localbus bus, and FPGA device is connected and communicated with DDR memory through DDR interface; MCU performs data reading operation on DDR memory through FPGA device. Communication between FPGA device and MCU is realized through Localbus bus of MCU, and storage address of DDR memory is mapped to storage address space of MCU, so that FPGA device can operate data of DDR memory by address mapping of MCU, which is simple, convenient and flexible, and data operation of DDR memory can be realized on existing system architecture, thereby improving data processing efficiency and expanding application space of FPGA and MCU. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0030] Figure 1 It is a structural schematic diagram of a data processing system of the present invention in which FPGA and MCU are interconnected;

[0031] Figure 2 It is a timing diagram of the present invention performing a write operation via the Localbus bus;

[0032] Figure 3 It is a timing diagram of the present invention performing a read operation via the Localbus bus;

[0033] Figure 4 It is a control schematic diagram of a DDR controller in an FPGA device of the present invention;

[0034] Figure 5It is a structural schematic diagram of an embodiment of a data processing system in which an FPGA and an MCU are interconnected according to the present invention;

[0035] Figure 6 It is a specific data diagram read by the MCU through the FPGA device in one embodiment of the present invention;

[0036] Figure 7 It is a signaling interaction diagram of a data processing method for interconnecting FPGA and MCU in one embodiment of the present invention;

[0037] Figure 8 is a structural schematic diagram of an FPGA device in one embodiment of the present invention;

[0038] Fig. 9 It is a display effect diagram of a piece of picture data in one embodiment of the present invention;

[0039] Fig.10 It is a specific data graph displayed by the editor in one embodiment of the present invention. DETAILED DESCRIPTION

[0040] The technical solution of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or their collections. It should also be understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0042] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0043] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0044] It should be understood that the order of execution of the steps in the following embodiments does not imply a precedence of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0045] In order to illustrate the technical solution of the present invention, specific embodiments are provided below for illustration.

[0046] The data processing method for interconnecting FPGA and MCU provided by the embodiment of the present invention can be applied in the following aspects: Figure 1 In the data processing system of interconnecting FPGA and MCU shown, the data processing system of interconnecting FPGA and MCU includes independent microcontroller MCU, FPGA device and DDR memory. Among them, registers are provided on the FPGA device, and the address space of the MCU maps the data address of the registers. The MCU is connected and communicated with the FPGA device through the Localbus bus. The MCU can access the internal registers on the FPGA device through address mapping to realize data read, write and read operations on the registers, thereby expanding the application space of the MCU or FPGA device.

[0047] Among them, the Localbus bus is a data bus with parallel address and data. Specifically, when the MCU and the FPGA device communicate through the Localbus bus, the direct transmission signals between the MCU and the FPGA device include the chip select signal CSn, the address valid signal NADV, the write signal (data write signal) WRn or the read signal (data read signal) RDn. According to the changes of the above signals, the FPGA device latches the address bus AB and the data bus DB between the MCU and the FPGA device, determines the write data and the write address, and then realizes the data writing and reading of the DDR memory. According to the changes of the above signals, the MCU latches the data bus DB, captures the data fed back by the FPGA device, and realizes the data reading of the DDR memory.

[0048] When the MCU needs to write data to the register on the FPGA device, the signals between the FPGA device and the MCU include the chip select signal CSn, the address valid signal NADV and the write signal WRn. At this time, the FPGA device can determine that it has received the data write signal from the MCU, and the FPGA device determines the writing timing based on the chip select signal CSn and the address valid signal NADV. The timing diagram of the write operation is shown in the figure below. Figure 2 As shown, the chip select signal CSn changes from high level to low level, the address valid signal NADV changes from high level to low level, and the data write operation starts. Among them, NADV is the address and data multiplexing selection flag signal. At the rising edge of the address valid signal, the low bit of the address (Address) on the data bus DB and the high bit on the address bus AB are latched, thereby latching the address (Address); then, the data is latched at a preset time after the falling edge of the write signal WRn to complete the data write operation. By detecting the falling edge of the write signal WRn, the data is latched after a delay of some beats to complete the write operation and ensure the integrity of the data write.

[0049] When the MCU needs to read the data on the register or DDR memory on the FPGA device, the signals between the FPGA device and the MCU include the chip select signal CSn, the address valid signal NADV and the read signal RDn. At this time, the FPGA device can determine that it has received the data read signal from the MCU. The timing diagram of the read operation is shown in the figure below. Figure 3 As shown, when the chip select signal CSn changes from high level to low level, and the address valid signal NADV changes from high level to low level, it indicates that the read operation starts. The FPGA device latches the low address on the data bus DB and the high address on the AB address bus at the rising edge of the NADV signal, thereby latching the address to obtain the data read address for subsequent use. In this process, the MCU will always detect the signal change of the write signal RDn. The read signal RDn is at a low level, and the MCU waits for the FPGA device to feedback data; when the read signal RDn rises, the data is latched, that is, the target data returned by the FPGA device is captured, and the Localbus read operation is completed. Therefore, the FPGA device needs to prepare the data in advance. Our design is that as long as the MCU does not write to the FPGA device, it is considered that the MCU is reading data. This means that the read data must be prepared at all times at other times.

[0050] in, Figures 1 to 3 The 1-10 in represents the time. Figures 1 to 3 The data bus DB[15,0] indicates that it is a 16-bit data bus, 15 represents the most significant bit, and 0 represents the least significant bit; the address bus AB[23,16] represents an address range, where 23 is the high-order address and 16 is the low-order address.

[0051] Among them, the high 8-bit physical address (i.e. Address[23:8]=0) and the low 16-bit physical address (i.e. 16-bit Address[15:0]) in the MCU can be mapped to the data address range of the register. That is, the register read and write operations are determined according to the address on the Localbus bus. When the address high 8-bit Address[23:8]=0, the 64K byte range addressed by the low 16-bit Address[15:0] is the data address range of the register. When WRn or RDn is low and effective, the corresponding register address is written or read, and the written or read data appears in Figure 2 or Figure 3 The DB[15:0] data bus of the MCU is connected to the MCU.

[0052] In this embodiment, by means of address mapping, the specific address range of the FPGA device can be mapped to the address space of the MCU, so that the MCU can directly access the registers inside the FPGA device. This method simplifies the data exchange process between the FPGA device and the MCU, and improves the overall performance and efficiency of the system. By means of the MCU's Localbus bus and address mapping, efficient communication between the FPGA device and the MCU can be achieved, meeting the requirements of real-time and scalability, while reducing the workload of software development and improving the overall performance and reliability of the system.

[0053] In one embodiment, the FPGA device is connected and communicated with the DDR memory through the DDR interface, that is, the DDR memory is mounted on the FPGA device. The address space of the MCU is mapped with the data address of the DDR memory. The MCU can be connected and communicated with the FPGA device through the Localbus bus. The FPGA device is connected and communicated with the DDR memory through the DDR interface, so that the MCU can use the address mapping method to access the DDR memory through the FPGA device and perform data reading operations on the DDR memory. Among them, when the Localbus bus address of the MCU maps the high 4M address space, it is the read address of the DDR memory. For example, in the embodiment, the 0x61C00000~0x61FFFFFF space is the read address of the DDR memory, that is, the high 4M address space on the MCU is the mapped data address of the DDR memory. For example, at this time, the address space of 0x61C00000~0x61FFFFFF on the MCU is the mapped data address of the DDR memory.

[0054] Specifically, when the MCU needs to read data from the DDR memory, the MCU sends a data read signal to the FPGA device through the Localbus bus. Since the address space of the MCU is mapped with the data address of the DDR memory, that is, the two addresses have a mapping relationship, after the FPGA device receives the data read signal, it can access the DDR memory through the DDR interface, and then perform a data read operation on the DDR memory according to the data read address of the data read signal to obtain the target data; the FPGA device will feed back the target data to the MCU through the Localbus bus. The MCU performs address latching and data latching on the target data fed back by the FPGA device through the Localbus bus to obtain the target data.

[0055] In this embodiment, the communication between the FPGA device and the MCU is achieved through the Localbus bus of the MCU, and the storage address of the DDR memory is mapped to the storage address space of the MCU, so that the FPGA device can use the address mapping method of the MCU to operate the data of the DDR memory. It is simple, convenient and flexible, and the data operation of the DDR memory can be implemented on the existing system architecture, thereby improving the efficiency of data processing.

[0056] In one embodiment, a data read operation is performed on a DDR memory through an FPGA device, specifically comprising the following steps: the MCU sends a data read signal to the FPGA device through the Localbus bus; after the FPGA device receives the data read signal sent by the MCU through the Localbus bus, the FPGA device performs a data read operation on the DDR memory according to the data read address of the data read signal, and feeds back the read target data to the MCU through the Localbus bus.

[0057] Among them, when the MCU needs to read the data on the DDR memory connected to the FPGA device, the signals between the FPGA device and the MCU include the chip select signal CSn, the address valid signal NADV and the read signal WRn. At this time, the FPGA device can determine that it has received the data read signal from the MCU. When the chip select signal CSn changes from a high level to a low level, and the address valid signal (NADV) changes from a high level to a low level, it indicates that the read operation starts. The FPGA device latches the address low bit on the data bus DB and the high bit on the AB address bus at the rising edge of the NADV signal, thereby latching the address to obtain the data read address for subsequent use. Then, the FPGA device accesses the DDR memory through the DDR interface, reads the corresponding data in the DDR memory according to the data read address, obtains the target data and feeds it back to the MCU through the Localbus bus. In this process, the MCU will always detect the signal change of the read signal RDn. The read signal RDn is at a low level, and the MCU waits for the FPGA device to feedback data; when the read signal RDn rises, the data is latched, that is, the target data returned by the FPGA device is captured, and the read operation of the Localbus bus is completed.

[0058] In one embodiment, the data processing system in which the FPGA and the MCU are interconnected further includes at least one peripheral device, and the FPGA device is connected and communicated with the peripheral device via a bus. When the peripheral device generates data, the data can be stored in the DDR memory here. Specifically, the FPGA device writes the data generated or transmitted by the peripheral device into the DDR memory, so that the MCU performs a data reading operation on the DDR memory through the FPGA device, thereby realizing access and reading of the data of the peripheral device, which is convenient for subsequent calls.

[0059] In one embodiment, the peripheral device further includes at least one SPI device, and the FPGA device is connected and communicated with the SPI device via the SPI bus. The FPGA device writes the data generated or transmitted by the SPI device into the DDR memory, so that the Localbus bus of the MCU performs a data reading operation on the DDR memory through the FPGA device, thereby accessing and reading the collected data of the SPI device, which is convenient for subsequent calls.

[0060] In one embodiment, if Figure 4As shown, a DDR controller is provided on the FPGA device, and the DDR controller of the FPGA device is connected to the DDR memory. The FPGA device uses the AXI (Advanced eXtensible Interface) 4-Full Matrix bus to connect to the DDR controller. When the FPGA device needs to write data collected by the SPI device, that is, when the control module of the FPGA device writes data to the DDR memory, the control module of the FPGA device will collect the data collected and transmitted by the SPI device. When the collected data reaches a certain data size (such as 256 bytes), the control module of the FPGA device will transmit it to the DDR controller through the AXI4-Full Matrix bus at one time in a burst write mode, and then write it to the DDR memory. In addition, when the control module of the FPGA device reads data from the DDR memory, the control module of the FPGA device controls the DDR controller to read data through the AXI4-FullMatrix bus, and then feeds back the read data to the MCU or writes it into the memory of the FPGA device, such as writing it into the SRAM for subsequent MCU reading.

[0061] The DDR controller is controlled by the AXI4 bus to read or write the storage unit of the DDR memory. It is suitable for various embedded systems and large data application scenarios, and improves data throughput and system performance.

[0062] In one embodiment, the DDR memory includes multiple data blocks of different data sizes, and the multiple data blocks are arranged in sequence. When the FPGA device writes the data collected and transmitted by the SPI device into the DDR memory, the FPGA device writes the data to be written into the current data block of the DDR memory in sequence through the DDR controller in a cyclic writing manner, and automatically controls the current block address until the multiple data blocks are full, and then re-circulates the data.

[0063] It is important to understand that due to the limited address space of Localbus, the memory of DDR memory must be divided into multiple data blocks. For example, a 128M DDR memory is divided into 32 data blocks, each of which is 4M. When storing image data, the size of a picture data is generally several M to more than 10 M. The DDR controller of the FPGA device automatically controls the address of the current data block. A picture can correspond to a data block, and a data block address is updated to achieve storage. Later, the MCU can access the entire 128M DDR memory resource in the form of data blocks, which is simple and convenient.

[0064] Among them, when writing the data to be written (such as the data collected and transmitted by the SPI device) into the DDR memory, the DDR controller needs to continuously receive the data to be written until the data to be written of the preset size is obtained, and writes it into the data block of the DDR memory in a burst writing manner at one time until all the data blocks are full, and then rewrites the data from the first data block. When writing data, the DDR controller needs to synchronously update the address of the data in the current data block according to the preset size. After the current data block is full, the DDR controller automatically switches the address of the new data block, that is, after each burst writing, the data address of the data block is increased by the preset size. After writing a data block, the data write address of the DDR memory is correspondingly increased by the size of a data block until all the data blocks are full.

[0065] For example, the DDR controller collects the data to be written to the DDR memory and makes up a certain size, such as 256 bytes. The starting write address of each group of data (each picture) is fixed, and the block data block is written in a burst manner, 256 bytes are written each time, and the address written to the DDR memory increases by 256 after each burst. After writing a block data block, the block data block address increases by 1, and the corresponding DDR memory data address also increases by the size of a block data block. After all the block data blocks are filled in sequence, the block data block address returns to 0, completing a complete write of the DDR memory, and then starts writing again from the starting address 0 of the DDR memory.

[0066] In this embodiment, by collecting a certain amount of data (such as 256 bytes) and then performing burst writing, the high bandwidth of the DDR memory can be fully utilized, the overhead of the write operation can be reduced, and the write efficiency can be improved. It is particularly suitable for caching and storing video image data or other large amounts of data. By dividing the data blocks and automatically controlling the address, the resources of the DDR memory can be effectively managed and utilized. In addition, the starting write address is fixed each time the data is written, and the write address and block address are automatically increased to ensure the continuity and integrity of the data writing, simplify the address management, and improve the reliability of the system. The cyclic writing method ensures the cyclic utilization of the DDR memory resources and improves the utilization rate of the DDR memory.

[0067] In one embodiment, the FPGA device includes an SRAM, which is a static random access memory (Static Random Access Memory). The SRAM memory is used to synchronize the data of the DDR memory. After the data is written to the DDR memory, such as after the data collected and transmitted by the SPI device is written to the DDR memory, the FPGA device stores the written data in the DDR memory synchronously to the SRAM memory, and keeps the data address and content of the DDR memory consistent with those of the SRAM memory. The data transfer of the DDR memory is realized through the SRAM of the FPGA device, which solves the problem of address mapping between the MCU address space and the DDR. By synchronizing the data in the DDR to the SRAM, when the MCU reads the data of the DDR memory later, it can read directly from the SRAM, taking advantage of the high speed of the SRAM, improving the efficiency of data access, and improving the overall system performance.

[0068] In one embodiment, a data read operation is performed on a DDR memory according to a data read address of a data read signal, and the read target data is fed back to the MCU via the Localbus bus, including: when the data of the data read address is stored in the SRAM memory of the FPGA device, the data corresponding to the data read address in the SRAM memory is directly read to obtain the target data; and the target data is fed back to the MCU via the Localbus bus. By caching the storage data of the DDR in the SRAM, the delay when the MCU reads the data can be reduced, and the real-time performance and response speed of the system can be improved.

[0069] In one embodiment, a data read operation is performed on the DDR memory according to the data read address of the data read signal, and the read target data is fed back to the MCU via the Localbus bus, including: when the data of the data read address is not stored in the SRAM memory of the FPGA device, the data of the DDR memory is stored in the SRAM memory of the FPGA device by burst burst reading, and the data address and content of the DDR memory and the SRAM memory are kept consistent; then, the data corresponding to the data read address in the SRAM memory is read to obtain the target data, and the target data is fed back to the MCU via the Localbus bus. By loading data from the DDR memory to the SRAM memory, the address space of the Localbus bus can be mapped to the storage space of the DDR memory, thereby improving the overall access efficiency of the system. The burst write / read method of the DDR memory can also write / read a large amount of data at one time, reducing the overhead of bus transmission.

[0070] In one embodiment, to avoid misreading data, when the MCU performs a data read operation on the DDR memory through the FPGA device, a virtual read operation needs to be performed, that is, after the MCU sends a data read signal to the FPGA device through the Localbus bus, the FPGA device needs to synchronously load the data of the DDR memory into the SRAM memory to keep the data address and content of the two consistent; then, determine to read the corresponding target data from the SRAM memory according to the data read address of the data read signal, and feed it back to the MCU through the Localbus bus. To avoid misreading data, after sending the data read signal, the MCU needs to wait for a preset time before reading the target data returned by the FPGA device to ensure that accurate and complete target data can be read.

[0071] For example, when the MCU is performing a data read operation through the FPGA device, in order to avoid reading the wrong content of the first 16-bit data, you can first perform a virtual read in the MCU code, so that the FPGA device can trigger the execution of a DDR memory read to SRAM operation, and then actually start to read the 16K bytes of SRAM data. After reading, if you want to read the next 16K bytes, you can do the same operation. In this way, the wrong data will not be read due to the SRAM data not being refreshed in time. When the MCU uses an emulator such as Jlink to debug and read through Memory operations, the first 16-bit data error is inevitable, but the overall size of 16K bytes of data, there are 2 bytes (16 bits) of data is wrong, which does not affect the overall situation. When the picture is displayed, the 2-byte error does not affect the normal display of the picture at all. Fig. 9 The following is the display effect of a picture data. Or, to go a step further, you can use the script of the MCU's JTAG ((Joint Test Action Group)) debugger, such as the Jlink script, to imitate the design of writing a program, and first read it virtually, so that no false or erroneous data will be read. In addition, when the FPGA device reads 16K bytes of data as a whole and writes it into the SRAM memory, it also reads 256 bytes at a time according to the burst read method until the entire 16K bytes are read.

[0072] In addition, each data block of the DDR memory is 4M bytes in size, so after the MCU reads one data block, it needs to trigger the FPGA device to perform 4096÷16=100 data read operations. Each time the data of the DDR memory is written to the SRAM memory, it also includes 16x1024÷256=64 busrt burst reads of the DDR memory data to complete the write.

[0073] In one embodiment, the register of the FPGA device stores the configuration parameters of each peripheral device (such as an SPI device), and the address space of the MCU maps the address of the register on the FPGA device. The MCU uses address mapping to perform data operations (such as write or read operations) on the configuration parameters of the peripheral device in the register of the FPGA device through the Localbus bus, thereby realizing the control of multiple SPI devices. The Localbus bus of the MCU is used to realize the communication between the FPGA device and the MCU, and the register data of the FPGA device can be operated by the address mapping method of the MCU, so that the peripheral device (such as an SPI device) generated and realized on the FPGA device can be manipulated, which is convenient and fast, greatly expanding the application space of the MCU or FPGA device, and easy to expand to support more peripherals.

[0074] The SPI device in this embodiment includes an RX sensor receiving chip module and a TX sensor sending chip module. The SPI device includes 12 RX sensor chips and 12 TX sensor chips. Figure 5 As shown, the FPGA device is equipped with 12 SPI (Serial Peripheral Interface) interfaces: sensor SPI RX 1-6, sensor SPI RX7-12. Through the 12 SPI interfaces, the 12 receiving chip modules (RX sensor) can be connected and communicated with the SPI bus respectively, thereby controlling the 12 receiving chip modules to collect and transmit data, so as to write to the DDR memory later. The FPGA device is also equipped with 12 TX sensorSPI interfaces, which are connected and communicated with the 12 sending chip modules (TXsensor chips) through the SPI bus respectively through a shared SPI interface, thereby controlling the 12 sending chip modules. The MCU can read and write data in the register through the Localbus bus, such as the configuration parameters of the SPI device, thereby changing the working status of each SPI device, realizing the operation of different SPI devices, and further improving the data processing efficiency of the system. The FPGA device is also equipped with a FLASH memory for flash data. The MCU is equipped with a JTAG-Port (port) for connecting to a JTAG debugger. The MCU is equipped with a USB chip, and the MCU communicates with the USB chip through USB_ULPI (Low Pin Count Interface). The USB-Port of the USB chip is connected to other terminals (such as PCs) to display the data read by the MCU. In addition, Figure 5As shown, the data processing system in which the FPGA and MCU are interconnected in this embodiment also includes a power supply circuit for supplying power to the MCU and FPGA devices to ensure the normal operation of the system. The power supply voltage VCC (Volt Current Condenser) of the power supply circuit is 5V, and there is another power supply circuit whose power supply voltage VCC is 3.3V (i.e. 3V3).

[0075] In one embodiment, a universal USB bus (Universal Serial Bus, USB) interface is provided on the MCU, and the USB interface is used to connect to a terminal device (such as a PC) via a data cable. After the MCU reads the target data on the DDR memory through the Localbus bus, the target data can be sent to the terminal device through the USB interface so that the data can be displayed through the terminal device.

[0076] In summary, the MCU in this embodiment can quickly read data from the DDR memory connected to the FPGA device through the Localbus bus, and display the data on the DDR memory through a related terminal (such as a PC). For example, according to actual verification, the MCU can view the data on the DDR memory through the memory view function of the integrated development environment Keil IDE (Integrated Development Environment). During the test process, the test data generated by the FPGA device are all sequential data from 0 to 255. Through the Memory view function, when the MCU uses the Jlink emulator to read the data content on the DDR memory, the data actually read is also sequential data from 0 to 255, such as Figure 6 Then, the data read from the DDR memory is sent to a terminal device (such as a PC) through a USB interface, and the image effect is displayed on the terminal device, such as Fig. 9 As shown, it can be clearly seen that the data are indeed sequential data from 0 to 255. At the same time, the MCU uses the Jlinksavebin command to grab the DDR memory data through the Localbus bus and save it to the terminal device. Then, through an editor such as Ultraedit, the hexadecimal data is displayed and it is found that the data displayed is also sequential data from 0 to 255, which is consistent with the expected result. Fig.10As shown. Through testing, it can be seen that the data processing system in which the FPGA and MCU are interconnected in this embodiment uses the Localbus bus of the MCU to realize the communication between the FPGA device and the MCU. The data reading and writing are simple and convenient, with high flexibility, and are suitable for the existing system architecture where each device is independent, which can effectively improve the data processing efficiency and increase the system reliability.

[0077] in, Figure 6 Each line of string in represents the storage address of the data and the corresponding data. For example, using Keil IDE Memoryview (Memory1) to query the data with the storage address (Address) of 0x61C00000, the following content can be obtained:

[0078] 0x61C00000 (storage address of data): 00 01 02 03 04 05 06 07 08 09 0A 0B OC ODOE OF 10 11 12 13 14 15 16 17 18 191A 1B 1C 1D 1E 1F20 21 (data);

[0079] 0x61C00022: 2223 24 25 26 27 2B 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 353637 3B 39 3A 3B 3C3D 3E 3F 40 41 42 43;

[0080] 0x61C00044: 44 45 46 47 48 49 4A 4B4C 4D4E 4F 50 51 52 53 54 55 56 5758 595A 5B 5C 5D 5E 5F 60 61 62 63 64 65;

[0081] 0x61C00066: 66 67 6B 696A6B6C6D 6E 6F 80 71 72 73 74 75 76 77 78 79 7A7B 7C7D 7E 7F B0 B1 B2B38485 86 87;

[0082] 0x61C00088: 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A9B 9C9D 9E 9F AO A1A2 A3 A4 A5 A6 A7 A8 A9;

[0083] <h2 style=";text-align:left;direction:ltr">0x61C000AA:AAAB AC AD AE AF B0 B1B2 B3B4B5B6B7B8 B9 BA BB BCBDBEBFC0C1 C2C3 C4 C5C6 C7 C8 C9 CA CB;<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0084] <h2 style=";text-align:left;direction:ltr"> 0x61C000CC:CCCDCECFDO D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0E1 E2E3E4E5E6 E7 E8 E9 EA EB ECED;<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0085] <h2 style=";text-align:left;direction:ltr"> 0x61C000EE:EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FE 0001 0203 04 05 06 07 08 09 0A 0B 0C OD OE OF;<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0086] <h2 style=";text-align:left;direction:ltr"> 0x61C00110:10 11 12 13 14 15 16 17 18 19lAlB 1C 1D lE 1F 20 21 22 2324 2526 27 28 292A2B2C2D2E 2F30 31;<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0087] <h2 style=";text-align:left;direction:ltr"> 0x61C00132:32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 4445 4647 48 49 4A4B 4C4D4E 4F 50 51 52 53;<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0088] <h2 style=";text-align:left;direction:ltr"> 0x61C00154: 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 6667 6869A 6B 6C 6D 6E 6F 80 71 72 73 74 75;<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0089] <h2 style=";text-align:left;direction:ltr"> 0x61C00176: 76 77 78 79 7A 7B 7C 7D7E 7F B0 B1 B2 B3 B4 B5 B6 B7 BB B98A BB BC BD BE BF 90 91 92 93 94 95 96 97;<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0090] 0x61C00198: 98 99 9A 9B 9C 9D 9E 9F AO A1 A2 A3 A4 A5 A6 A7 A8 A9 AAAB AC AD AE AF BO B1 B2 B3 B4 B5 B6 B7 B8 B9;

[0091] 0x61C001BA: BA BB BC BDBE BFCOC1C2C3C4C5C6C7C8C9CACBCCCDCECFDOD1D2D3D4D5D6D7D8D9DADB;

[0092] 0x61C001DC: DC DD DE DF EO E1 E2 E3 E4 E5 E6 E7EBE9 AEBECEDEEE EF F0F1 F2F3 F4 F5F6F7 F8F9 FA FB FCFD;

[0093] 0x61C001FE:FE FE00 01 02 03 04 05 06 07 08 09 0A OB OC OD OE OF 10 1112 1314 15 16 17 18 19lA 1B 1C1D1ElF;

[0094] 0x61C00220: 2021 22 23 24 25 26 27 28 29 2A 2B 2C2D2E2F 30 31 32 33 3435 3637 38 39 3A 3B3C3D3E3F40 41;

[0095] 0x61C00242: 42 43 44 45 46 47 48 49 4A 4B4C 4D4E 4F 50 51 52 53 54 5556 5758 59 5A 5B 5C 5D 5E 5F 60 61 62 63;

[0096] 0x61C00264: 64 65 66 67 6B 69 6A6B6C 6D 6E 6F 80 71 72 73 74 75 76 7778 797A 7B 7C 7D7E7F B0 B1 B2 B3 B4 B5.

[0097] In this embodiment, Figure 6 The data storage address and the corresponding data in the data storage address are only exemplary. In other embodiments, the data storage address and the corresponding data may be other, which will not be repeated here.

[0098] In one embodiment, if Figure 7 As shown, a data processing method for interconnecting FPGA and MCU is provided, and the method is applied in Figure 1 The data processing system in which the FPGA and MCU are interconnected is used as an example to illustrate the following steps:

[0099] S10: MCU sends a data read signal to the FPGA device through the Localbus;

[0100] S20: After receiving the data read signal from the MCU through the Localbus bus, the FPGA device performs a data read operation on the DDR memory according to the data read address of the data read signal, and feeds back the read target data;

[0101] S30: The MCU receives the target data sent by the FPGA device via the Localbus.

[0102] In this embodiment, the communication between the FPGA device and the MCU is achieved through the Localbus bus of the MCU, and the storage address of the DDR memory is mapped to the storage address space of the MCU, so that the FPGA device can use the address mapping method of the MCU to operate the data of the DDR memory. It is simple, convenient and highly flexible. The MCU can read the data of the FPGA DDR memory on the existing system architecture, thereby improving the efficiency of data processing.

[0103] Among them, the FPGA device is connected and communicated with the DDR memory through the DDR interface, that is, the DDR memory is mounted on the FPGA device. The address space of the MCU is mapped with the data address of the DDR memory. The MCU can be connected and communicated with the FPGA device through the Localbus bus, and the FPGA device is connected and communicated with the DDR memory through the DDR interface. When the MCU needs to read the data in the DDR memory, the MCU sends a data read signal to the FPGA device through the Localbus bus. Among them, since the address space of the MCU is mapped with the data address of the DDR memory, that is, the addresses of the two have a mapping relationship, after receiving the data read signal, the FPGA device can access the DDR memory through the DDR interface, and then perform a data read operation on the DDR memory according to the data read address of the data read signal to obtain the target data; the FPGA device will feed back the target data to the MCU through the Localbus bus. The MCU performs address latching and data latching on the target data fed back by the FPGA device through the Localbus bus to obtain the target data.

[0104] In this embodiment, the steps in the data processing method of interconnecting FPGA and MCU refer to the above definition of MCU and FPGA devices in the data processing system of interconnecting FPGA and MCU, which will not be repeated here.

[0105] The English abbreviations appearing in the above embodiments of the present application have the following meanings:

[0106] MCU: Microcontroller Unit (MCU), also known as Single Chip Microcomputer or Single Chip Microcomputer

[0107] FPGA: Field Programmable Gate Array. It is a product further developed on the basis of programmable devices such as PAL (Programmable Array Logic) and GAL (General Array Logic). It appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0108] Localbus: A local bus is a data transmission channel used to connect various components inside a computer. It is a parallel data bus in address + data mode.

[0109] SPI: Abbreviation for Serial Peripheral Interface. It is a synchronous serial interface technology introduced by Motorola.

[0110] DDR: The full name is DDR SDRAM (Double Data Rate SDRAM), a storage unit that does not save memory when power is off.

[0111] USB: Universal Serial Bus is a serial bus standard and a technical specification for input and output interfaces. It is widely used in information communication products such as personal computers and mobile devices.

[0112] SRAM: Static Random-Access Memory is a type of random access memory.

[0113] RX SPI RX sensor: receiving chip module.

[0114] TX SPI TX sensor sending chip module.

[0115] AXI bus: (Advanced eXtensible Interface) is a bus protocol. This protocol is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus oriented to high performance, high bandwidth and low latency.

[0116] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0117] In one embodiment, an FPGA device is provided, which has a one-to-one correspondence with the functions of the FPGA device in the data processing system in which the FPGA and the MCU are interconnected in the above-mentioned embodiment. Figure 8 As shown, the FPGA device includes a Localbus communication module 801 and a control module 802. The functional modules are described in detail as follows:

[0118] The Localbus communication module 801 is used to: receive the data reading signal of the MCU via the Localbus;

[0119] The control module 802 is used to: after receiving a data read signal from the MCU via the Localbus bus, perform a data read operation on the DDR memory according to a data read address of the data read signal;

[0120] The Localbus communication module 801 is also used to feed back the read target data to the MCU via the Localbus.

[0121] In one embodiment, an MCU is provided, which corresponds to the function of the MCU in the data processing system in which the FPGA and the MCU are interconnected in the above-mentioned embodiment. The MCU includes a Localbus bus communication module, which is used to: send a data read signal to the FPGA device through the Localbus bus, so that the FPGA device performs a data read operation on the DDR memory according to the data read address of the data read signal, and feeds back the read target data, and receives the target data sent by the FPGA device through the Localbus bus.

[0122] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0123] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0124] An embodiment of the present application also provides an electronic device, which may be an FPGA device + MCU device, and includes: a memory and an FPGA + MCU program stored in the memory and executable on the FPGA + MCU, wherein the FPGA + MCU implements the steps in any of the above-mentioned method embodiments when executing the FPGA + MCU program, or implements the functions of each device / equipment in the above-mentioned system embodiments when the processor executes the computer program.

[0125] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through the FPGA+MCU program. The FPGA+MCU program can be stored in a readable storage medium, and the FPGA+MCU program can implement the steps of the above-mentioned various method embodiments when it is executed by the FPGA+MCU. The readable storage medium may at least include: any entity or device that can carry the FPGA+MCU program code to the camera / terminal device, a recording medium, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk, or an optical disk. In some jurisdictions, according to legislation and patent practice, the readable storage medium cannot be an electric carrier signal and a telecommunication signal.

[0126] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0127] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0128] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0129] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0130] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A data processing system in which FPGA and MCU are interconnected, characterized in that: It includes an MCU, an FPGA device and a DDR memory, wherein the address space of the MCU is mapped with the data address of the DDR memory; The MCU is connected to the FPGA device for communication via a Localbus bus, and the FPGA device is connected to the DDR memory for communication via a DDR interface; The MCU can perform data reading operations on the DDR memory through the FPGA device.

2. The data processing system according to claim 1, characterized in that The FPGA device includes an SRAM, and the SRAM is used to synchronize data in the DDR memory; After the data is written to the DDR memory, the FPGA device stores the data written in the DDR memory to the SRAM when the MCU has a read request, and keeps the data address and content of the DDR memory consistent with that of the SRAM.

3. The data processing system according to claim 1, wherein: The performing a data reading operation on the DDR memory by using the FPGA device includes: The MCU sends a data read signal to the FPGA device via the Localbus; After receiving the data read signal, the FPGA device performs a data read operation on the DDR memory according to the data read address of the data read signal, and feeds back the read target data to the MCU via the Localbus bus.

4. The data processing system according to claim 3, characterized in that The performing a data reading operation on the DDR memory according to the data reading address of the data reading signal, and feeding back the read target data to the MCU through the Localbus bus, comprises: When the data at the data read address is not stored in the SRAM of the FPGA device, the data of the DDR memory is stored in the SRAM of the FPGA device, and the data address and content of the DDR memory are kept consistent with those of the SRAM; When the data at the data read address is stored in the SRAM, the data corresponding to the data read address in the SRAM is directly read to obtain the target data, and the target data is fed back to the MCU via the Localbus bus.

5. The data processing system according to any one of claims 1 to 4, characterized in that: The FPGA device also includes a register for implementing the generation, and the address space of the MCU is mapped with a data address of the register on the FPGA device so as to perform a read and write operation on the register; The MCU accesses the register of the FPGA device through the Localbus bus to perform data operations on the register in a manner of address mapping.

6. The data processing system according to any one of claims 1 to 4, characterized in that: The data processing system also includes at least one peripheral device, the FPGA device is connected and communicated with the peripheral device through a bus, and the MCU controls the operation of the peripheral device on the FPGA device through registers on the FPGA device; the FPGA device writes the data generated by the peripheral device into the DDR memory, so that the MCU performs data reading operations on the DDR memory through the FPGA device.

7. The data processing system according to claim 6, characterized in that The peripheral device is a SPI device.

8. The data processing system according to claim 5, characterized in that The register stores configuration parameters of the peripheral device; The MCU performs data operations on the configuration parameters of the peripheral devices in the registers of the FPGA device through the Localbus bus, so as to control the multiple peripheral devices generated by the FPGA.

9. A data processing method for interconnecting FPGA and MCU, characterized in that: An FPGA device used in a data processing system in which an FPGA and an MCU are interconnected, wherein the data processing system in which the FPGA and the MCU are interconnected further comprises an MCU and a DDR memory, wherein the address space of the MCU is mapped with a data address of the DDR memory, the MCU is connected and communicated with the FPGA device via a Localbus bus, and the FPGA device is connected and communicated with the DDR memory via a DDR interface; the method comprises: After receiving the data read signal from the MCU via the Localbus bus, a data read operation is performed on the DDR memory according to the data read address of the data read signal, and the read target data is fed back to the MCU via the Localbus bus.

10. A data processing method for interconnecting FPGA and MCU, characterized in that: The MCU is applied to a data processing system in which an FPGA and an MCU are interconnected. The data processing system in which the FPGA and the MCU are interconnected further comprises an FPGA device and a DDR memory. The address space of the MCU is mapped with a data address of the DDR memory. The MCU is connected and communicated with the FPGA device via a Localbus bus. The FPGA device is connected and communicated with the DDR memory via a DDR interface. The method comprises: Sending a data read signal to the FPGA device through the Localbus bus, so that the FPGA device performs a data read operation on the DDR memory according to a data read address of the data read signal, and feeds back the read target data; Receive the target data sent by the FPGA device through the Localbus bus.

Images