Interface circuit

Abstract

The invention relates to the technical field of PCIE (Peripheral Component Interface Express) equipment, and discloses an interface circuit, an anti-creeping circuit detects whether second power supply voltage leaks electricity to first power supply voltage or not, and when electricity leaks, the anti-creeping circuit thoroughly cuts off a first power supply and forms a discharge loop of the second power supply voltage so as to avoid secondary faults caused by electricity leakage of the power supply; the anti-pull-up resistor repetition circuit detects whether the resistance value of the pull-up resistor of the mainboard and the pull-up resistor of the daughter card after being connected in parallel is smaller than a preset resistance value or not, and when the resistance value is smaller than the preset resistance value, the anti-pull-up resistor repetition circuit cuts off the connection between the pull-up resistor of the mainboard and the I2C bus, so that the influence of repeated pull-up resistors on the quality of the I2C bus is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of PCIE equipment, and in particular to an interface circuit. Background Art

[0002] PCI-Express (peripheral component interconnect express, referred to as PCIE) is a high-speed serial computer expansion bus standard. The PCIE interface is mainly used to connect the CPU to high-performance peripheral devices, such as GPU, network card, array card, sound card, etc. In the PCIE interface standard, there are several types, including X1, X4, X8, and X16, depending on the number of channels, corresponding to different slot lengths. In addition to high-speed channels, the PCIE interface specification also defines signal pins such as voltage source, two-wire serial communication bus (Inter-Integrated Circuit, referred to as I2C), joint test working group interface (Joint Test Action Group, referred to as JTAG), WAKE, RESET, etc.

[0003] In the relevant PCIE design, the motherboard provides multiple power supply voltages to the PCIE device through the interface, such as P3V3_STBY, P12V, and P3V3 power supply. Among them, P3V3_STBY always provides 3.3V power supply, P12V and P3V3 have no output when turned off, and only provide 12V and 3.3V power supply when turned on. However, on the motherboard side and the PCIE device side, there are many chips and peripheral circuits that use P3V3_STBY and P3V3 at the same time. Due to defects in the chip itself or defects in the peripheral circuit design, some PCIE devices will leak from P3V3_STBY to P3V3 when they are turned off, causing the voltage of P3V3 to be not 0 when it is turned off, affecting chip initialization.

[0004] In the relevant PCIE design, for the I2C bus design, a pull-up resistor will be added on the motherboard side, and a pull-up resistor will also be reserved on the PCIE device side. Different types of PCIE devices will have different pull-up resistance values, which will lead to repeated pull-up parallel resistance values, resulting in an equivalent pull-up resistance value that is too small, resulting in increased signal noise on the I2C bus or increased interference, thereby causing communication errors or data loss. Summary of the invention

[0005] In view of this, the present invention provides an interface circuit to solve the problems of power supply voltage leakage and pull-up resistor duplication in PCIE design.

[0006] The present invention provides an interface circuit. The mainboard interface circuit is used to connect the mainboard with a daughter card. The mainboard interface circuit includes: an anti-leakage circuit and an anti-pull-up resistor repetition circuit, wherein a first end of the mainboard anti-leakage circuit inputs a first power supply voltage output by the mainboard, a second end of the anti-leakage circuit inputs a second power supply voltage output by the mainboard, and a third end of the anti-leakage circuit is grounded; when the mainboard stops outputting the first power supply voltage and the mainboard still outputs the second power supply voltage, the anti-leakage circuit detects whether the second power supply voltage leaks to the first power supply voltage. When leakage occurs, the anti-leakage circuit outputs a shutdown signal to the first power supply of the mainboard, and the anti-leakage circuit constitutes a discharge circuit for the second power supply voltage. The shutdown signal is used to shut down the first power supply voltage. The first power supply is used to output a first power supply voltage; the first end of the pull-up resistor duplication circuit is connected to the first end of the pull-up resistor of the mainboard, the second end of the pull-up resistor duplication circuit is connected to the I2C bus, and the third end of the pull-up resistor duplication circuit is grounded; the second end of the pull-up resistor of the mainboard inputs the second power supply voltage; when the daughter card is inserted, the first end of the pull-up resistor of the daughter card inputs the second power supply voltage, the second end of the pull-up resistor of the daughter card is connected to the I2C bus, and the pull-up resistor duplication circuit detects whether the resistance value of the pull-up resistor of the mainboard and the pull-up resistor of the daughter card in parallel is less than a preset resistance value. When it is less than the preset resistance value, the pull-up resistor duplication circuit cuts off the connection between the pull-up resistor of the mainboard and the I2C bus.

[0007] In the present invention, the leakage prevention circuit detects whether the second power supply voltage leaks to the first power supply voltage. When leakage occurs, the leakage prevention circuit completely cuts off the first power supply and forms a discharge circuit for the second power supply voltage to avoid secondary faults caused by power supply leakage; the pull-up resistor duplication prevention circuit detects whether the resistance value of the pull-up resistor of the mainboard and the pull-up resistor of the daughter card in parallel is less than a preset resistance value. When it is less than the preset resistance value, the pull-up resistor duplication prevention circuit cuts off the connection between the pull-up resistor of the mainboard and the I2C bus, thereby avoiding the influence of the repeated pull-up resistor on the quality of the I2C bus.

[0008] In an optional embodiment, the first power supply includes: a voltage conversion circuit and a voltage stabilizing circuit connected in series, and the leakage prevention circuit includes: a first switch circuit, a first comparison circuit, and a first enabling circuit, wherein the first end of the first switch circuit inputs the first supply voltage, the second end of the first switch circuit inputs the first enabling signal of the voltage conversion circuit, and the second end of the first switch circuit is also connected to the control end of the voltage conversion circuit; the first end of the first comparison circuit is connected to the third end of the first switch circuit, and the second end of the first comparison circuit inputs the second supply voltage; the first end of the first enabling circuit is connected to the third end of the first comparison circuit, the second end of the first enabling circuit inputs the second enabling signal, and the third end of the first enabling circuit is connected to the voltage stabilizing circuit. The control end of the circuit is connected; when the mainboard is turned off, the first enable signal turns off the voltage conversion circuit, and the first enable signal turns on the first switch circuit, and the first comparison circuit compares the third terminal voltage of the first switch circuit with the divided voltage of the second power supply voltage; when the third terminal voltage of the first switch circuit is greater than the divided voltage of the second power supply voltage, the first comparison circuit outputs the first control signal, the first enable signal outputs the first control signal to the voltage conversion circuit, and the first control signal is used to turn off the voltage stabilizing circuit; when the third terminal voltage of the first switch circuit is less than the divided voltage of the second power supply voltage, the first comparison circuit outputs the second control signal, the first enable signal outputs the first enable signal to the voltage conversion circuit, and the first enable signal is used to turn off or start the voltage stabilizing circuit.

[0009] In an optional embodiment, the first switching circuit includes: a first thyristor, a first resistor and a second resistor, wherein the first end of the first thyristor inputs a first power supply voltage, the second end of the first thyristor is connected to the first end of the first resistor and the first end of the first comparison circuit, the control end of the first thyristor inputs a first enable signal of the voltage conversion circuit, the control end of the first thyristor is also connected to the control end of the voltage conversion circuit, and the control end of the first thyristor is also connected to the first end of the second resistor; the second end of the first resistor and the second end of the second resistor are both grounded; when the mainboard is turned off, the first enable signal turns on the first thyristor.

[0010] In an optional implementation, the first thyristor is a PMOS switch tube.

[0011] In an optional embodiment, the first comparison circuit includes: a first comparator, a third resistor and a fourth resistor, wherein the positive input terminal of the first comparator is connected to the first end of the third resistor and the first end of the fourth resistor, the negative input terminal of the first comparator is connected to the third end of the first switching circuit, and the output terminal of the first comparator is connected to the first end of the first enabling circuit; the second end of the third resistor inputs the second supply voltage; and the second end of the fourth resistor is grounded.

[0012] In an optional embodiment, the first enabling circuit includes: an AND logic gate, wherein the first end of the AND logic gate inputs the second enabling signal, the second end of the AND logic gate is connected to the third end of the first comparison circuit, and the third end of the AND logic gate is connected to the control end of the voltage stabilizing circuit.

[0013] In an optional implementation, the pull-up resistor duplication prevention circuit includes: a second switch circuit, a second comparison circuit, and a second enabling circuit, wherein a first end of the second switch circuit is connected to a first end of a pull-up resistor of a mainboard, a second end of the second switch circuit is connected to an I2C bus, and a third end of the second switch circuit is grounded; a first end of the second comparison circuit inputs a second power supply voltage, and a second end of the second comparison circuit is connected to the I2C bus; a second enabling circuit, a first end of which inputs a second power supply voltage, a second end of which inputs a daughter card insertion signal, a third end of which is connected to a third end of the second comparison circuit, and a fourth end of which inputs a daughter card insertion signal. connected to the fourth end of the second switch circuit; when the daughter card is inserted, the daughter card insertion signal is input to the second end of the second enabling circuit, and the second comparison circuit compares the I2C bus voltage with the divided voltage of the second power supply voltage; when the I2C bus voltage is greater than the divided voltage of the second power supply voltage, the second comparison circuit outputs a third control signal, and the second enabling circuit outputs a shutdown signal, which is used to shut down the second switch circuit; when the I2C bus voltage is less than the divided voltage of the second power supply voltage, the second comparison circuit outputs a fourth control signal, and the second enabling circuit outputs a turn-on signal, which is used to turn on the second switch circuit.

[0014] In an optional embodiment, the second switching circuit includes: a second thyristor, a fifth resistor, and a sixth resistor, wherein the first end of the second thyristor inputs the second power supply voltage, the second end of the second thyristor is connected to the I2C bus and the first end of the fifth resistor, the control end of the second thyristor is connected to the fourth end of the second enabling circuit and the first end of the sixth resistor; the second end of the fifth resistor and the second end of the sixth resistor are grounded; the shutdown signal is used to shut down the second thyristor, and the turn-on signal is used to turn on the second thyristor.

[0015] In an optional implementation, the second thyristor is a PMOS switch tube.

[0016] In an optional embodiment, the second comparison circuit includes: a second comparator, a seventh resistor and an eighth resistor, wherein the positive input terminal of the second comparator is connected to the first end of the seventh resistor and the first end of the eighth resistor, the negative input terminal of the second comparator is connected to the I2C bus, and the output terminal of the second comparator is connected to the third end of the second enabling circuit; the second end of the seventh resistor inputs the second supply voltage; and the second end of the eighth resistor is grounded.

[0017] In an optional implementation, the second enabling circuit includes: a NOR gate SR latch and a ninth resistor, wherein the R end of the NOR gate SR latch is connected to the first end of the ninth resistor, the R end of the NOR gate SR latch also inputs a daughter card insertion signal, the S end of the NOR gate SR latch is connected to the third end of the second comparison circuit, the Q end of the NOR gate SR latch is connected to the third end of the second switch circuit, and the NOR gate SR latch is connected to the third end of the second comparison circuit. Hanging. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 Schematic diagram of PCIE interface in related technology;

[0020] Figure 2 The power supply design diagram of the motherboard in the related art;

[0021] Figure 3 The signal interconnection design diagram of the motherboard in the related art;

[0022] Figure 4 is a composition diagram of an interface circuit according to an embodiment of the present invention;

[0023] Figure 5 is a composition diagram of an anti-leakage circuit according to an embodiment of the present invention;

[0024] Figure 6 is a specific circuit structure diagram of the leakage protection circuit according to an embodiment of the present invention;

[0025] Figure 7 is a flow chart of a method for preventing leakage according to an embodiment of the present invention;

[0026] Figure 8 is a composition diagram of an anti-pull-up resistor duplication circuit according to an embodiment of the present invention;

[0027] Fig. 9 is a specific circuit structure diagram of an anti-pull-up resistor duplication circuit according to an embodiment of the present invention;

[0028] Fig.10 4 is a flow chart of a method for preventing pull-up resistor duplication according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0030] The power and signal names in the PCIE interface are as follows Figure 1 As shown, SDA / SCL are the signal line and clock line of the I2C bus, PRSNT_N is the in-position detection signal, and when PRSNT_N is low, it indicates that the device in the slot has been inserted.

[0031] The motherboard supplies power to the daughter card through the interface circuit. The motherboard power supply design is as follows: Figure 2 As shown, in the existing PCIE design, P3V3_STBY, P12V, and P3V3 are provided to the PCIE device through PCIE SLOT. P3V3_STBY always provides 3.3V power supply, P12V and P3V3 have no output when turned off, and only provide 12V and 3.3V power supply when turned on. There are many chips and peripheral circuits on the motherboard side and PCIE device side, which will use P3V3_STBY and P3V3 at the same time. Due to defects in the chip body or defects in the peripheral circuit design of some PCIE devices, when the power is off, power will leak from P3V3_STBY to P3V3, causing the voltage of P3V3 to be not 0 when it is off, affecting chip initialization.

[0032] The signal interconnection design of the motherboard is as follows Figure 3 As shown, for I2C bus design, pull-up resistors are added on the motherboard side (e.g. Figure 3 R01), on the PCIE device side, a pull-up resistor is also reserved (for example Figure 3 R02). Considering the I2C requirements on the PCIE device and the requirements of other I2C bus devices on the motherboard, the I2C bus on the motherboard needs to be equipped with a pull-up resistor and the resistance value needs to be adjusted to meet the requirements. The PCIE device also places a pull-up resistor on the I2C bus. Different types of PCIE devices have different pull-up resistor values, which results in the parallel resistance value of repeated pull-ups, resulting in the equivalent pull-up resistor value being too small, resulting in increased signal noise or interference on the I2C bus, which in turn leads to communication errors or data loss.

[0033] In order to solve the leakage of P3V3_STBY to P3V3 in the shutdown state and the repeated pull-up problem of the I2C bus, an interface circuit is provided in this embodiment. The interface circuit is used to connect the mainboard with the daughter card. The interface circuit includes: an anti-leakage circuit 1 and an anti-pull-up resistor repetition circuit 2.

[0034] like Figure 4 As shown, the first end of the leakage protection circuit 1 inputs the first power supply voltage U1 output by the mainboard, the second end of the leakage protection circuit 1 inputs the second power supply voltage U2 output by the mainboard, and the third end of the leakage protection circuit 1 is grounded.

[0035] When the mainboard stops outputting the first power supply voltage U1 and still outputs the second power supply voltage U2, the anti-leakage circuit 1 detects whether the second power supply voltage U2 leaks to the first power supply voltage U1. When leakage occurs, the anti-leakage circuit 1 outputs a shutdown signal to the first power supply of the mainboard, and the anti-leakage circuit constitutes a discharge circuit for the second power supply voltage. The shutdown signal is used to shut down the first power supply, and the first power supply is used to output the first supply voltage U1.

[0036] Specifically, the first power supply is composed of a voltage stabilizing circuit and a voltage conversion circuit connected in sequence. The voltage stabilizing circuit can stabilize the P12_PSU, and the voltage conversion circuit can convert the 12V voltage into the P3V3 voltage, that is, the first power supply voltage U1. When the mainboard is turned off, the mainboard stops the P3V3 power supply, but still provides P3V3_STBY, that is, stops the first power supply voltage U1, and continues the second power supply voltage U2. In order to prevent leakage from P3V3_STBY to P3V3, the anti-leakage circuit 1 detects whether there is leakage in real time. When there is leakage, the anti-leakage circuit 1 completely shuts down the voltage stabilizing circuit, so that the voltage conversion circuit is completely stopped, and forms a grounded discharge circuit for P3V3_STBY to discharge the leakage to the ground terminal.

[0037] Optionally, the anti-leakage circuit 1 internally integrates a switch circuit and a leakage detection circuit. After the leakage detection circuit detects leakage, the switch circuit forms a discharge loop.

[0038] like Figure 4 As shown, the first end of the anti-pull-up resistor duplication circuit 2 is connected to the first end of the pull-up resistor R01 of the mainboard, the second end of the anti-pull-up resistor duplication circuit 2 is connected to the I2C bus, and the third end of the anti-pull-up resistor duplication circuit 2 is grounded; the second end of the pull-up resistor R01 of the mainboard inputs the second power supply voltage U2.

[0039] When the daughter card is inserted, the first end of the pull-up resistor of the daughter card inputs the second power supply voltage U2, and the second end of the pull-up resistor R02 of the daughter card is connected to the I2C bus. The pull-up resistor duplication prevention circuit 2 detects whether the resistance value of the pull-up resistor R01 of the mainboard and the pull-up resistor R02 of the daughter card in parallel is less than the preset resistance value. When it is less than the preset resistance value, the pull-up resistor duplication prevention circuit 2 cuts off the connection between the pull-up resistor R01 of the mainboard and the I2C bus.

[0040] Specifically, in order to prevent the pull-up resistor R02 of the daughter card from being too small in parallel with the pull-up resistor R01 of the main board due to the insertion of the daughter card, the pull-up resistor duplication prevention circuit 2 detects the I2C bus voltage to determine whether the resistance is less than the I2C bus device requirement. If it is less than, the pull-up resistor duplication prevention circuit 2 cuts out the pull-up resistor R01 of the main board and only retains the pull-up resistor R02 of the daughter card.

[0041] Optionally, the anti-pull-up resistor duplication circuit 2 has a built-in switch circuit and a resistance detection circuit. The resistance detection circuit can determine whether the resistance is required by the I2C bus device. When it is less than, the switch circuit is turned off to cut out the pull-up resistor R01 of the mainboard.

[0042] Optionally, the interface circuit of this embodiment can not only be provided with an anti-leakage circuit 1 and an anti-pull-up resistor duplication circuit 2, but also be provided with an anti-reverse connection circuit to detect whether the power supply is reversely connected, or be provided with a protection circuit to cut off the connection between the mainboard and the sub-card when the output voltage of the mainboard is too large.

[0043] In some optional embodiments, the first power supply includes: a voltage conversion circuit and a voltage stabilization circuit connected in series, such as Figure 5 As shown, the leakage protection circuit 1 includes: a first switch circuit 11 , a first comparison circuit 12 , and a first enabling circuit 13 .

[0044] like Figure 5 As shown, the first end of the first switch circuit 11 inputs the first power supply voltage U1 (i.e., P3V3), the second end of the first switch circuit 11 inputs the first enable signal of the voltage conversion circuit (i.e., EN_P3V3), and the second end of the first switch circuit 11 is also connected to the control end of the voltage conversion circuit; the first end of the first comparison circuit 12 is connected to the third end of the first switch circuit 11, and the second end of the first comparison circuit 12 inputs the second power supply voltage U2 (i.e., P3V3_STBY); the first end of the first enable circuit 13 is connected to the third end of the first comparison circuit 12, the second end of the first enable circuit 13 inputs the second enable signal (i.e., EN_P12V), and the third end of the first enable circuit 13 is connected to the control end of the voltage stabilizing circuit.

[0045] Specifically, when the mainboard is turned off, the first enable signal turns off the voltage conversion circuit, and the first enable signal turns on the first switch circuit 11, and the first comparison circuit 12 compares the third terminal voltage of the first switch circuit 11 with the divided voltage of the second power supply voltage U2; the comparison result involves the following two situations:

[0046] (1) When the voltage at the third terminal of the first switch circuit 11 is greater than the divided voltage of the second power supply voltage U2, the first comparison circuit 12 outputs a first control signal, and the first enable signal outputs the first control signal to the voltage conversion circuit, and the first control signal is used to turn off the voltage stabilizing circuit. That is, when leakage occurs, the shutdown of the voltage stabilizing circuit is controlled by the first control signal.

[0047] (2) When the voltage at the third terminal of the first switch circuit 11 is less than the divided voltage of the second power supply voltage U2, the first comparison circuit 12 outputs the second control signal, and the first enable signal outputs the first enable signal to the voltage conversion circuit, and the first enable signal is used to turn off or turn on the voltage stabilizing circuit. That is, when no leakage occurs, the turning on and off of the voltage stabilizing circuit is controlled by the second enable signal.

[0048] In some optional embodiments, such as Figure 6 As shown, the first switch circuit 11 includes: a first thyristor Q1, a first resistor R1 and a second resistor R2.

[0049] like Figure 6 As shown, the first end of the first thyristor Q1 inputs the first power supply voltage U1, the second end of the first thyristor Q1 is connected to the first end of the first resistor R1 and the first end of the first comparison circuit 12 (i.e., the first comparator U1), the control end of the first thyristor Q1 inputs the first enable signal of the voltage conversion circuit, the control end of the first thyristor Q1 is also connected to the control end of the voltage conversion circuit, and the control end of the first thyristor Q1 is also connected to the first end of the second resistor R2; the second end of the first resistor R1 and the second end of the second resistor R2 are both grounded. When the mainboard is turned off, the first enable signal turns on the first thyristor Q1, and the first enable signal turns off the voltage conversion circuit.

[0050] Optionally, the first thyristor Q1 is a PMOS switch tube, but this is only an example and is not intended to be limiting.

[0051] Alternatively, if Figure 6 As shown, the first comparison circuit 12 includes: a first comparator U1, a third resistor R3 and a fourth resistor R4. The positive input terminal of the first comparator U1 is connected to the first terminal of the third resistor R3 and the first terminal of the fourth resistor R4, the negative input terminal of the first comparator U1 is connected to the third terminal of the first switch circuit 11, and the output terminal of the first comparator U1 is connected to the first terminal of the first enabling circuit 13 (that is, to the logic gate U2); the second terminal of the third resistor R3 inputs the second power supply voltage U2; the second terminal of the fourth resistor R4 is grounded.

[0052] Alternatively, if Figure 6As shown, the first enabling circuit 13 includes: an AND logic gate U2, wherein the first end of the AND logic gate U2 inputs the second enabling signal, the second end of the AND logic gate U2 is connected to the third end of the first comparison circuit 12 (i.e., the first comparator U1), and the third end of the AND logic gate U2 is connected to the control end of the voltage stabilizing circuit.

[0053] Specifically, Figure 6 When the motherboard is shut down,<EN_P3V3> The level is low, the voltage conversion circuit of P3V3 is always closed, and the voltage value of P3V3 Net is expected to be 0. At this time, Q1 is turned on, and regardless of whether there is leakage, P3V3Net will be connected to GND, so that the voltage value of P3V3 Net is close to 0V. The first comparator U1 is an inverting comparator. When the negative input terminal of the first comparator U1 is smaller than the positive input terminal, the first comparator U1 outputs a high level; when the negative input terminal of the first comparator U1 is larger than the positive input terminal, the first comparator U1 outputs a low level.

[0054] Figure 6 In the example, the voltage at point A is the divided voltage of the second power supply voltage U2, that is, VA = 3.3*R4 / (R3+R4). Then, for leakage, if Figure 7 As shown, there are two situations:

[0055] (1) If there is no leakage, or the leakage current I is very small, then the voltage value VB at point B = I*R1 is very small, and the circuit is risk-free. VA is greater than VB, and the output value of U1 is high. Then the output value state of U2 is the same as<EN_P12V> Same, you can boot normally.

[0056] (2) If the leakage current is large, the voltage value VB at point B = I*R1 is too large, and the circuit is at risk. VB is greater than VA, and the output value of U1 is low. U2 always outputs a low level.<EN_P12V> Unable to control EFUSE of P12V to open and unable to boot.

[0057] In some optional embodiments, such as Figure 8 As shown, the pull-up resistor duplication prevention circuit 2 includes: a second switch circuit 21 , a second comparison circuit 22 , and a second enabling circuit 23 .

[0058] like Figure 8As shown, the first end of the second switch circuit 21 is connected to the first end of the pull-up resistor R01 of the mainboard, the second end of the second switch circuit 21 is connected to the I2C bus, and the third end of the second switch circuit 21 is grounded; the first end of the second comparison circuit 22 inputs the second power supply voltage U2, and the second end of the second comparison circuit 22 is connected to the I2C bus; the second enabling circuit 23, whose first end inputs the second power supply voltage U2, whose second end inputs the daughter card insertion signal, whose third end is connected to the third end of the second comparison circuit 22, and whose fourth end is connected to the fourth end of the second switch circuit 21.

[0059] When the daughter card is inserted, the daughter card insertion signal is input to the second end of the second enabling circuit 23, and the second comparison circuit 22 compares the I2C bus voltage with the divided voltage of the second power supply voltage U2; based on different comparison results, the second enabling circuit 23 outputs different signals to the second switch circuit 21, as follows:

[0060] (1) When the I2C bus voltage is greater than the divided voltage of the second power supply voltage U2, the second comparison circuit 22 outputs a third control signal, and the second enabling circuit 23 outputs a shutdown signal, which is used to shut down the second switch circuit 21; that is, when the pull-up resistor R02 of the daughter card is connected in parallel with the pull-up resistor R01 of the mainboard, resulting in a resistance less than the resistance required by the I2C bus, the second switch circuit 21 is shut down, so that only the pull-up resistor R02 of the daughter card is retained.

[0061] (2) When the I2C bus voltage is less than the divided voltage of the second power supply voltage U2, the second comparison circuit 22 outputs a fourth control signal, and the second enabling circuit 23 outputs a conduction signal, which is used to turn on the second switch circuit 21; that is, when the pull-up resistor R02 of the daughter card is connected in parallel with the pull-up resistor R01 of the main board, resulting in a resistance greater than the resistance required by the I2C bus, the second switch circuit 21 is turned on, so that the pull-up resistor R02 of the daughter card and the pull-up resistor of the host are both retained.

[0062] In some optional embodiments, such as Fig. 9 As shown, the second switch circuit 21 includes: a second thyristor Q2, a fifth resistor R5, and a sixth resistor R6. The first end of the second thyristor Q2 is input with the second power supply voltage U2, the second end of the second thyristor Q2 is connected to the I2C bus and the first end of the fifth resistor R5, the control end of the second thyristor Q2 is connected to the fourth end of the second enabling circuit 23 (i.e., the NOR gate SR latch U4) and the first end of the sixth resistor R6; the second end of the fifth resistor R5 and the second end of the sixth resistor R6 are grounded; the turn-off signal is used to turn off the second thyristor Q2, and the turn-on signal is used to turn on the second thyristor Q2.

[0063] Optionally, the second thyristor Q2 is a PMOS switch tube.

[0064] Alternatively, if Fig. 9 As shown, the second comparison circuit 22 includes: a second comparator U3, a seventh resistor R7 and an eighth resistor R8, wherein the positive input terminal of the second comparator U3 is connected to the first end of the seventh resistor R7 and the first end of the eighth resistor R8, the negative input terminal of the second comparator U3 is connected to the I2C bus, and the output terminal of the second comparator U3 is connected to the third end of the second enabling circuit 23 (i.e., the NOR gate SR latch U4); the second end of the seventh resistor R7 inputs the second power supply voltage U2; and the second end of the eighth resistor R8 is grounded.

[0065] Alternatively, if Fig. 9 As shown, the second enabling circuit 23 includes: a NOR gate SR latch U4 and a ninth resistor R9, wherein the R end of the NOR gate SR latch U4 is connected to the first end of the ninth resistor R9, the R end of the NOR gate SR latch U4 also inputs a sub-card insertion signal (i.e., PRSNT_N), the S end of the NOR gate SR latch U4 is connected to the third end of the second comparison circuit 22 (i.e., the second comparator U3), the Q end of the NOR gate SR latch U4 is connected to the third end of the second switch circuit 21 (i.e., the second thyristor Q2), and the NOR gate SR latch U4 is connected to the third end of the second switch circuit 21 (i.e., the second thyristor Q2). Hanging.

[0066] Specifically, refer to Fig. 9 The pull-up resistor value range of the I2C bus has a clear calculation formula R = (V DD -V OL ) / I OL , where V DD is the supply voltage, V OL is the output low voltage, I OL It outputs low current. In the server design circuit, the pull-up resistor is usually selected in the range of 1k~10k. The pull-up resistor value on the mainboard side meets the needs of the mainboard side, and the pull-up resistor value on the daughter card side needs to meet the needs of the daughter card. When repeated pull-ups cause the pull-up resistor value to be too small, the pull-up resistor value on the mainboard side is disconnected from the I2C bus by controlling the second switch circuit 21 to turn off, leaving only the pull-up resistor on the daughter card side. The specific process is as follows Fig.10 shown.

[0067] Specifically, refer to Fig. 9 The second comparison circuit 22 is used to detect whether the pull-up resistance value is too small. When the resistance value of R01 and R02 is small after being connected in parallel, the voltage value of the voltage divided by R01 / / R02 and R5 at point D will be greater than the voltage value at point C, and U3 outputs a high level; when the voltage value of the voltage divided by R01 / / R02 and R5 at point D is less than the voltage value at point C, U3 outputs a low level.

[0068] Specifically, the truth table of the NOR gate SR latch U4 is shown in Table 1. When the daughter card is inserted, PRSNT_N is low, then the R-end input of U4 is 0; when the S-end input of U4 is low, the Q-end output of U4 maintains the previous state; when the S-end of U4 is high, the Q-end output of U4 is 1.

[0069] Table 1

[0070] S R Q Q Function 0 0 constant constant Keep 0 1 0 1 Set to 0 1 0 1 0 Set to 1 1 1 0 0 Undefined state

[0071] refer to Fig. 9 As shown in Table 1, when U3 outputs a high level, U4 outputs a high level, and the high level controls Q2 to turn off, so that R01 is disconnected from the I2C bus; when U3 outputs a low level, U4 output maintains the previous state.

[0072] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An interface circuit, characterized in that: The interface circuit is used to connect the mainboard with the daughter card, and the interface circuit includes: an anti-leakage circuit and an anti-pull-up resistor duplication circuit, wherein: The first end of the anti-leakage circuit inputs the first power supply voltage output by the mainboard, the second end of the anti-leakage circuit inputs the second power supply voltage output by the mainboard, and the third end of the anti-leakage circuit is grounded; When the mainboard stops outputting the first power supply voltage and the mainboard still outputs the second power supply voltage, the anti-leakage circuit detects whether the second power supply voltage leaks to the first power supply voltage. When leakage occurs, the anti-leakage circuit outputs a shutdown signal to the first power supply of the mainboard, and the anti-leakage circuit constitutes a discharge circuit of the second power supply voltage. The shutdown signal is used to shut down the first power supply, and the first power supply is used to output the first power supply voltage; The first end of the pull-up resistor duplication circuit is connected to the first end of the pull-up resistor of the mainboard, the second end of the pull-up resistor duplication circuit is connected to the I2C bus, and the third end of the pull-up resistor duplication circuit is grounded; the second end of the pull-up resistor of the mainboard is input with the second supply voltage; When the daughter card is inserted, the first end of the pull-up resistor of the daughter card inputs the second power supply voltage, and the second end of the pull-up resistor of the daughter card is connected to the I2C bus. The anti-pull-up resistor duplication circuit detects whether the resistance value of the pull-up resistor of the mainboard and the pull-up resistor of the daughter card in parallel is less than a preset resistance value. When it is less than the preset resistance value, the anti-pull-up resistor duplication circuit cuts off the connection between the pull-up resistor of the mainboard and the I2C bus.

2. The interface circuit according to claim 1, characterized in that: The first power supply includes: a voltage conversion circuit and a voltage stabilizing circuit connected in series, and the leakage prevention circuit includes: a first switch circuit, a first comparison circuit, and a first enabling circuit, wherein: The first supply voltage is input to a first terminal of the first switch circuit, the first enable signal of the voltage conversion circuit is input to a second terminal of the first switch circuit, and the second terminal of the first switch circuit is also connected to a control terminal of the voltage conversion circuit; The first end of the first comparison circuit is connected to the third end of the first switch circuit, and the second end of the first comparison circuit is input with the second supply voltage; The first terminal of the first enabling circuit is connected to the third terminal of the first comparison circuit, the second terminal of the first enabling circuit inputs the second enabling signal, and the third terminal of the first enabling circuit is connected to the control terminal of the voltage stabilizing circuit; When the mainboard is turned off, the first enable signal turns off the voltage conversion circuit, and the first enable signal turns on the first switch circuit, and the first comparison circuit compares the third terminal voltage of the first switch circuit with the divided voltage of the second power supply voltage; When the voltage at the third terminal of the first switch circuit is greater than the divided voltage of the second power supply voltage, the first comparison circuit outputs a first control signal, and the first enable signal outputs the first control signal to the voltage conversion circuit, and the first control signal is used to turn off the voltage stabilization circuit; When the third terminal voltage of the first switching circuit is less than the divided voltage of the second supply voltage, the first comparison circuit outputs a second control signal, and the first enable signal outputs the first enable signal to the voltage conversion circuit, and the first enable signal is used to turn off or turn on the voltage stabilizing circuit.

3. The interface circuit according to claim 2, characterized in that: The first switch circuit includes: a first thyristor, a first resistor and a second resistor, wherein: The first end of the first thyristor inputs the first power supply voltage, the second end of the first thyristor is connected to the first end of the first resistor and the first end of the first comparison circuit, the control end of the first thyristor inputs the first enable signal of the voltage conversion circuit, the control end of the first thyristor is also connected to the control end of the voltage conversion circuit, and the control end of the first thyristor is also connected to the first end of the second resistor; The second end of the first resistor and the second end of the second resistor are both grounded; When the mainboard is powered off, the first enable signal turns on the first thyristor.

4. The interface circuit according to claim 3, characterized in that: The first thyristor is a PMOS switch tube.

5. The interface circuit according to claim 2, characterized in that: The first comparison circuit includes: a first comparator, a third resistor and a fourth resistor, wherein: The positive input terminal of the first comparator is connected to the first terminal of the third resistor and the first terminal of the fourth resistor, the negative input terminal of the first comparator is connected to the third terminal of the first switch circuit, and the output terminal of the first comparator is connected to the first terminal of the first enabling circuit; The second end of the third resistor inputs the second supply voltage; A second end of the fourth resistor is grounded.

6. The interface circuit according to claim 2, characterized in that: The first enabling circuit comprises: an AND logic gate, wherein: The first end of the AND logic gate inputs the second enable signal, the second end of the AND logic gate is connected to the third end of the first comparison circuit, and the third end of the AND logic gate is connected to the control end of the voltage stabilizing circuit.

7. The interface circuit according to claim 1, characterized in that: The pull-up resistor duplication prevention circuit comprises: a second switch circuit, a second comparison circuit, and a second enabling circuit, wherein: A first end of the second switch circuit is connected to a first end of a pull-up resistor of the mainboard, a second end of the second switch circuit is connected to the I2C bus, and a third end of the second switch circuit is grounded; The second supply voltage is input to a first terminal of the second comparison circuit, and a second terminal of the second comparison circuit is connected to the I2C bus; a second enabling circuit, a first end of which is input with the second power supply voltage, a second end of which is input with the daughter card insertion signal, a third end of which is connected with the third end of the second comparison circuit, and a fourth end of which is connected with the fourth end of the second switch circuit; When a daughter card is inserted, the daughter card insertion signal is input to the second end of the second enabling circuit, and the second comparison circuit compares the I2C bus voltage with the divided voltage of the second power supply voltage; When the I2C bus voltage is greater than the divided voltage of the second power supply voltage, the second comparison circuit outputs a third control signal, and the second enabling circuit outputs a shutdown signal, wherein the shutdown signal is used to shut down the second switch circuit; When the I2C bus voltage is less than the divided voltage of the second power supply voltage, the second comparison circuit outputs a fourth control signal, and the second enabling circuit outputs a turn-on signal, where the turn-on signal is used to turn on the second switch circuit.

8. The interface circuit according to claim 7, characterized in that: The second switch circuit includes: a second thyristor, a fifth resistor, and a sixth resistor, wherein: The first end of the second thyristor inputs the second power supply voltage, the second end of the second thyristor is connected to the I2C bus and the first end of the fifth resistor, and the control end of the second thyristor is connected to the fourth end of the second enabling circuit and the first end of the sixth resistor; The second end of the fifth resistor and the second end of the sixth resistor are grounded; The turn-off signal is used to turn off the second thyristor, and the turn-on signal is used to turn on the second thyristor.

9. The interface circuit according to claim 8, characterized in that: The second thyristor is a PMOS switch tube.

10. The interface circuit according to claim 7, characterized in that: The second comparison circuit includes: a second comparator, a seventh resistor and an eighth resistor, wherein: The positive input terminal of the second comparator is connected to the first terminal of the seventh resistor and the first terminal of the eighth resistor, the negative input terminal of the second comparator is connected to the I2C bus, and the output terminal of the second comparator is connected to the third terminal of the second enabling circuit; The second supply voltage is input to the second end of the seventh resistor; A second end of the eighth resistor is grounded.

11. The interface circuit according to claim 7, characterized in that: The second enabling circuit includes: a NOR gate SR latch and a ninth resistor, wherein: The R end of the NOR gate SR latch is connected to the first end of the ninth resistor, the R end of the NOR gate SR latch also inputs the sub-card insertion signal, the S end of the NOR gate SR latch is connected to the third end of the second comparison circuit, the Q end of the NOR gate SR latch is connected to the third end of the second switch circuit, and the Q end of the NOR gate SR latch is suspended.

Images