Method for establishing low-temperature CMOS intensive model

Abstract

The invention discloses a method for establishing a low-temperature CMOS intensive model, and the method comprises the steps: designing a plurality of low-temperature test samples, and enabling the sizes of the low-temperature test samples to cover the sizes of a process boundary; sequentially selecting a plurality of test samples with the same size for variable temperature test, and determining a standard test core particle, a global mismatched core particle and a low-temperature local mismatched core particle; performing batch testing on the standard test core particles, the global mismatch core particles and the low-temperature local mismatch core particles to obtain parameters of the device at different temperatures; fitting is carried out according to the parameters, a low-temperature intrinsic model, a low-temperature radio frequency model and a low-temperature back-end model are established, and a low-temperature CMOS intensive model is established by combining the low-temperature intrinsic model, the low-temperature radio frequency model and the low-temperature back-end model. According to the method for establishing the low-temperature CMOS intensive model, provided by the invention, the capabilities of design, preparation and quantitative analysis of a low-temperature application-specific integrated circuit chip system of a designer can be improved, and the design and quantitative analysis of the low-temperature application-specific integrated circuit chip system can be met.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a method for establishing a low-temperature CMOS intensive model. Background Art

[0002] Against the backdrop of the slowdown in the development of Moore's Law, quantum computing, as a feasible path to break through the bottleneck of traditional computing energy efficiency, has attracted much attention in recent years. In emerging fields represented by quantum computing, low-temperature complementary metal-oxide-semiconductor (CMOS) technology plays a key role. The core of a quantum computer is a qubit array composed of quantum bits. These quantum bits are very unstable and need to work in an ultra-low temperature environment to extend the life of their quantum states. Low-temperature CMOS technology is used to control and read out the physical signals of these quantum bits to ensure their stability and operability in quantum computing.

[0003] Compared to room temperature, metal oxide semiconductor field effect transistors (MOSFETs) will exhibit a large number of temperature-dependent physical effects in low temperature environments, such as various scattering mechanisms, thermal voltage and Fermi level shifts, which cause the device to exhibit greater mobility, steeper subthreshold swings, lower leakage currents and greater threshold voltages, which in turn affect the performance changes of low-temperature CMOS circuits. However, current CMOS wafer manufacturers can only provide intensive device models in the range of -40℃-125℃, which cannot accurately describe device behavior at low temperatures. Circuit designers can usually only use the structure of normal temperature circuits and reserve a large amount of design margin to cope with the uncertainty of device parameters at low temperatures. This poses a great challenge to the design of control and readout in quantum computing, and restricts the design and manufacture of large-scale low-temperature integrated circuits. Summary of the invention

[0004] The purpose of the present invention is to provide a method for establishing a low-temperature CMOS intensive model. Through the method for establishing a low-temperature CMOS intensive model provided by the present invention, a low-temperature CMOS intensive model design scheme that can cover the entire temperature range and full size is established, so that designers can effectively measure performance indicators when designing low-temperature circuits, which helps to improve the designer's ability to design, prepare and quantitatively analyze low-temperature dedicated integrated circuit chip systems, and meet the design and quantitative analysis of low-temperature integrated circuit chip systems.

[0005] In order to solve the above technical problems, the present invention provides a method for establishing a low-temperature CMOS intensive model, which at least comprises the following steps:

[0006] Designing a plurality of low-temperature test samples, wherein the sizes of the low-temperature test samples cover various sizes of the process boundary;

[0007] Selecting a plurality of the test samples of the same size in turn to perform variable temperature testing to determine a standard test core particle, a global mismatch core particle, and a low-temperature local mismatch core particle;

[0008] Performing batch tests on the standard test core particles, the global mismatch core particles and the low-temperature local mismatch core particles to obtain parameters of the device at different temperatures;

[0009] Fitting is performed according to the parameters to establish a low-temperature intrinsic model, a low-temperature radio frequency model and a low-temperature back-end model, and a low-temperature CMOS intensive model is established by combining the low-temperature intrinsic model, the low-temperature radio frequency model and the low-temperature back-end model.

[0010] In one embodiment of the present invention, the standard test core particles are core particles that reflect the overall average level of the process on the entire wafer, the global mismatch core particles are core particles that reflect the process deviation level, and the low-temperature local mismatch core particles are devices whose test results are distributed on both sides of the statistical results after the standard test core particles are subjected to variable temperature testing in a low-temperature environment.

[0011] In one embodiment of the present invention, the test includes a low-temperature direct current test, a low-temperature radio frequency test, and a low-temperature back-end device test.

[0012] In one embodiment of the present invention, after obtaining the low-temperature DC test data, the mobility, subthreshold swing and threshold voltage intrinsic parameters of the test sample are extracted, and based on the intrinsic parameter values ​​in the BSIM4 typical model, low-temperature fitting is performed through the following formula to obtain a low-temperature typical model:

[0013]

[0014] Among them, Cryo_A_Typical is the value of parameter A under the low temperature typical model, A is the mobility, subthreshold swing or threshold voltage, a0, a L 、a W 、a P is the fitting coefficient, L is the channel length of the test sample, W is the gate width of the test sample, f(T) is the calculation formula of the corresponding mobility, subthreshold swing or threshold voltage in the BSIM4 typical model, and T is the temperature.

[0015] In one embodiment of the present invention, the method further comprises: performing batch testing on the standard test core particles and the global mismatch core particles, and extracting the variance σ of the global mismatch core particle parameters at different temperatures. mis (T), perform low temperature tests on the local mismatch core particles and extract the variance σ of the local mismatch core particle parameters at different temperatures var (T).

[0016] In one embodiment of the present invention, based on the variance σ of the global mismatch core particle parameter mis (T), and obtain the mismatch parameter sigma(T) of the global process floating random variable: Based on the variance σ of the mismatched core particle parameters var (T), and obtain the local process mismatch random variable mismatch parameter beta(T): Among them, σ mis (298K) is the variance of the global mismatch core parameter at 298K, σ var (298K) is the variance of the local mismatch core particle parameters at 298K, and T is the temperature.

[0017] In one embodiment of the present invention, the weights of the global process floating mismatch parameter sigma(T) and the local mismatch random variable mismatch parameter beta(T) at low temperature are adjusted, and a low temperature statistical model is established through Monte Carlo simulation verification:

[0018] Cryo_A=Cryo_A_Typical+(1+sigma(T))*A mis +(1+beta(T))*A var ;

[0019] Where Cryo_A is the value of parameter A under the low temperature statistical model, A is the mobility, subthreshold swing or threshold voltage, and A mis is the global mismatch parameter of the original normal temperature model, A var is the local mismatch parameter of the original normal temperature model, and T is the temperature; a low temperature intrinsic model is established by combining the formulas in the low temperature typical model and the low temperature statistical model.

[0020] In one embodiment of the present invention, based on the device model of the low-temperature DC test, an additional sub-circuit is added to the periphery to cover the characteristics in the high-frequency range, the temperature characteristics of the parasitic resistance and capacitance caused by the device layout are analyzed, and the temperature coefficient related to temperature in the BSIM4 typical model is corrected by using an empirical second-order polynomial. The correction formula is as follows:

[0021] T eff =A×(T-298) 2 +B×(T-298)+1;

[0022] Among them, T eff is the temperature correction correlation of the node resistance, A and B are the correction coefficients related to the semiconductor device material, and T is the temperature; the correction formula is integrated into the normal temperature RF model in the BSIM4 typical model, the parasitic capacitance and resistance equations are re-established, and the low temperature RF model is established.

[0023] In one embodiment of the present invention, the method for establishing the low-temperature back-end model includes: performing back-end interconnect line testing based on the electrical characteristics of the back-end interconnect metal layer at different temperatures, statistically analyzing the electrical characteristics of the back-end interconnect lines at different temperatures, and fitting the equation of the electrical characteristics changing with temperature through a quadratic polynomial to establish a low-temperature back-end model.

[0024] In one embodiment of the present invention, the dimensions of the low-temperature test sample cover large size, small size, wide size, long size and intermediate size, and the width of the metal connection and the number of through holes of the low-temperature test sample meet more than 1.5 times the current density requirement of the process device at room temperature.

[0025] In summary, the present invention provides a method for establishing a low-temperature CMOS intensive model, and establishes a low-temperature CMOS intensive model through low-temperature DC model fitting items, statistical model fitting items, and radio frequency model fitting items, which can cover the full temperature range and full-size low-temperature CMOS intensive model design scheme. It is possible to integrate the low-temperature models of the front-end transistors and the back-end interconnection layers, verify the working state of the relevant circuits at low temperatures, and establish a complete low-temperature CMOS intensive model. By correcting the fitting items of key electrical parameters in the device model card under low-temperature environments, designers can effectively measure performance indicators when designing low-temperature circuits, which helps to improve the designer's ability to design, prepare, and quantitatively analyze low-temperature dedicated integrated circuit chip systems, and meet the design and quantitative analysis of low-temperature integrated circuit chip systems.

[0026] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0028] Figure 1 FIG. 1 is a schematic diagram of establishing a low-temperature CMOS intensive model in one embodiment of the present invention.

[0029] Figure 2 Schematic diagram of size selection of low temperature test samples in one embodiment of the present invention.

[0030] Figure 3 Schematic diagram of selecting standard test core particles in one embodiment of the present invention.

[0031] Figure 4 It is a schematic diagram of establishing a typical low temperature model in one embodiment of the present invention.

[0032] Figure 5 It is a schematic diagram of establishing a low-temperature intrinsic model in one embodiment of the present invention.

[0033] Figure 6 Schematic diagram of an equivalent circuit of a low-temperature radio frequency device in one embodiment of the present invention.

[0034] Figure 7 Schematic diagram of establishing a low-temperature front-end model in one embodiment of the present invention.

[0035] Figure 8 FIG. 1 is a schematic diagram of establishing a low-temperature CMOS intensive model in one embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] In the description of this specification, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing this solution and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on this solution. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0039] Please refer to Figure 1. In one embodiment of the present invention, a method for establishing a low-temperature CMOS intensive model is provided, which at least includes designing multiple low-temperature test samples, and the sizes of the low-temperature test samples cover all sizes of the process boundary. Select multiple test samples of the same size in turn for variable temperature testing to determine the standard test core particles, global mismatch core particles and low-temperature local mismatch core particles. Perform batch tests on the standard test core particles, global mismatch core particles and low-temperature local mismatch core particles to obtain the parameters of the device at different temperatures. According to the parameters, corrections are made to establish a low-temperature intrinsic model, a low-temperature RF model and a low-temperature back-end model, thereby establishing a low-temperature CMOS intensive model. It can cover the entire temperature range and the full size of CMOS to meet the circuit designer's ability to effectively measure performance indicators when designing low-temperature circuits.

[0040] See 1 and Figure 2 As shown, in one embodiment of the present invention, in step S11, when designing multiple low-temperature test samples, the size of the low-temperature test samples covers all sizes of the process boundary, for example, the size of the designed low-temperature device covers large-size devices, short-channel devices, narrow-channel devices, and small-size devices. In this embodiment, considering the low-temperature long channel and narrow channel effects, large-size and narrow-size semiconductor devices are selected as test samples before modeling the semiconductor device. Considering the completeness of the model, the semiconductor device size covers large size (gate width W and channel length L are both large), small size (gate width W and channel length L are both small), wide size (gate width W is large, channel length L is from large to small), long size (channel length L is large, gate width W is from large to small), and intermediate size (partial device within the size angle) devices as test samples. That is, in this embodiment, in addition to selecting devices of the corresponding model partition boundary size to obtain sufficient data to cover all size angles of a certain process, it should also focus on selecting device sizes with longer and narrower channels. After selecting the low-temperature device size, in addition to the intrinsic devices, the process-related mismatch parameters will also increase at low temperatures. Therefore, devices with the same layout structure and the same size are designed as local mismatch core particles to simulate large-scale wafer production for low-temperature scenarios.

[0041] See 1 and Figure 2 As shown, in one embodiment of the present invention, in a low temperature environment, the parasitic parameters in the semiconductor device will change accordingly, causing the operating current of the semiconductor device to increase significantly. In order to reduce parasitic effects and ensure the stable operation of semiconductor devices, when designing the layout of the low temperature test sample, it is necessary to ensure that the width of the metal connection and the number of through holes meet more than 1.5 times the current density requirement of the process device at room temperature. After completing the design of the low temperature test sample, the low temperature test sample is manufactured. The manufacturing process and process will not be discussed in detail here, and it can be completed using any existing semiconductor manufacturing process.

[0042] See 1 and Figure 3 As shown, in one embodiment of the present invention, after obtaining the low-temperature test sample, step S12 is performed to select a low-temperature test core particle. Specifically, 4 to 5 different width and length dimensions are selected as the dimensions to be tested, and multiple test samples of the same size are selected in turn for variable temperature testing, such as statistics of key electrical parameters such as threshold voltage and turn-on current. Due to the existence of process errors, the electrical characteristics of devices of the same size on different core particles are quite different. According to the statistical results, the electrical parameters between the core particles of semiconductor devices are normally distributed based on the process average value. Therefore, the core particles that reflect the overall average level of the process are selected from the entire wafer (wafer) as standard test core particles (Golden Die), and the core particles that reflect the process deviation level are used as global mismatch core particles. Then, in a low-temperature environment, multiple standard test core particles of the same size are subjected to variable temperature tests, and the key electrical parameters are compared, and the devices distributed on both sides of the statistical results are selected as low-temperature local mismatch core particles.

[0043] Please refer to Figure 1. In one embodiment of the present invention, after selecting a low-temperature test core particle, step S13 is performed to test the low-temperature device, such as batch testing of standard test core particles of different sizes, global mismatch core particles and low-temperature local mismatch core particles, to obtain parameters of semiconductor devices of different sizes at different temperatures, and the low-temperature device test includes, for example, low-temperature DC test, low-temperature RF test and low-temperature back-end device test. In a low-temperature environment, the intrinsic parameters of semiconductor devices will change significantly. By performing a low-temperature DC test, semiconductor devices of different sizes are tested and characterized by three types of curves, namely, temperature-dependent transfer characteristic curve (IDS-VGS), output characteristic curve (IDS-VDS) and substrate current curve (Isub-VGS) under different DC biases, to obtain the electrical characteristics of the semiconductor device in the subthreshold region, linear region and saturation region at different temperatures, and to extract the curve of the change of relevant intrinsic parameters with temperature.

[0044] Please refer to Figure 1. In one embodiment of the present invention, in a low temperature environment, the process deviation of the semiconductor device will further increase. By fixing bias conditions, such as DC voltage and current, etc., the standard test core particles and the global mismatch core particles are batch tested to extract the variance σ of the global mismatch core particle parameters at different temperatures. mis (T). After completing the test of the global mismatch core particles, the local mismatch core particles are tested at low temperature to extract the variance σ of the local mismatch core particle parameters at different temperatures. var (T).

[0045] Please refer to Figure 1. In one embodiment of the present invention, in a low temperature environment, the parasitic parameters of the semiconductor device will change. When performing low temperature RF testing, at each test temperature point, the test sample is pierced with a RF GSG probe, for example. After the test is completed, the standard SOLT (Short-Open-Load-Through) calibration method is performed to remove the parasitic parameters of the instrument, cable and probe, and the RF S parameters of the MOSFET device at different temperatures are obtained. The RF S parameters are such as resistance and capacitance, and the RF S parameters remove the parasitic resistance and capacitance caused by the device layout. At the same time, in this embodiment, for example, the four-probe method is used to measure the temperature-related characteristics of various sizes of back-end components, such as resistance, capacitance and interconnect metal, to obtain low temperature back-end parameters, which is conducive to the adjustment of the model back-end parasitic parameters and the establishment of a low temperature back-end model.

[0046] Please refer to 1. Figure 4 and Figure 5 As shown, in one embodiment of the present invention, after obtaining the parameters of the semiconductor device at different temperatures, step S14 is performed to establish a low-temperature model. Specifically, according to the data in the low-temperature DC test, the intrinsic parameters such as the mobility (U0), subthreshold swing (NAFC) and threshold voltage (K1) of the semiconductor device are extracted. For the test results of the standard test core particles, under the framework of the macro model, based on the parameter values ​​of U0, NAFC, K1 and other parameters in the original BSIM4 typical model, the parameters such as U0, NAFC, K1 are fitted, and the low electric field mobility Cryo_U0, subthreshold swing factor Cryo_NFAC, threshold voltage coefficient Cryo_K1 and the like at low temperature are defined, and low-temperature fitting is performed through the following formula:

[0047]

[0048] Among them, Cryo_A_Typical is the value of parameter A under the typical low temperature model, A is the parameters such as U0, NAFC, K1, a0, a L 、a W 、a P is the fitting coefficient, L is the channel length of the semiconductor device, W is the gate width of the semiconductor device, f(T) is the calculation formula of the corresponding parameters such as U0, NAFC, K1 in the BSIM4 typical model, and T is the temperature. By fitting the intrinsic parameters at low temperature, the low temperature model is corrected, and the low temperature typical model is obtained by combining the BSIM4 typical model. By fitting the intrinsic parameters, a low temperature typical model that can cover different sizes and lower temperature ranges can be realized.

[0049] Please refer to 1. Figure 4 and Figure 5As shown, in one embodiment of the present invention, since the process fluctuation characteristics are amplified at low temperature, the intrinsic parameters of the mismatched samples are statistically analyzed to establish a low-temperature statistical model. Specifically, based on the variance σ of the global mismatched core particle parameters at different temperatures mis (T), the mismatch parameter sigma(T) of the global process floating random variable can be obtained by the following formula:

[0050]

[0051] Among them, σ mis (298K) is the variance of the global mismatch core particle parameters at 298K, and T is the temperature.

[0052] The standard test core particles were tested, and the local mismatch core particles were selected. After multiple tests, the variance σ of the local mismatch core particles at different temperatures was calculated. var (T), the local process mismatch random variable mismatch parameter beta(T) can be obtained by the following formula:

[0053]

[0054] Among them, σ var (298K) is the variance of the local mismatch core particle parameters at 298K, and T is the temperature.

[0055] After obtaining the mismatch parameter sigma(T) of the global process floating random variable and the mismatch parameter beta(T) of the local process mismatch random variable, the process floating characteristics of semiconductor device parameters (such as threshold voltage, etc.) at low temperature are integrated into the PDK library. The difference between the global process floating random variable and the local mismatch random variable in a low temperature environment is obtained, and the weights of the global process floating mismatch parameter sigma(T) and the local mismatch random variable mismatch parameter beta(T) of parameters such as threshold voltage and subthreshold swing at low temperatures are increased. The low temperature statistical model is established through Monte Carlo simulation verification. Among them, in the low temperature statistical model, the value of parameter A at low temperature is obtained by the following formula:

[0056] Cryo_A=Cryo_A_Typical+(1+sigma(T))*A mis +(1+beta(T))*A var ;

[0057] Among them, Cryo_A is the value of parameter A under the low temperature statistical model, A is the parameter of U0, NAFC, K1, etc. mis is the global mismatch parameter of the original normal temperature model, A var is the local mismatch parameter of the original normal temperature model, and T is the temperature. The formulas in the low temperature typical model and the low temperature statistical model are combined to establish the low temperature intrinsic model.

[0058] Please refer to 1. Figure 6 and Figure 7 As shown, in one embodiment of the present invention, Figure 6 The equivalent circuit of the radio frequency device used in the present invention includes an intrinsic device model and peripheral parasitic parameters. Among them, the peripheral parasitic parameters mainly include three types, one is the layout-dependent peripheral resistance, including the gate electrode resistance Rg,ext and the node resistance Rd,ext and Rs,ext, the second is the peripheral parasitic capacitance Cgs,ext, Cgd,ext and Cds,ext caused by the interconnection between the metal and the MOSFET transistor, and the third is the equivalent substrate resistance on the substrate network, including the equivalent substrate resistance Rsub, the gate-to-body capacitance Cgb and the junction capacitance Cjs and Cjd. Based on the existing low-temperature intrinsic model, an additional sub-circuit is added to the periphery of the device model for low-temperature DC testing to cover the characteristics within the high-frequency range, and the temperature characteristics of the parasitic resistance and capacitance caused by the device layout are analyzed and studied. By analyzing and studying the temperature characteristics of the parasitic resistance and capacitance caused by the device layout in the high-frequency range, an empirical second-order polynomial is used to correct the temperature coefficient related to temperature in the BSIM4 typical model, so that it can take into account the static operating point of the device in the high-frequency operating range, the radio frequency effect of the gate and substrate at low temperature, and the temperature sensitivity characteristics of other components. The correction formula is as follows:

[0059] T eff =A×(T-298) 2 +B×(T-298)+1;

[0060] Among them, T eff is the temperature correction correlation of the node resistance, A and B are the correction coefficients related to the semiconductor device material, and T is the temperature. This formula is integrated into the room temperature RF model in the BSIM4 typical model to establish a low temperature RF model. Then, the low temperature intrinsic model and the low temperature RF model are combined to establish a low temperature front-end model.

[0061] See 1 and Figure 8As shown, in one embodiment of the present invention, on the basis of obtaining the low-temperature front-end model, the back-end interconnection line test is carried out based on the electrical characteristics of the back-end interconnection metal layer at different temperatures, the electrical characteristics of the back-end interconnection line at different temperatures are statistically analyzed, and the equations of its temperature variation are fitted by quadratic polynomials to establish a low-temperature back-end model. The low-temperature front-end model and the low-temperature back-end model are integrated, that is, the low-temperature models of the front-end transistor and the back-end interconnection layer are integrated to verify the working state of the relevant circuits at low temperatures, and establish a complete low-temperature CMOS intensive model. The reliability of this intensive model is further verified by simulation tests of circuits such as ring oscillators under corresponding processes under low-temperature conditions. The method for establishing a low-temperature CMOS intensive model provided by the present invention establishes a low-temperature CMOS intensive model through low-temperature DC model fitting items, statistical model fitting items, and RF model fitting items, etc., which can cover the full temperature range and full-size low-temperature CMOS intensive model design scheme, and the fitting items of key electrical parameters in the device model card under low-temperature environment are corrected, so that the designer can effectively measure the performance indicators when designing low-temperature circuits, which helps to improve the designer's ability to design, prepare and quantitatively analyze low-temperature dedicated integrated circuit chip systems, and meet the design and quantitative analysis of low-temperature integrated circuit chip systems.

[0062] In summary, the present invention provides a method for establishing a low-temperature CMOS intensive model, and establishes a low-temperature CMOS intensive model through low-temperature DC model fitting items, statistical model fitting items, and radio frequency model fitting items, etc., which can cover the full temperature range and full-size low-temperature CMOS intensive model design scheme. It is possible to integrate the low-temperature models of the front-end transistors and the back-end interconnection layers, verify the working state of the relevant circuits at low temperatures, and establish a complete low-temperature CMOS intensive model. By correcting the fitting items of key electrical parameters in the device model card under low-temperature environments, the designer can effectively measure the performance indicators when designing low-temperature circuits, which helps to improve the designer's ability to design, prepare and quantitatively analyze low-temperature dedicated integrated circuit chip systems, and meet the design and quantitative analysis of low-temperature integrated circuit chip systems.

[0063] The above description of the illustrated embodiments of the present invention (including the contents described in the Abstract) is not intended to be an exhaustive list or to limit the present invention to the precise form disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention as will be recognized and appreciated by those skilled in the art. As noted, these modifications may be made to the present invention in accordance with the above description of the embodiments described in the present invention, and these modifications will be within the spirit and scope of the present invention.

[0064] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solution formed by replacing the above features with the technical features with similar functions disclosed in this application (but not limited to). In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be described in detail here.

Claims

1. A method for establishing a low-temperature CMOS intensive model, characterized in that: At least the following steps are included: Designing a plurality of low-temperature test samples, wherein the sizes of the low-temperature test samples cover various sizes of the process boundary; Selecting a plurality of the test samples of the same size in turn to perform variable temperature testing to determine a standard test core particle, a global mismatch core particle, and a low-temperature local mismatch core particle; Performing batch tests on the standard test core particles, the global mismatch core particles and the low-temperature local mismatch core particles to obtain parameters of the device at different temperatures; Fitting is performed according to the parameters to establish a low-temperature intrinsic model, a low-temperature radio frequency model and a low-temperature back-end model, and a low-temperature CMOS intensive model is established by combining the low-temperature intrinsic model, the low-temperature radio frequency model and the low-temperature back-end model.

2. The method for establishing a low-temperature CMOS intensive model according to claim 1, characterized in that: The standard test core particles are core particles that reflect the overall average level of the process on the entire wafer, the global mismatch core particles are core particles that reflect the process deviation level, and the low-temperature local mismatch core particles are devices whose test results are distributed on both sides of the statistical results after the standard test core particles are subjected to variable temperature testing in a low-temperature environment.

3. The method for establishing a low-temperature CMOS intensive model according to claim 1, characterized in that: The tests include low temperature DC test, low temperature RF test and low temperature back-end device test.

4. The method for establishing a low-temperature CMOS intensive model according to claim 3, characterized in that: After obtaining the low-temperature DC test data, the mobility, subthreshold swing and threshold voltage intrinsic parameters of the test sample are extracted, and based on the intrinsic parameter values ​​in the BSIM4 typical model, low-temperature fitting is performed through the following formula to obtain a low-temperature typical model: Among them, Cryo_A_Typical is the value of parameter A under the low temperature typical model, A is the mobility, subthreshold swing or threshold voltage, a0, a L 、a W 、a P is the fitting coefficient, L is the channel length of the test sample, W is the gate width of the test sample, f(T) is the calculation formula of the corresponding mobility, subthreshold swing or threshold voltage in the BSIM4 typical model, and T is the temperature.

5. The method for establishing a low-temperature CMOS intensive model according to claim 4, characterized in that: The method further comprises: performing batch testing on the standard test core particles and the global mismatch core particles, and extracting the variance σ of the global mismatch core particle parameters at different temperatures. mis (T), perform low temperature tests on the local mismatch core particles and extract the variance σ of the local mismatch core particle parameters at different temperatures var (T).

6. The method for establishing a low-temperature CMOS intensive model according to claim 5, characterized in that: Based on the variance σ of the global mismatch core particle parameters mis (T), obtain the mismatch parameter of the global process floating random variable Based on the variance σ of the mismatched core particle parameters var (T), obtain the local process mismatch random variable mismatch parameter Among them, σ mis (298K) is the variance of the global mismatch core parameter at 298K, σ var (298K) is the variance of the local mismatch core particle parameters at 298K, and T is the temperature.

7. The method for establishing a low-temperature CMOS intensive model according to claim 6, characterized in that: The weights of the global process floating mismatch parameter sigma(T) and the local mismatch random variable mismatch parameter beta(T) at low temperature are adjusted, and a low temperature statistical model is established through Monte Carlo simulation verification: Cryo_A=Cryo_A_Typical+(1+sigma(T))*A mis +(1+beta(T))*A var ; Where Cryo_A is the value of parameter A under the low temperature statistical model, A is the mobility, subthreshold swing or threshold voltage, and A mis is the global mismatch parameter of the original normal temperature model, A var is the local mismatch parameter of the original normal temperature model, and T is the temperature; a low temperature intrinsic model is established by combining the formulas in the low temperature typical model and the low temperature statistical model.

8. The method for establishing a low-temperature CMOS intensive model according to claim 3, characterized in that: Based on the device model of the low-temperature DC test, additional sub-circuits are added to the periphery to cover the characteristics in the high-frequency range, and the temperature characteristics of parasitic resistance and capacitance caused by the device layout are analyzed. The temperature coefficient related to temperature in the BSIM4 typical model is corrected using an empirical second-order polynomial. The correction formula is as follows: T eff =A×(T-298) 2 +B×(T-298)+1; Among them, T eff is the temperature correction correlation of the node resistance, A and B are the correction coefficients related to the semiconductor device material, and T is the temperature; the correction formula is integrated into the normal temperature RF model in the BSIM4 typical model, the parasitic capacitance and resistance equations are re-established, and the low temperature RF model is established.

9. The method for establishing a low-temperature CMOS intensive model according to claim 1, characterized in that: The method for establishing the low-temperature back-end model includes: performing back-end interconnect line testing based on the electrical characteristics of the back-end interconnect metal layer at different temperatures, statistically analyzing the electrical characteristics of the back-end interconnect lines at different temperatures, and fitting the equation of the electrical characteristics changing with temperature through a quadratic polynomial to establish a low-temperature back-end model.

10. The method for establishing a low-temperature CMOS intensive model according to claim 1, characterized in that: The sizes of the low-temperature test samples cover large size, small size, wide size, long size and intermediate size. The width of the metal connections and the number of through holes of the low-temperature test samples meet more than 1.5 times the current density requirements of the process device at room temperature.

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