High-performance high and low dropout linear regulator PSRR layout method

Abstract

The present invention discloses a high-performance high-low voltage difference linear regulator PSRR layout method, which belongs to the field of voltage regulator layout design optimization technology. It includes the following steps: S1, obtaining LDO layout, performing circuit analysis and layout analysis; S2, redesigning the power supply network according to the results of circuit analysis and layout analysis. The present invention uses circuit analysis and layout analysis to deeply analyze and post-analyze the existing LDO layout, and continuously optimize the layout in a loop, and finally realizes the design of high-performance high-low voltage difference linear regulator, which can effectively improve the PSRR of LDO and ensure the stability and reliability of the regulator under various working conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage regulator layout design optimization, and in particular to a high-performance high-low voltage difference linear voltage regulator PSRR layout method. Background Art

[0002] In the existing low-dropout regulator (LDO) layout design, how to solve the problem of LDO high-frequency power supply rejection (PSR) has always been a research hotspot and challenge. The basic circuit of LDO is composed of a reference circuit, an error amplifier and a power device. The reference circuit provides a reference voltage VREF. The error amplifier amplifies the small error signal between the output feedback voltage and the reference voltage, and then passes through the adjustment tube and is connected to the negative end of the op amp to form negative feedback. The purpose of keeping the output voltage unchanged when the input voltage and load current change is achieved.

[0003] Here are some existing methods for improving the PSR performance of LDOs at high frequencies:

[0004] 1. Optimize the internal layout of the LDO, reduce the loop area, and avoid long wiring. This can reduce the area and wiring between key components such as the error amplifier, power tube, and feedback network, thereby reducing the coupling and interference of LDO noise.

[0005] 2. Use enough capacitors. Use enough capacitors at the output to provide stable voltage and current and suppress noise. In the input feedback network, add feedforward capacitors to form a bypass path, enhance the ability to suppress noise, and make the power tube receiving end relatively stable.

[0006] 3. Optimize the power network design. Usually a single-point grounding strategy is used to reduce noise and interference on the power ground. At the same time, use sufficiently wide wiring to reduce parasitic resistance, thereby reducing voltage drop and improving transmission quality.

[0007] 4. Introduce noise isolation. Add a guard ring and shielding layer around the LDO to reduce the interference of external noise on the LDO.

[0008] However, with the existing technology, when the frequency is continuously increased to UGF (Unity Gain Frequency), the shunt effect of the feedback loop no longer exists, and the PSR is only determined by the RDS (Drain-Source Resistance) of the adjustment tube and the impedance voltage divider between the output and the ground that is independent of the frequency. Therefore, the parasitic coupling in the layout will cause the PSR of the LDO to deteriorate at high frequencies. In the process of PSR deterioration, in order to suppress noise with sufficient capacitance, the capacitance will continue to increase, thereby increasing the LDO loop area and increasing the routing length between key nodes. In the process of solving PSR, new problems arise, which deteriorate the PSR of the power tube. At the same time, with the smaller and smaller process technology, the restrictions of DRC (Design Rule Check) rules and the increase in metal levels, the parasitic coupling and noise brought by the multi-layer metal power network have an increasing impact on PSR.

[0009] Therefore, it is urgent to propose a high-performance high-low dropout linear regulator PSRR (Power Supply Rejection Ratio) layout method. Summary of the invention

[0010] The purpose of the present invention is to provide a high-performance high-low voltage difference linear regulator PSRR layout method, through the analysis of high and low frequency PSR status and the prior art, the entire power supply network of the LDO layout is innovatively designed to effectively solve the problem of high frequency PSR deterioration.

[0011] The purpose of the present invention is achieved by the following technical solutions:

[0012] In a first aspect, the present invention provides a high-performance high-low voltage drop linear regulator PSRR layout method, comprising the following steps:

[0013] S1. Obtain the LDO layout and perform circuit analysis and layout analysis;

[0014] S2. Redesign the power supply network based on the circuit analysis and layout analysis results;

[0015] Among them, in step S1, the LDO layout is obtained and the circuit analysis is performed, which specifically includes the following contents:

[0016] Step S101, extracting the layout power network according to the LDO layout, and analyzing the small signal difference of the high-frequency PSR circuit;

[0017] Step S102, performing circuit post-simulation and analysis according to the high-frequency PSR circuit small signal difference analysis result to obtain the circuit post-simulation analysis result;

[0018] Step S103, identifying key design parameters that affect PSRR based on the circuit post-simulation analysis results;

[0019] Step S104: Propose a layout power network optimization strategy based on key design parameters.

[0020] Preferably, in step S1, the LDO layout is obtained and the layout analysis is performed, which specifically includes the following contents:

[0021] Step S11, performing post-simulation analysis based on the LDO layout to identify shortcomings and deficiencies in the design;

[0022] Step S12, summarizing a series of processing methods for the layout according to the post-simulation analysis results of the LDO layout;

[0023] Step S13: Perform layout iterative optimization and verification according to the series processing method.

[0024] Preferably, the step S11 specifically includes the following process:

[0025] Step S111: Use post-simulation tools to simulate the LDO layout to ensure that the circuit model is consistent with the actual layout. Figure 1 parameters, connection methods and layout information.

[0026] Step S112: Perform post-simulation analysis to identify potential design defects and deficiencies in the power supply network.

[0027] Preferably, the step S112 includes:

[0028] According to the simulation results, the output voltage fluctuation, load response and frequency characteristics of LDO are analyzed;

[0029] Based on simulation results, identify design flaws in the power network, including high-impedance paths, long traces, inadequately filtered capacitors, and ground loops.

[0030] According to the simulation results, the PSR values ​​at different frequencies are obtained, and the changes of PSR at different frequencies are identified;

[0031] Based on the simulation results, identify whether there are crossings between signal lines and power lines or ground lines in the layout.

[0032] Preferably, the step S13 specifically includes:

[0033] Step S131, modifying the LDO layout according to the series processing method;

[0034] Step S132, performing post-simulation analysis on the modified LDO layout again to obtain the post-simulation analysis result;

[0035] Step S133, verifying the improvement effect of the series of processing methods according to the post-simulation analysis results;

[0036] Step S134: According to the improvement effect, the layout is iterated and post-simulation verification is performed again.

[0037] Preferably, step 101 includes the following process:

[0038] Extract the wiring structure between power supply and ground from the LDO layout to obtain the power supply network;

[0039] Establish a small signal model for the LDO circuit and extract key parameters;

[0040] Determine the frequency range of the high-frequency noise source and apply it to the input of the LDO;

[0041] Calculate the PSR and record the PSR values ​​at different frequencies.

[0042] Preferably, the step S102 specifically includes:

[0043] After the circuit design is completed, post-simulation is performed to verify the performance of the circuit under the actual layout;

[0044] Measure the change of PSR value in the post-simulation, record the PSR value at different frequencies, and obtain the circuit post-simulation analysis results.

[0045] Preferably, step S1, obtaining the LDO layout, performing circuit analysis and layout analysis, further includes: establishing a feedback mechanism to form a closed-loop feedback loop between the circuit analysis and the layout analysis. The establishment of the feedback mechanism specifically includes the following process:

[0046] Establishing mutual feedback between step S101 and step S11;

[0047] A mutual feedback between step S104 and step S12 is established.

[0048] Preferably, mutual feedback is established between step S101 and step S11, including: comparing a first PSR variation characteristic obtained from a small signal difference of a high-frequency PSR circuit with a second PSR variation characteristic obtained by post-simulation analysis based on an LDO layout; and proposing layout optimization suggestions based on the comparison results.

[0049] Preferably, establishing mutual feedback between step S104 and step S12 includes: performing iterative optimization and verification of the layout according to the layout power network optimization strategy and the series of layout processing methods; specifically including:

[0050] Step S201, comparing the layout power network optimization strategy and the series of processing methods of the layout, and extracting the comparison results with consistent strategies;

[0051] Step S202, modifying the LDO layout according to the strategy-consistent comparison results;

[0052] Step S203, performing post-simulation analysis on the modified LDO layout again to obtain the post-simulation analysis result;

[0053] Step S204, verifying the improvement effect of the comparison results with consistent strategies according to the post-simulation analysis results;

[0054] Step S205: According to the improvement effect, the layout is iterated and post-simulation verification is performed again.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] The present invention uses circuit analysis and layout analysis, in-depth analysis of the existing LDO layout, post-simulation analysis and continuous iterative optimization of the layout, and finally realizes the design of high-performance high and low voltage difference linear regulators, which can effectively improve the PSRR of the LDO and ensure the stability and reliability of the regulator under various working conditions.

[0057] The present invention establishes a feedback mechanism of circuit analysis and layout analysis to realize closed-loop feedback of LDO layout, links the various stages of circuit analysis and layout analysis, iterates and optimizes the layout design through continuous comparison and feedback, and finally realizes a high-performance high and low voltage difference linear regulator design, which can effectively improve the PSRR of the LDO and ensure the stability and reliability of the regulator under various working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0059] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0060] Figure 1 A schematic flow chart of a high-performance high-low voltage difference linear regulator PSRR layout method is provided for the present invention;

[0061] Figure 2 A schematic diagram of a flow chart of circuit analysis provided in the first embodiment;

[0062] Figure 3 A schematic diagram of the flow of layout analysis provided in the first embodiment;

[0063] Figure 4 A schematic diagram of the process of step S13 provided in the first embodiment;

[0064] Figure 5 A schematic diagram of a process for establishing a feedback mechanism provided in the second embodiment;

[0065] Figure 6 This is a schematic diagram of the structure of an electronic device provided in the third embodiment. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0068] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0069] The present invention provides a high-performance high-low voltage difference linear regulator PSRR layout method, which is mainly carried out by combining circuit analysis with layout analysis. It not only solves the layout power network redesign of high-frequency PSR, but also solves the processing of layout capacitance of high-frequency PSR.

[0070] The specific embodiments of the present invention will be described in detail below:

[0071] Embodiment 1:

[0072] like Figure 1 As shown, the present invention provides a high-performance high-low voltage difference linear regulator PSRR layout method, comprising the following steps:

[0073] S1. Obtain the LDO layout and perform circuit analysis and layout analysis. The LDO (low dropout linear regulator) layout refers to the physical layout of the LDO circuit in the integrated circuit (IC) design. It includes a two-dimensional representation of all electrical components (such as transistors, resistors, capacitors, etc.) and their connections. The design of the LDO layout directly affects its performance, power consumption, thermal management, and power integrity.

[0074] For circuit analysis: It is necessary to understand the circuit behavior under low and high frequency conditions in LDO (low dropout linear regulator) design. Specifically:

[0075] Under low-frequency conditions, the path is from VDD to output VREG, and the layout ensures sufficient EMIR capability and noise absorption capability of the filter capacitor. However, after introducing the filter capacitor into the feedback loop, it is found that the capacitor under low-frequency conditions only ensures that the noise can be effectively absorbed and continuously discharged to the ground under low-frequency equivalent DC.

[0076] However, at high frequencies, capacitors have the characteristics of AC conduction and DC resistance, and at this time, the capacitor is equivalent to a wire, and the resistance R to the ground becomes important, which affects the discharge capacity of the capacitor. If R is large, the discharge efficiency of the capacitor will decrease, resulting in the inability to effectively absorb high-frequency noise, affecting the stability and performance of the circuit.

[0077] For layout analysis: It is necessary to understand how the layout and planning of the layout affect the stability and reliability of the LDO power network design in the LDO (low dropout linear regulator) design. Specifically:

[0078] In the design of the power network of the prior art, the power device is mainly used as the core three terminals, and the metal is crisscrossed and overlapped horizontally and vertically to form a network. In the low-frequency state, the three terminals of the MOS are grouped together for layout and routing to ensure that the EMIR is sufficient and uniform; but when this power network reaches the high-frequency state, it will be found that the PSR is seriously deteriorated, even if a shielding line is added to each group of the three terminals, it still does not improve. After continuous testing, it was found that in addition to the capacitor terminal R affecting the high-frequency PSR, the parasitic C of the power network inside the power tube will also cause the output to be raised by VDD as the frequency increases. Then the internal C was continuously tested, and it was found that a large proportion of the parasitic C came from the overlapping parasitics between the power supply and the output metal layers in the power network. Therefore, based on the test results, the power network of the prior art was redesigned.

[0079] In step S1, the LDO layout is obtained and the circuit analysis is performed, such as Figure 2 As shown, it specifically includes the following contents:

[0080] Step S101, extract the layout power network according to the LDO layout, and analyze the small signal difference of the high-frequency PSR circuit. The layout power network refers to the wiring and connection structure between the power supply (VDD) and the ground (GND) in the LDO design. It is responsible for transmitting the power signal to each part of the LDO and ensuring the stability and low noise of the power supply. The design of the power network is crucial to the performance of the LDO because it directly affects the anti-interference ability, load response and overall efficiency of the power supply. By performing high-frequency PSR (power supply rejection) small signal analysis on the layout of the existing power network, the purpose is to identify the response differences of the circuit under high-frequency conditions, including the study of the impact of input power supply noise on the output voltage, in order to find possible performance bottlenecks.

[0081] Specifically, step 101 includes the following process:

[0082] Extract the layout power network, extract the wiring structure between power (VDD) and ground (GND) from the LDO layout, and obtain the power network. Record the trace width, length, material, and hierarchy of the power network. For example, assuming that the trace width of the power network is 10μm, the length is 500μm, copper material is used, and the number of layers is 2, the resistance and inductance of the trace can be calculated by current density and geometry.

[0083] Establish a small signal model: Establish a small signal model for the LDO circuit and extract key parameters such as gain, phase, and output impedance. For example, in small signal analysis, a small signal equivalent circuit can be used to represent the input and output characteristics of the LDO circuit. Use AC analysis tools (such as SPICE, etc.) to simulate and obtain the gain and phase response curves at different frequencies. For example: In small signal analysis, the gain of the LDO is 20dB and the output impedance is 5Ω.

[0084] Select a high-frequency noise source and apply it: Determine the frequency range of the high-frequency noise source (e.g., 1MHz to 100MHz) and apply it to the input of the LDO. Use a signal generator to apply sinusoidal noise signals of different frequencies and observe the response of the LDO output. This process can record the waveforms of the input and output signals for subsequent analysis.

[0085] Measuring PSR changes: Calculate PSR (power supply rejection ratio) by measuring input noise Vin, noise and output noise Vout,noise The PSR can be expressed by the following formula:

[0086] ,

[0087] Record the PSR values ​​at different frequencies, especially the changes in the PSR values ​​in the high frequency range.

[0088] Example:

[0089] Assume that at 1MHz, the PSR is measured to be 40dB, and at 10MHz it drops to 20dB. This result shows that

[0090] The LDO's insufficient suppression capability at high frequencies may cause the system to perform poorly in high-frequency noise environments.

[0091] Step S102, performing circuit post-simulation and analysis according to the high-frequency PSR circuit small signal difference analysis result to obtain the circuit post-simulation analysis result; specifically comprising:

[0092] After the circuit design is completed, post-layout simulation is performed to verify the performance of the circuit under the actual layout. Specifically, post-layout simulation tools (such as Cadence Spectre or HSPICE) can be used to simulate the layout power network to ensure that the circuit model is consistent with the actual layout. Figure 1 parameters, connection methods and layout information.

[0093] Measure the change of PSR value in the simulation, record the PSR value at different frequencies, and obtain the circuit simulation analysis results. According to the change of PSR value, we can analyze how the fluctuation of input power affects the output voltage.

[0094] Example:

[0095] The simulation results show that the PSR is 34dB at 1MHz and drops to 26dB at 10MHz, which is consistent with the previous small signal analysis results, indicating that the PSR performance at high frequencies is insufficient.

[0096] Step S103: Identify key design parameters that affect PSRR based on the circuit post-simulation analysis results. The key design parameters include the resistance and inductance of the power path, the position and size of the decoupling capacitor, etc. This provides a basis for layout design and optimization.

[0097] Among them, the resistance and inductance of the power path: The resistance and inductance of the trace will affect the transmission of high-frequency signals, resulting in a decrease in PSR.

[0098] Location and size of decoupling capacitors: The selection and layout of decoupling capacitors can significantly affect the stability and anti-interference ability of the power supply.

[0099] Step S104: Propose a layout power network optimization strategy based on key design parameters. The layout power network optimization strategy is to ensure that the power network can effectively discharge noise in a high-frequency noise environment and improve the stability and reliability of the LDO.

[0100] The layout power network optimization strategy includes but is not limited to:

[0101] Reduce the trace length and increase the trace width of the power path to reduce resistance and inductance.

[0102] Selecting a larger decoupling capacitor (such as increasing it to 22 μF) and optimizing its layout position can improve PSR performance.

[0103] Lowering the resistance of the trace will help improve current transfer capabilities at high frequencies, allowing the capacitor to absorb and discharge noise more effectively.

[0104] In step S1, the LDO layout is obtained and the layout analysis is performed, such as Figure 3 As shown, it specifically includes the following contents:

[0105] Step S11: Perform post-simulation analysis based on the LDO layout, and identify the shortcomings and deficiencies in the design by post-simulating the layout shortcomings, that is, performing post-simulation analysis on the existing LDO layout. This includes a comprehensive review of the power network layout to find possible design defects and performance issues. For example: PSR drops significantly at certain frequencies, signal interference caused by improper layout, etc.

[0106] The step S11 specifically includes the following process:

[0107] Step S111: Use post-simulation tools (such as Cadence Spectre or HSPICE) to simulate the existing LDO layout to ensure that the circuit model is consistent with the actual layout. Figure 1 parameters, connection methods and layout information.

[0108] Step S112: Perform post-simulation analysis to identify potential design defects and deficiencies in the power supply network. Specifically, it includes:

[0109] Based on the simulation results, analyze the output voltage fluctuation, load response, frequency characteristics, etc. of the LDO, paying special attention to the impact of high-frequency noise on the output. For example, observe the output voltage stability and frequency response under different load conditions.

[0110] Based on the simulation results, possible design defects in the power network are identified, including high impedance paths, long traces, insufficiently filtered capacitors, ground loops, and other problems. When laying out the power network (including VDD, GND, and other power rails), the impedance must be as low as possible. Too long traces may cause attenuation and delay of high-frequency signals, and the formation of ground loops cannot ensure that the signal return path is short and stable. For example, it was found that the VDD trace was too long, resulting in the introduction of high-frequency noise, and the filter capacitor at the output end was far away from the LDO pin, which increased the inductance.

[0111] Based on the simulation results, the PSR values ​​at different frequencies are obtained to identify the changes in PSR at different frequencies. For example, it is found that the PSR of the LDO is 40dB at 1MHz, but drops to 20dB at 10MHz, indicating that the high-frequency suppression capability is insufficient.

[0112] Based on the simulation results, identify whether there are intersections of signal lines with power lines or ground lines in the layout, which may cause signal interference. For example, it is found that some sensitive signal lines are parallel to high-frequency power lines, which may introduce noise interference.

[0113] Example: When performing post-simulation analysis on a certain LDO layout, the following problems were found:

[0114] PSR decrease: In the high frequency range (such as 10MHz), PSR decreases from 40dB to 15dB, indicating that the high frequency noise suppression capability is insufficient.

[0115] Signal interference: The signal line at the output end is routed parallel to the input power line, causing high-frequency noise to be coupled to the signal line through the power line, affecting the output quality.

[0116] Grounding problem: The ground loop is not short enough, causing ground noise to affect output stability, especially under dynamic load conditions.

[0117] Step S12: Summarize a series of processing methods for the layout based on the post-simulation analysis results of the LDO layout. For the defects found in the post-simulation analysis, propose specific processing methods to optimize the design of the LDO. The series of processing methods include but are not limited to:

[0118] 1) Routing optimization:

[0119] Shorten trace length: Redesign the power and ground traces and try to shorten the trace length to reduce inductance and resistance.

[0120] Increase trace width: Increase the width of input and output traces, for example to 20 μm, to reduce resistance and improve high-frequency performance.

[0121] 2) Decoupling capacitor optimization:

[0122] Choose a suitable decoupling capacitor: Increase the value of the decoupling capacitor, for example, increase the value of the decoupling capacitor from 10μF to 22μF to improve the decoupling capability of low and high frequencies.

[0123] Optimize layout: Place the decoupling capacitors as close to the input and output of the LDO as possible to reduce the transmission of power supply noise.

[0124] 3) Add bypass capacitors:

[0125] In high frequency cases, add additional high frequency bypass capacitors (such as 1μF ceramic capacitors) to improve the ability to suppress high frequency noise.

[0126] Preferably, in some embodiments of the present invention, in step S1, the LDO layout is obtained and the layout analysis is performed, and the method further comprises: step S13, performing iterative optimization and verification of the layout according to a series of processing methods. Figure 4 As shown, specifically including:

[0127] Step S131, modifying the LDO layout according to the series of processing methods, including redesigning the power and ground routing, shortening the routing length, widening the important routing, adjusting the layout of the decoupling capacitors closer to the input and output ends of the LDO, and adding additional high-frequency bypass capacitors, etc.

[0128] Step S132, perform post-simulation analysis on the modified LDO layout again to obtain the post-simulation analysis result. The shortcomings and deficiencies of the modified LDO layout design are found. Specifically, this step re-performs circuit simulation, and the post-simulation process is the same as the aforementioned step S11, which will not be repeated here.

[0129] Step S133: Verify the improvement effect of the series of processing methods according to the post-simulation analysis results, including the improvement of PSR, output stability, signal interference and other aspects.

[0130] In some embodiments of the present invention, the verification can be performed by comparing the new post-simulation results with the previous results to verify the effectiveness of the optimization measures. For example, by comparing the new and old PSR values, it is found that the PSR is significantly improved at high frequencies, indicating that the high-frequency noise suppression capability is improved.

[0131] In some embodiments of the present invention, the verification can be performed by checking the waveform of the output signal to ensure that the output voltage fluctuation is within an acceptable range under dynamic load conditions to verify signal integrity. For example, a reduction in the fluctuation amplitude of the output voltage when the load changes indicates improved output stability.

[0132] Step S134: According to the improvement effect, the layout is iterated and post-simulated again, that is, steps S131-S133 are repeated until the layout performance meets the design requirements, wherein the design requirements include power network and component layout and PSR performance.

[0133] S2. Redesign the power supply network based on the circuit analysis and layout analysis results.

[0134] Based on a full analysis of the circuit analysis results and layout analysis results, redesign the power network, which may include adjusting the power path, adding decoupling capacitors, optimizing the ground layout, etc. Ensure that the new design can effectively reduce the impact of input noise on the output and improve the overall PSR performance.

[0135] In a specific embodiment of the present invention, the above-mentioned method for redesigning a power supply network of the present invention is applied, and the specific measures are: where overlapping layers appear in the power supply network, all the middle layers across the layers are treated as ground wires.

[0136] Example: Taking Samsung 4n as an example, the existing technology is that metal 12 is horizontal, metal 11 is vertical, metal 10 is horizontal... In this way, countless overlapping parasitic C will inevitably be generated for power wiring. However, the above method of the present invention changes the direction of metal 10, ① replaces the original metal 11 with metal 10, and ② adds a metal 12 ground wire that meets the thinnest drc between the VDD and output of metal 12, and the empty metal 11 is isolated by inserting a metal 11 ground wire connected to the metal 12 ground wire in the same direction as metal 10 at the place where metal 12 overlaps metal 10. Thereby greatly reducing the internal parasitic C (if the parasitic C is not satisfied, the remaining metals can be similarly applied, and attention should be paid to meeting EMIR).

[0137] The present invention uses circuit analysis and layout analysis, in-depth analysis of the existing LDO layout, post-simulation analysis and continuous iterative optimization of the layout, and finally realizes the design of high-performance high and low voltage difference linear regulators, which can effectively improve the PSRR of the LDO and ensure the stability and reliability of the regulator under various working conditions.

[0138] Embodiment 2

[0139] This embodiment also provides a high-performance high-low dropout linear regulator PSRR layout method, which is different from the first embodiment of the present invention in that: step S1, obtaining the LDO layout, performing circuit analysis and layout analysis, and also includes: establishing a feedback mechanism to form a closed-loop feedback of the circuit analysis and layout analysis. Establishing the feedback mechanism specifically includes the following process:

[0140] Establishing mutual feedback between step S101 and step S11;

[0141] Establishing mutual feedback between step S104 and step S12;

[0142] Among them, establishing mutual feedback between step S101 and step S11 includes: comparing the first PSR change characteristic obtained from the small signal difference of the high-frequency PSR circuit with the second PSR change characteristic obtained by post-simulation analysis based on the LDO layout; and proposing layout optimization suggestions based on the comparison results.

[0143] When the comparison results show that the changes in PSR are consistent, such as both showing a decrease in PSR value with increasing frequency, that is, the results of circuit analysis and layout analysis are consistent, both indicating insufficient high-frequency suppression capability; then the LDO layout needs to be optimized, including: shortening the VDD and GND routing, reducing inductance and resistance, increasing the number or capacity of filter capacitors and placing them closer to the LDO pins, using wider metal routing to reduce impedance, and other optimization strategies.

[0144] When the comparison results show that the PSR change trends are inconsistent, such as the first PSR change characteristic shows that the PSR value decreases with the increase of frequency, and the second PSR change characteristic shows that the PSR value remains unchanged or increases slowly with the increase of frequency, that is, the circuit analysis and layout analysis results are inconsistent, it is necessary to re-execute step S101 and step S11, and establish mutual feedback again based on the results of the re-execution.

[0145] The mutual feedback between step S104 and step S12 is established, including: performing iterative optimization and verification of the layout according to the layout power network optimization strategy and the series of layout processing methods. Figure 5 As shown, specifically including:

[0146] Step S201, comparing the layout power network optimization strategy and the series of processing methods of the layout, and extracting the comparison results with consistent strategies;

[0147] Step S202: based on the strategy-consistent comparison results, modify the LDO layout, including redesigning the power and ground routing, shortening the routing length, widening important routing, adjusting the layout of the decoupling capacitors closer to the input and output ends of the LDO, and adding additional high-frequency bypass capacitors.

[0148] Step S203, perform post-simulation analysis on the modified LDO layout again to obtain the post-simulation analysis result. The shortcomings and deficiencies of the modified LDO layout design are found. Specifically, this step re-performs circuit simulation, and the post-simulation process is the same as the aforementioned step S11, which will not be repeated here.

[0149] Step S204: Verify the improvement effect of the strategy-consistent comparison results based on the post-simulation analysis results, including improvements in PSR, output stability, signal interference, etc.

[0150] In some embodiments of the present invention, the verification can be performed by comparing the new post-simulation results with the previous results to verify the effectiveness of the optimization measures. For example, by comparing the new and old PSR values, it is found that the PSR is significantly improved at high frequencies, indicating that the high-frequency noise suppression capability is improved.

[0151] In some embodiments of the present invention, the verification can be performed by checking the waveform of the output signal to ensure that the output voltage fluctuation is within an acceptable range under dynamic load conditions to verify signal integrity. For example, a reduction in the fluctuation amplitude of the output voltage when the load changes indicates improved output stability.

[0152] Step S205: According to the improvement effect, the layout is iterated and post-simulated again, that is, steps S201-S204 are repeated until the layout performance meets the design requirements, wherein the design requirements include power network and component layout and PSR performance.

[0153] The present invention establishes a feedback mechanism of circuit analysis and layout analysis to realize closed-loop feedback of LDO layout, links the various stages of circuit analysis and layout analysis, iterates and optimizes the layout design through continuous comparison and feedback, and finally realizes a high-performance high and low voltage difference linear regulator design, which can effectively improve the PSRR of the LDO and ensure the stability and reliability of the regulator under various working conditions.

[0154] Embodiment 3

[0155] like Figure 6 As shown, the present invention also provides an electronic device 2, including a processor 21 and a memory 22, the memory 22 is used to store computer program code, the computer program code includes computer instructions, when the processor 21 executes the computer instructions, the electronic device executes a high-performance high and low voltage difference linear regulator PSRR layout method of the above embodiment.

[0156] The electronic device 2 also includes an input device 24 and an output device 23. The processor 21, the memory 22, the input device 24 and the output device 23 are coupled via a connector, and the connector includes various interfaces, transmission lines or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0157] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0158] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0159] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0160] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A high-performance high-low voltage drop linear regulator PSRR layout method, characterized in that: The steps include: S1. Obtain the LDO layout and perform circuit analysis and layout analysis; S2. Redesign the power supply network based on the circuit analysis and layout analysis results; Among them, in step S1, the LDO layout is obtained and the circuit analysis is performed, which specifically includes the following contents: Step S101, extracting the layout power network according to the LDO layout, and analyzing the small signal difference of the high-frequency PSR circuit; Step S102, performing circuit post-simulation and analysis according to the high-frequency PSR circuit small signal difference analysis result to obtain the circuit post-simulation analysis result; Step S103, identifying key design parameters that affect PSRR based on the circuit post-simulation analysis results; Step S104: Propose a layout power network optimization strategy based on key design parameters.

2. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 1, characterized in that: In step S1, the LDO layout is obtained and the layout analysis is performed, which specifically includes the following contents: Step S11, performing post-simulation analysis based on the LDO layout to identify shortcomings and deficiencies in the design; Step S12, summarizing a series of processing methods for the layout according to the post-simulation analysis results of the LDO layout; Step S13: Perform layout iterative optimization and verification according to the series processing method.

3. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 2, characterized in that: The step S11 specifically includes the following process: Step S111, using a post-simulation tool to simulate the LDO layout to ensure that the circuit model is consistent with the actual layout, including component parameters, connection methods and layout information; Step S112: Perform post-simulation analysis to identify potential design defects and deficiencies in the power supply network.

4. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 3, characterized in that: The step S112 includes: According to the simulation results, the output voltage fluctuation, load response and frequency characteristics of LDO are analyzed; Based on simulation results, design flaws in the power network are identified, including high-impedance paths, long traces, inadequately filtered capacitors, and ground loops. According to the simulation results, the PSR values ​​at different frequencies are obtained, and the changes of PSR at different frequencies are identified; Based on the simulation results, identify whether there are crossings between signal lines and power lines or ground lines in the layout.

5. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 2, characterized in that: The step S13 specifically includes: Step S131, modifying the LDO layout according to the series processing method; Step S132, performing post-simulation analysis on the modified LDO layout again to obtain the post-simulation analysis result; Step S133, verifying the improvement effect of the series of processing methods according to the post-simulation analysis results; Step S134: According to the improvement effect, the layout is iterated and post-simulation verification is performed again.

6. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 1, characterized in that: The step S101 includes the following process: Extract the wiring structure between power supply and ground from the LDO layout to obtain the power supply network; Establish a small signal model for the LDO circuit and extract key parameters; Determine the frequency range of the high-frequency noise source and apply it to the input of the LDO; Calculate the PSR and record the PSR values ​​at different frequencies.

7. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 1, characterized in that: The step S102 specifically includes: After the circuit design is completed, post-simulation is performed to verify the performance of the circuit under the actual layout; Measure the change of PSR value in the post-simulation, record the PSR value at different frequencies, and obtain the circuit post-simulation analysis results.

8. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 2, characterized in that: Step S1, obtaining the LDO layout, performing circuit analysis and layout analysis, and also includes: establishing a feedback mechanism to form a closed-loop feedback of the circuit analysis and layout analysis. The establishment of the feedback mechanism specifically includes the following process: Establishing mutual feedback between step S101 and step S11; A mutual feedback between step S104 and step S12 is established.

9. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 8, characterized in that: Establishing mutual feedback between step S101 and step S11, including: comparing a first PSR variation characteristic obtained from a small signal difference of a high-frequency PSR circuit with a second PSR variation characteristic obtained by post-simulation analysis based on an LDO layout; and proposing layout optimization suggestions based on the comparison results.

10. A high performance high and low voltage drop linear regulator PSRR layout method according to claim 9, characterized in that: Establishing mutual feedback between step S104 and step S12 includes: performing iterative optimization and verification of the layout according to the layout power network optimization strategy and the series of layout processing methods; specifically including: Step S201, comparing the layout power network optimization strategy and the series of processing methods of the layout, and extracting the comparison results with consistent strategies; Step S202, modifying the LDO layout according to the strategy-consistent comparison results; Step S203, performing post-simulation analysis on the modified LDO layout again to obtain the post-simulation analysis result; Step S204, verifying the improvement effect of the comparison results with consistent strategies according to the post-simulation analysis results; Step S205: According to the improvement effect, the layout is iterated and post-simulation verification is performed again.

Images