Capacitor design prediction method for chip self-test

Abstract

The invention relates to the technical field of chip design, in particular to a capacitor design prediction method for chip self-testing, which comprises the following steps: acquiring a power supply voltage, setting a DUT maximum power supply current, a transient current percentage and a voltage drop allowed by capacitor discharge, and calculating a lower limit of a total capacitance value of a capacitor on a chip board; calculating the ESR value of the shunt capacitor under the estimated maximum ripple of the Bulk capacitor; carrying out model selection on the Buck capacitor; selecting a plurality of models and a plurality of numbers of Buck capacitors, and calculating a total equivalent resistance value of the Buck capacitors; calculating the total capacitance value of the Buck capacitors according to the models and the number of the Buck capacitors; calculating a capacitance estimated maximum value of the ceramic capacitor according to the total equivalent resistance value of the Buck capacitor; and selecting a plurality of models and a plurality of numbers of ceramic capacitors, calculating the total capacitance value of the ceramic capacitors, and constraining the total capacitance value of the ceramic capacitors and the total capacitance value of the Buck capacitor. The problem of reasonable matching of the Bulk capacitor and the ceramic capacitor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a capacitance design prediction method for chip self-testing. Background Art

[0002] Circuit boards are an important part of the physical support and signal transmission of electronic products; chip test carriers are interface circuit boards used for chip testing that connect the chip to be tested and the test machine, referred to as test carriers.

[0003] With the rapid development of chip technology and the increase in chip complexity, chip testing needs to be paid more and more attention; the carrier of chip functional testing is the test substrate, and the design and manufacture of the test substrate is an indispensable part in the entire semiconductor industry.

[0004] For the chip automatic testing industry, test machine manufacturers provide standard test machines, so the test board as a carrier must also strictly comply with the specifications of the test machine. Specifically, the test board's dimensions, thickness, location of the test channel, location of the chip to be tested, etc. must all be designed in strict accordance with the specifications of the test machine.

[0005] Power supply design is a very important part of chip testing. As the driving force of the chip, the performance of the power supply directly affects the working state of the chip. Especially on high-performance chips, the chip may switch between low power consumption and high power consumption states arbitrarily, and the requirements for power supply stability are further increased.

[0006] Bulk capacitors are used in power supply systems of electronic designs. They can store energy and filter (the energy storage function is greater than the filtering function). They are usually polarized capacitors with large capacitance values.

[0007] Ceramic capacitors are used in power supply systems of electronic designs. They can store energy and filter (the filtering effect is greater than the energy storage effect). They are usually non-polar capacitors with small capacitance values.

[0008] The test board has the characteristics of larger board size, higher board thickness, higher performance requirements, shorter design cycle and higher design cost. In the design of high-current chip test board, in order to better improve the stability of chip power supply, bulk capacitors and ceramic capacitors need to be designed closer to the chip, that is, designed on the chip test board. Therefore, how to achieve a reasonable combination of bulk capacitors and ceramic capacitors is an urgent problem to be solved. Summary of the invention

[0009] In view of the shortcomings of the existing methods, the present invention solves the problem of reasonable matching of bulk capacitors and ceramic capacitors.

[0010] The technical solution adopted by the present invention is: a capacitance design prediction method for chip self-test includes the following steps:

[0011] Step 1: Obtain the supply voltage of the test machine, set the maximum supply current of the DUT, the transient current percentage, and the voltage drop allowed for capacitor discharge, and calculate the lower limit of the total capacitance value of the capacitors on the chip board;

[0012] Step 2: Use the theoretical ESR of the Bulk capacitor as an index to determine whether the combination of the actual Bulk capacitor models and quantities is reasonable, and calculate the ESR value of the parallel capacitors under the estimated maximum ripple of the Bulk capacitor;

[0013] Step 3: Select the Buck capacitor using the capacitor resonance frequency and the capacitor attenuation factor;

[0014] As a preferred embodiment of the present invention, Step 3 specifically includes:

[0015] Set the threshold of the capacitor resonance frequency f cap and the capacitor attenuation factor D d . When f cap , D d meet the threshold conditions, the Buck capacitor model meets the design requirements.

[0016] As a preferred embodiment of the present invention, the thresholds of the capacitor resonance frequency f cap and the capacitor attenuation factor D d include: The first threshold: f cap <f0 and D d >D0; The second threshold: f cap =f1 and D d >D1; The third threshold: f2 =<f cap <=f3 and D d >D2.

[0017] As a preferred embodiment of the present invention, when the capacitor resonance frequency f cap and the capacitor attenuation factor D d meet the first threshold or the second threshold or the third threshold, the Buck capacitor model meets the design requirements.

[0018] Step 4: Select several models and several numbers of Buck capacitors, and calculate the total equivalent resistance of the Buck capacitors;

[0019] As a preferred embodiment of the present invention, the formula for the total equivalent resistance of the Buck capacitors is:

[0020]

[0021] where i is the serial number of the Buck capacitor model, k jis the number of a certain type of Buck capacitor; M is the total number of Buck capacitor models; N is the total number of a certain Buck capacitor model, ESR Buck_i is the equivalent resistance value of a certain Buck capacitor model.

[0022] As a preferred embodiment of the present invention, the total value of the equivalent resistance of the Buck capacitor is constrained, and the constraint condition is ESR Bulk <ESR max_ripple .

[0023] Step 5. Calculate the total capacitance of the Buck capacitor according to the model and number of Buck capacitors;

[0024] Step 6: According to ESR Bulk Calculate the estimated maximum capacitance of ceramic capacitors;

[0025] Step 7. Select several models and numbers of ceramic capacitors, calculate the total capacitance of the ceramic capacitors, and constrain the total capacitance of the ceramic capacitors and the total capacitance of the Buck capacitors.

[0026] As a preferred embodiment of the present invention, the condition for constraining the total capacitance of the ceramic capacitor is: C ceramic <C ceramic_max .

[0027] As a preferred embodiment of the present invention, the condition for constraining the total capacitance of the ceramic capacitor and the total capacitance of the Buck capacitor is: C ceramic +C Bulk >C total_ripple .

[0028] As a preferred embodiment of the present invention, a capacitance design prediction system for chip self-test includes: a memory for storing instructions executable by a processor; and a processor for executing the instructions to implement a capacitance design prediction method for chip self-test.

[0029] As a preferred embodiment of the present invention, a computer readable medium stores computer program codes, and when the computer program codes are executed by a processor, a capacitance design prediction method for chip self-test is implemented.

[0030] Beneficial effects of the present invention:

[0031] 1. The selection and quantity ratio of capacitors can be planned before the chip design begins, which has a strong guiding significance for chip design;

[0032] 2. The prediction method of the present invention can be realized through Excel macro, which has the advantages of easy use and high accuracy;

[0033] 3. Greatly shorten the design time of chip test projects and reduce the number of iterations of chip test projects. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flow chart of the capacitance design prediction method for chip self-test of the present invention;

[0035] Figure 2 is a schematic diagram of a chip testing system;

[0036] Figure 3 It is a schematic diagram of a system in which a Buck capacitor and a ceramic capacitor are arranged on a chip test carrier board according to the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described below in conjunction with the accompanying drawings and embodiments. This figure is a simplified schematic diagram, which only illustrates the basic structure of the present invention in a schematic manner, and therefore it only shows the components related to the present invention.

[0038] like Figure 1 As shown, a capacitance design prediction method for chip self-test includes the following steps:

[0039] like Figure 2 This is a schematic diagram of a chip testing system. The three important structures in chip testing include: a test machine, which is responsible for providing power supply; a test carrier as a medium connecting the test machine and the chip to be tested; and the chip to be tested is the test object.

[0040] like Figure 3 As shown, the test machine power supply is UHC4 power supply, which has low voltage, high current and fast transient application, which amplifies the problem of path Z impedance, as shown in the formula V DUT =V ATE_HC -I*R cable -L cable *d I / d t If the bulk capacitor is placed on the chip test board instead of inside the power supply system of the test machine, the ripple caused by the voltage drop of the test board (ATE) control loop can be greatly reduced.

[0041] The UHC4 power channel of the present invention requires that the Bulk capacitor of the power supply be placed on the chip board to be tested, which is the biggest difference from other DPS power channels; the Bulk capacitor on the test board is part of the test board power supply system, which not only provides phase stability for the test board power control loop, but also provides power for the chip to be tested while waiting for the power supply response.

[0042] Figure 3This is the basic theory of the design method of bulk capacitors in high-current chip testing. The chip under test that requires high current power supply will encounter a large transient voltage drop during the test. For example, when the chip suddenly switches from a low-power standby state to a high-power state running at full computing power, the voltage will be unstable. In severe cases, the chip may not work or even be damaged.

[0043] The introduction of bulk capacitors can effectively improve voltage stability. Bulk capacitors can be directly designed into the power supply system inside the test machine.

[0044] In addition, the stability of the power supply system is also related to ceramic capacitors. Relatively speaking, ceramic capacitors have a slightly smaller impact on the stability of the power supply system than bulk capacitors.

[0045] In the design of a high-current chip test carrier, in order to better improve the stability of the chip power supply, bulk capacitors and ceramic capacitors need to be designed closer to the chip, that is, designed on the chip test carrier.

[0046] Therefore, it is very important to realize the reasonable combination of bulk capacitors and ceramic capacitors. Simply speaking, the combination of bulk capacitors and ceramic capacitors can be divided into two aspects:

[0047] 1. What type of capacitor to use? The differences between different types of capacitors include: capacitance value, equivalent resistance, equivalent inductance, manufacturer, etc.

[0048] 2. How to select the quantity of capacitors of different models, how to predict the selection and quantity ratio of bulk capacitors and ceramic capacitors, and whether the prediction results can meet the performance requirements of the current chip in a quick and accurate way are issues that need to be solved urgently.

[0049] Step 1: Get the power supply voltage V of the test machine Supply , set the DUT maximum supply current I DUT , transient current percentage PCT Transient The permissible voltage drop of the capacitor discharge is PCT drop ; Calculate the lower limit of the total capacitance C on the chip board total_ripple , the formula is:

[0050]

[0051] Among them, t Supply_response The response time of the power supply is taken as a constant of 0.00004 seconds; PCT drop The additional multiplication factor of 1 / 2 is due to the voltage drop caused by the capacitor's self-discharge when working.

[0052] The capacitors required for the power supply system consist of two parts: Bulk capacitors and ceramic capacitors. The sum of the capacitance values of the Bulk capacitors and the ceramic capacitors needs to be greater than C total_ripple The capacitance values of the Bulk capacitors and the ceramic capacitors are not in a fixed ratio. It is necessary to determine the ratio of the two types of capacitors, that is, the matching of the model and quantity.

[0053] Step 2: Use the theoretical ESR (equivalent resistance) of the Bulk capacitor as an indicator to determine whether the combination of the actual Bulk capacitor model and quantity is reasonable, and calculate the ESR value ESR of the parallel capacitors under the estimated maximum ripple of the Bulk capacitor max_ripple The formula is:

[0054]

[0055] Step 3: Select the Buck capacitor using the capacitor resonance frequency f cap and the capacitor attenuation factor D d ;

[0056] Set the thresholds for the capacitor resonance frequency and the capacitor attenuation factor. When f cap and D d meet the threshold conditions, the Buck capacitor model meets the design requirements;

[0057] The thresholds for the capacitor resonance frequency and the capacitor attenuation factor include: The first threshold: f cap < f0 and D d > D0; The second threshold: f cap = f1 and D d > D1; The second threshold: f2 = < f cap <= f3 and D d > D2;

[0058] In this embodiment, f0 = 100 kHz; f1 = 150 kHz; f2 = 200 kHz; f3 = 250 kHz; D0 = 0.5; D1 = 1; D2 = 2.5;

[0059] When f cap and D d meet the first threshold or the second threshold or the third threshold, the Buck capacitor model meets the design requirements.

[0060] Step 4: Select several models and several numbers of Buck capacitors, and calculate the total equivalent resistance ESR of the Buck capacitors Bulk The formula is:

[0061]

[0062] where i is the serial number of the Buck capacitor model, k jis the number of a certain type of Buck capacitor; M is the total number of Buck capacitor models; N is the total number of a certain Buck capacitor model, ESR Buck_i is the equivalent resistance value of a certain Buck capacitor model.

[0063] Using ESR max_ripple ESR Bulk Perform the first capacitance constraint, the first capacitance constraint condition is: ESR Bulk <ESR max_ripple .

[0064] Under the premise of meeting the capacitance constraint condition, ESR Bulk The smaller the value, the better the performance.

[0065] Step 5. Calculate the total capacitance of the Buck capacitor based on the model and number of Buck capacitors obtained in step 4. The formula is:

[0066]

[0067] Where i is the Buck capacitor model number, k is j is the number of Buck capacitors of a certain model, C Buck_i is the capacitance value of a certain Buck capacitor model.

[0068] Step 6: Based on the total equivalent resistance ESR of the Buck capacitor Bulk Calculate the estimated maximum capacitance C of ceramic capacitors ceramic_max , the formula is:

[0069] C ceramic_max =a / ESR Bulk

[0070] Among them, a is a constant, a=367.

[0071] Step 7. Select several models and numbers of ceramic capacitors and calculate the total capacitance C of the ceramic capacitors. ceramic , the formula is:

[0072]

[0073] Among them, i' is the model number of the ceramic capacitor, l j’ is the number of ceramic capacitors of a certain type, C ceramic_i' is the capacitance value of a certain ceramic capacitor model;

[0074] Using C ceramic_max C ceramic Perform the second capacitance constraint, the second capacitance constraint condition is: C ceramic <C ceramic_max ;

[0075] Set the third capacitance capacity constraint. The third capacitance capacity constraint condition is:

[0076] C ceramic +C Bulk >C total_ripple Specific embodiment one:

[0078] Input basic design requirements:

[0079] Supply voltage V Supply :0.8V; Maximum supply current I DUT : 40A; Capacitor discharge allowable voltage drop PCT droop :5%; Transient current percentage PCT Transient : 100%;

[0080] Calculate the lower limit of the total capacitance of the chip board C total_ripple :8000uf;

[0081] Calculate the ESR value of the parallel capacitor under the estimated maximum ripple max_ripple : 0.5mohm;

[0082] Table 1 matches the models and quantities of Bulk capacitors:

[0083]

[0084] Calculate the total equivalent resistance ESR of the Buck capacitor Bulk : 0.395mohm;

[0085] It can be seen that the ESR value of the bulk capacitor after matching is lower than the ESR value of the parallel capacitor under the maximum ripple estimated by all bulk capacitors in theoretical calculation: 0.395<0.5;

[0086] Calculate the total capacitance of these bulk capacitors: 7980uf;

[0087] Calculate the theoretical maximum value of ceramic capacitor: 929.37uf;

[0088] Table 2 Ceramic capacitor model and quantity matching table

[0089]

[0090] Calculate the total capacitance of these ceramic capacitors: 541.3uf;

[0091] The total capacitance of the ceramic capacitors is lower than the calculated theoretical maximum value of the ceramic capacitors: 541.3 < 929.37; the total capacitance of the bulk capacitors and ceramic capacitors is greater than the calculated total capacitance required for system stability (lower limit): 7980 + 541.3 > 8000.

[0092] It indicates that the current design scheme of bulk capacitors and ceramic capacitors meets the relevant index requirements of the current project.

[0093] Embodiment 2:

[0094] Input basic design requirements:

[0095] Supply voltage V Supply :0.6V; Maximum supply current I DUT : 80A; Capacitor discharge allowable voltage drop PCT droop :5%; Transient current percentage PCT Transient : 100%;

[0096] Calculate the lower limit of the total capacitance of the chip board C total_ripple :21333uf;

[0097] Calculate the ESR value of the parallel capacitor under the estimated maximum ripple max_ripple : 0.188mohm;

[0098] Table 3 matches the models and quantities of bulk capacitors:

[0099]

[0100] Calculate the total equivalent resistance ESR of the Buck capacitor Bulk : 0.306mohm;

[0101] It can be seen that the ESR value of the bulk capacitor after matching is lower than the ESR value of the parallel capacitor under the maximum ripple estimated by all bulk capacitors in theoretical calculation: 0.306>0.188, which does not meet the standard;

[0102] Calculate the total capacitance of these bulk capacitors: 10470uf;

[0103] Calculate the theoretical maximum value of ceramic capacitor: 1198.87uf;

[0104] Table 4 Ceramic capacitor model and quantity matching table

[0105]

[0106] Calculate the total capacitance of these ceramic capacitors: 1343uf;

[0107] The total capacitance of the ceramic capacitors after combination is higher than the calculated theoretical maximum value of the ceramic capacitors: 1343>1198.87, which does not meet the standard; the total capacitance of the bulk capacitors and ceramic capacitors after combination is lower than the calculated total capacitance value (lower limit) required for system stability: 10470+1343<21333, which does not meet the standard.

[0108] This indicates that the current design of bulk capacitors and ceramic capacitors does not meet the relevant index requirements of the current project.

[0109] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A capacitance design prediction method for chip self-test, characterized in that: The following steps are involved: Step 1: Obtain the power supply voltage of the test machine, set the maximum power supply current of the DUT, the transient current percentage, and the voltage drop allowed for capacitor discharge, and calculate the lower limit of the total capacitance of the chip board; Step 2: Use the theoretical ESR of bulk capacitors as an indicator to determine whether the actual bulk capacitor model and quantity are reasonable, and calculate the ESR value of the parallel capacitor under the estimated maximum ripple of the bulk capacitor; Step 3: Select the Buck capacitor using the capacitor resonant frequency and capacitor attenuation factor; Step 4: Select several models and several numbers of Buck capacitors, and calculate the total equivalent resistance of the Buck capacitors; Step 5. Calculate the total capacitance of the Buck capacitor according to the model and number of Buck capacitors; Step 6. Calculate the estimated maximum capacitance of the ceramic capacitor based on the total equivalent resistance of the Buck capacitor; Step 7. Select several models and numbers of ceramic capacitors, calculate the total capacitance of the ceramic capacitors, and constrain the total capacitance of the ceramic capacitors and the total capacitance of the Buck capacitors.

2. The capacitance design prediction method for chip self-test according to claim 1, characterized in that: Step three specifically includes: Set the capacitor resonant frequency f cap and capacitance attenuation factor D d The threshold, when f cap , D d When the threshold conditions are met, the Buck capacitor model meets the design requirements.

3. The capacitance design prediction method for chip self-test according to claim 2, characterized in that: Capacitive resonance frequency f cap and capacitive attenuation factor D d The thresholds include: The first threshold: f cap < f0 and D d > D0; The second threshold: f cap = f1 and D d > D1; The second threshold: f2 = < f cap <= f3 and D d > D2.

4. The capacitance design prediction method for chip self-test according to claim 3, characterized in that: When the capacitor resonant frequency f cap and capacitance attenuation factor D d When the first threshold, the second threshold, or the third threshold is met, the Buck capacitor model meets the design requirements.

5. The capacitance design prediction method for chip self-test according to claim 1, characterized in that: The formula for the total equivalent resistance of the Buck capacitor is: Where i is the Buck capacitor model number, k is j is the number of a certain type of Buck capacitor; M is the total number of Buck capacitor models; N is the total number of a certain Buck capacitor model, ESR Buck_i is the equivalent resistance value of a certain Buck capacitor model.

6. The capacitance design prediction method for chip self-test according to claim 1, characterized in that: Constrain the total value of the Buck capacitor's equivalent resistance, and the constraint condition is ESR Bulk <ESR max_ripple .

7. The capacitance design prediction method for chip self-test according to claim 1, characterized in that: The condition that constrains the total capacitance of ceramic capacitors is: C ceramic <C ceramic_max .

8. The capacitance design prediction method for chip self-test according to claim 1, characterized in that: The condition for constraining the total capacitance of the ceramic capacitor and the total capacitance of the Buck capacitor is: C ceramic +C Bulk >C total_ripple .

9. A capacitance design prediction system for chip self-test, characterized in that: include: a memory for storing instructions executable by a processor; A processor, used for executing instructions to implement the capacitance design prediction method for chip self-test as described in any one of claims 1-8.

10. A computer readable medium storing computer program code, characterized in that: When the computer program code is executed by a processor, the computer program code implements the capacitance design prediction method for chip self-test as claimed in any one of claims 1 to 8.

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