DNN calculation engine

Abstract

The invention discloses a DNN calculation engine, and relates to the field of deep learning. The calculation engine comprises a compiler used for obtaining engine parameters, an input feature cache block used for reading original input feature maps, an input feature rearrangement module used for feature map rearrangement, a first selector used for mode switching and a second selector used for mode switching. The weight cache block is used for reading convolutional layer parameters of the DNN network; and the calculation array is used for realizing convolutional layer calculation. Compared with the prior art, the computing engine is more flexible and universal, and is more suitable for serving as a single computing engine in a multi-core DNN accelerator system.

Description

Technical Field

[0001] The present invention relates to the field of deep learning technology, and more specifically, to a DNN computing engine. Background Art

[0002] With the rapid development of artificial intelligence technology, Deep Neural Networks (DNNs) have become a key tool for solving many complex problems such as image recognition, speech recognition, and natural language processing. However, with the rapid increase in the complexity of task scenarios, single-core DNN accelerator systems are difficult to meet the computing performance requirements of such scenarios, while multi-core DNN accelerator systems composed of multiple single-core DNN accelerators have higher performance and have therefore been widely studied.

[0003] However, current single-core DNN accelerators mainly focus on hardware design for specific DNN networks, so they are less flexible and cannot be expanded. When used in a multi-core DNN accelerator system, it is difficult to obtain performance proportional to the number of DNN accelerators. In addition, due to the specificity of the single-core DNN accelerator design, it is difficult to deploy more flexible bandwidth allocation and task scheduling strategies in such multi-core DNN accelerator systems, making it difficult for the overall performance of the system to be significantly improved through multi-core. Summary of the invention

[0004] In order to overcome the deficiencies of the multi-core DNN accelerator described in the above-mentioned prior art in terms of insufficient flexibility and versatility, the present invention provides a DNN computing engine.

[0005] In order to solve the above technical problems, the technical solution of the present invention is as follows: In a first aspect, a DNN computing engine includes: A compiler, used to obtain engine parameters; the engine parameters include data precision, input channel expansion coefficient and output channel expansion coefficient; An input feature cache block is used to read and cache the original input feature map to be convolved in the DNN network; wherein the number of the input feature cache blocks is determined according to the input channel expansion coefficient; An input feature reordering module is used to reorder the original input feature map based on im2col, and output the reordered feature map to convert the convolution operation into a matrix-vector multiplication; A first selector, used for mode switching; wherein, when the computing engine works in the first-layer computing mode, the reordered feature map is selected as the output; when the computing engine works in the non-first-layer computing mode, the first selector selects the original input feature map as the output; A weight cache block, used to read and cache the convolution layer parameters of the DNN network; wherein the number of the weight cache blocks is determined according to the output channel expansion coefficient, and the data bit width of the weight cache block is determined according to the input channel expansion coefficient and the data precision; A computing array includes a plurality of parallel computing channels, and is used to read the output of the first selector and the convolution layer parameters to perform convolution layer calculations to obtain an output feature map; wherein the number of the computing channels is determined according to the output channel expansion coefficient.

[0006] In a second aspect, a multi-core DNN accelerator system includes several DNN computing engines as described in the first aspect.

[0007] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The present invention discloses an accelerator hardware system architecture suitable for a DNN network, comprising a plurality of input feature cache blocks, a plurality of weight cache blocks, an input feature rearrangement module, a first selector for mode switching, and a computing array; in addition, based on engine parameters introduced by a compiler, DNN computing engines of different sizes can be generated according to different application scenarios, such as bandwidth constraints / computing resource constraints, and the system has good scalability and high computing throughput, and is more flexible in bandwidth usage and task scheduling, and is more suitable as a single computing engine in a multi-core DNN accelerator system. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the structure of the computing engine described in the embodiment of the present application; Figure 2 A schematic diagram of the process of the non-first-layer computing mode described in the embodiment of the present application; Figure 3 A schematic diagram of the process flow of the first-layer calculation mode described in the embodiment of the present application; Figure 4 Schematic diagram of the structure of the input feature rearrangement module described in the embodiment of the present application; Figure 5 Schematic diagram of the calculation and data transmission granularity of the computing engine described in the embodiment of the present application. DETAILED DESCRIPTION

[0009] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged in appropriate cases, which is only to describe the distinction mode adopted by the objects of the same attributes in the embodiments of the present application when describing. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment containing a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment. The term "determine" widely covers various actions, and may include acquisition, calculation, calculation, processing, derivation, investigation, search (for example, search in a table, database or other data structure), ascertainment, and similar actions, and may also include reception (for example, receiving information), access (for example, accessing data in a memory) and similar actions, and may also include generation, creation, establishment and similar actions, as well as parsing, selection, selection and similar actions, etc. The relevant definitions of other terms will be given in the following description.

[0010] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0011] The drawings are for illustrative purposes only and should not be construed as limiting the present patent; In order to better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0012] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0013] This embodiment provides a DNN computing engine, referring to FIG1 , including: A compiler, used to obtain engine parameters; the engine parameters include data precision, input channel expansion coefficient and output channel expansion coefficient; An input feature cache block is used to read and cache the original input feature map to be convolved in the DNN network; wherein the number of the input feature cache blocks is determined according to the input channel expansion coefficient; An input feature reordering module is used to reorder the original input feature map based on im2col, and output the reordered feature map to convert the convolution operation into a matrix-vector multiplication; A first selector, used for mode switching; wherein, when the computing engine works in the first-layer computing mode, the reordered feature map is selected as the output; when the computing engine works in the non-first-layer computing mode, the first selector selects the original input feature map as the output; A weight cache block, used to read and cache the convolution layer parameters of the DNN network; wherein the number of the weight cache blocks is determined according to the output channel expansion coefficient, and the data bit width of the weight cache block is determined according to the input channel expansion coefficient and the data precision; A computing array includes a plurality of parallel computing channels, and is used to read the output of the first selector and the convolution layer parameters to perform convolution layer calculations to obtain an output feature map; wherein the number of the computing channels is determined according to the output channel expansion coefficient.

[0014] It should be emphasized that the computing engine described in this embodiment is highly parameterized, and the expansion coefficients of the input and output channels in the computing array, the number and data bit width of the input feature cache blocks, the number and data bit width of the weight cache blocks, the computing accuracy, and the system frequency can all be parameterized. These parameters can be used to generate DNN computing engines of different sizes according to different application scenarios, such as bandwidth constraints / computing resource constraints, and are more versatile.

[0015] It should be understood that the switching between different computing modes can be performed by changing the control signal of the first selector.

[0016] It should be noted that, in the first-layer calculation mode, the original input feature map is rearranged through the input feature rearrangement module, which can convert the convolution operation into a matrix-vector multiplication, so that the data with a lower number of channels is converted into high-channel vector data, thereby improving the calculation utilization. In the non-first-layer calculation mode, the convolution direct mapping calculation strategy is adopted.

[0017] In some specific implementations, a non-first-layer computing mode is used to implement 2x2 convolution, the number of convolution output channels is 2, the number of input channels of the original input feature map is 2, and the input channel expansion coefficient and output channel expansion coefficient of the DNN computing engine are both 2; the DNN computing engine has 2 computing channels, and the 2 computing channels share the input feature map data. Figure 2In the first calculation cycle (see (a) in Figure 2), the calculation array receives the eigenvalues ​​of the original input feature map in the direction of the input channel, that is, the I0 and J0 elements in the input feature map in Figure 2. For the weight value (that is, the convolution kernel matrix parameter), different calculation channels receive the weight values ​​of different output channels. Specifically, for the first calculation channel in Figure 2 (a), it receives the weight value corresponding to the first output channel of the weight block, that is, W0 and X0, while the second calculation channel receives the weight value corresponding to the second output channel of the weight block, that is, Y0 and Z0. At the same time, the result of the first cycle is saved in the register (marked with D). In the second cycle (see (b) in Figure 2), the input feature map and the weight block value are switched, and the calculation array receives the corresponding input channel value of the second element of the convolution kernel of the original input feature map, that is, I1 and J1. The result calculated in this cycle is accumulated with the result calculated in the previous cycle and saved in the register, that is, the output static data flow strategy is adopted. In the last cycle (see (d) in Figure 2), all elements of the convolution kernel are traversed, and the calculation array outputs the final value O and P.

[0018] It should be emphasized that since the number of input channels of the first layer of the DNN network is generally 3, and the input channel expansion coefficient of the DNN computing engine is generally a multiple of 32, the effective utilization rate of computing resources is very low. In this embodiment, a first-layer computing mode suitable for the first-layer calculation of the DNN network is designed for this purpose. Referring to Figure 3, assuming that the convolution layer implements 2 times 2 convolution (step size is 1), the number of convolution output channels is 2, the number of input channels of the original input feature map is 2, the input channel expansion coefficient of the computing engine is 4, and the output channel expansion coefficient is 2. Since the input channel expansion coefficient of the DNN computing engine is greater than the number of input channels of the convolution layer, adopting the non-first-layer computing mode of the DNN computing engine will cause half of the computing units in the computing array to be invalid. In the first-layer computing mode, the convolution operation will be converted into matrix multiplication by reordering the input feature map and the convolution kernel matrix, so that the original low-channel number data is converted into high-channel vector data, as shown in the middle sub-figure of Figure 3. In the first-layer calculation mode, matrix multiplication is essentially performed. The number of columns of the rearranged input feature matrix is ​​the convolution kernel size × the number of input channels (i.e., 2×2×2=8). The DNN calculation engine input channel expansion coefficient in this example is 4, and the output channel expansion coefficient is 2. Therefore, the multiplication and addition results of I0, J0, I1, J1 and W0, X0, W1, X1 and Y0, Z0, Y1, Z1 are first calculated and stored in the register, as shown in (a) in Figure 3. After that, the multiplication and addition results of I3, J3, I4, J4 and W2, X2, W3, X3 and Y2, Z2, Y3, Z3 are calculated and added to the results in (a) in Figure 3, thereby calculating O0 and P0. The calculation process of O0-O3 and P1-P3 needs to repeat this step, except that the feature input part of the calculation array corresponds to different rows of the rearranged input feature matrix.

[0019] It should be noted that in the DNN hardware accelerator, the original input feature map is an external input, that is, non-fixed data, while the value of the convolution kernel matrix is ​​a parameter obtained by pre-training the DNN hardware accelerator, which no longer changes during operation. Therefore, the rearrangement of the convolution kernel matrix can be implemented during the DNN accelerator training process without the need to reorder the convolution kernel matrix on the hardware.

[0020] In some specific implementations, the computing engine may be implemented based on FPGA (Field Programmable Gate Array).

[0021] In some specific implementations, the input feature cache block and the weight cache block are implemented based on SRAM (Static Random-Access Memory).

[0022] In some preferred embodiments, the input feature rearrangement module includes a second selector, a third selector, a fourth selector, a data preparation buffer and a data buffer; refer to FIG4 (it should be noted that, for ease of understanding, several fourth selectors connected to the calculation array are not shown in FIG4), wherein, The second selector is used to read the original input feature map from the input feature cache block and write it into the data preparation buffer based on a ping-pong operation; and Each of the data preparation buffers stores the original input feature map All input channels are data, that is, spliced ​​into one × The matrix of , to ensure that the rate at which the input features are rearranged does not affect the rate at which the array is computed; and, The data buffer receives the spliced ​​matrix in the data preparation buffer through the third selector, and its storage capacity is × , before The data in the reading window is connected to the calculation array through a plurality of fourth selectors to provide data for matrix multiplication; and each time the data buffer completes the calculation of a pixel, all buffers in the data buffer move forward. data; whenever there is free space in the data buffer × When there is a data space of a certain size, the data in the data preparation buffer is written into the data buffer; wherein, Represents the height of the convolution kernel; Represents the convolution kernel width; represents the number of input feature map channels about the original input feature map; represents the input channel expansion coefficient; Represents the convolution step size.

[0023] In some specific implementations, two of the data preparation buffers are used to implement a ping-pong operation.

[0024] In some optional embodiments, the computing engine uses the convolution layer as the scheduling granularity, the behavior calculation granularity of the output feature map, and the original input feature map as the Behavioral data transmission granularity, pipeline processing is used between calculation and data transmission.

[0025] It should be noted that the computing engine uses the DNN layer as the scheduling granularity, and can accurately predict the execution time based on the relevant information of the DNN layer, thereby deploying a more flexible upper-level task scheduling algorithm.

[0026] In addition, the computing engine calculates the granularity of the behavior of the convolution layer (that is, the behavior of the output feature map), and the corresponding off-chip memory access granularity is also in units of behavior, so that the calculation and memory access stages can be pipelined, while improving the flexibility of bandwidth scheduling.

[0027] Figure 5 shows the calculation and memory access granularity of the computing engine. Figure 5 (a) is the original input feature map of the calculated convolution layer, which has N rows and multiple input channels. The corresponding convolution kernel size is , the step size is 1. Figure 5 (b) shows the data transmission and calculation process of the DNN computing engine. According to the bandwidth allocated to the DNN computing engine, it can be divided into two categories: 1. The data transmission time is less than the calculation time, recorded as ; 2. The calculation time is less than the transmission time, recorded as .

[0028] Before the DNN computing engine runs, the convolution kernel matrix corresponding to the convolution layer needs to be read into the weight cache block in the DNN computing engine, and the first three rows of all input channels of the original input feature map need to be read into the input feature cache block in the DNN computing engine (marked by M-1). After reading, the DNN computing engine can start to calculate the first row of the output feature map (marked by C-1). During the calculation process, the next row of the original input feature map can be read in advance (marked by M-2). Since the data of the fourth row of the original input feature map is read in advance, after the calculation of the first three rows of the original input feature map is completed, the calculation of the next row of the output feature map can be started directly. Therefore, by using the behavior calculation and memory access granularity of the feature map, the calculation and transmission stages overlap, which greatly reduces the execution time of the DNN layer.

[0029] Further, the output feature is calculated by defining Figure 1 Time of trip The time to transmit s rows of the original input feature map When equal, , the bandwidth allocated to the computing engine is the critical bandwidth ; When the computing engine is allocated bandwidth Above the critical bandwidth When the delay of the computing engine Read the convolutional layer parameters and the original input feature map during initialization The time consumed by the line and the time consumed by calculating the output feature map The sum of the time consumed by the rows is expressed as follows:

[0030] And, when the computing engine is allocated bandwidth Not higher than the critical bandwidth When the delay of the computing engine is the sum of the time to transmit all the convolutional layer parameters and all the rows of the original input feature map and the time to calculate the last row of the output feature map, and its expression is as follows:

[0031] In the formula, represents the number of output feature map channels about the output feature map; Represents the height of the original input feature map; Represents the width of the original input feature map; Indicates the data bit width.

[0032] Furthermore, the calculation of the output feature Figure 1 Time of trip The expression is:

[0033] And, the time for transmitting the original input feature map s rows is The expression is:

[0034] In the formula, represents the output channel expansion coefficient.

[0035] It should be noted that the computing engine uses pipeline processing between calculation and data transmission, so the time to calculate a row is And transfer input feature map Time of trip For convolutional layers of different sizes, the execution time is calculated by the time to calculate a row. And transfer input feature map Time of trip The larger value is determined by the party that takes longer time.

[0036] The designed DNN computing engine has a delay when calculating the convolution layer. It can be expressed as a piecewise function with the allocated bandwidth value as a variable. The delay can be calculated based on the DNN computing engine design parameters, the calculated convolution layer parameters and the currently allocated bandwidth. As shown below:

[0037] When the bandwidth allocated by the DNN computing engine is higher than the critical bandwidth When the transmission needs to wait for the calculation to be completed, the overall delay is the time required to read the convolution kernel matrix and the input feature map during initialization. The time consumed by the line (in Identification), and calculate the output feature map The time consumed by the line (in logo); When the bandwidth allocated to the DNN computing engine is lower than the critical bandwidth When , the calculation needs to wait for the transmission to end, so the overall delay is the time to transmit the entire convolutional layer weights and all rows of the input feature map (in logo), and the time to calculate the last row of the output feature map .

[0038] In some preferred embodiments, the computing array implements an output static data flow strategy based on the register and accumulation unit at the output result, without accessing the on-chip memory, and multiplexing the intermediate output results at the register level (i.e., accumulating the output of the adder tree with the previous output result), thereby reducing the number of memory accesses. It should be understood that the computing architecture has a high computing throughput, and the bandwidth occupancy rate is greatly reduced by the output static data flow strategy.

[0039] In some preferred embodiments, the computing channel is composed of a multiplication array and an adder tree; wherein the multiplication array includes a plurality of multipliers, and the adder includes a plurality of adders responsible for adding the results of a plurality of multiplications.

[0040] In some optional embodiments, the engine parameters further include a speed grade; and registers are inserted between each stage in the adder tree according to the speed grade.

[0041] It should be noted that the speed grade maps different system frequency requirements. The register insertion is based on the principle of meeting the speed grade requirements so that the system can reach the required frequency with minimum register usage.

[0042] In some optional embodiments, within the multiplication array of any of the computing channels, the first operands of all the multipliers are connected to the output of the first selector, and the second operands are connected to the convolution layer parameters of the corresponding output channels in the weight cache block.

[0043] In some specific implementations, the output channel expansion factor is 2, so the generated parallel computing architecture (i.e., computing array) has two computing channels, each of which consists of a multiplication array and an adder tree. Taking the first computing channel as an example, the first operands of all multipliers in the multiplication array are connected to the output of the selector, and the second operands are connected to the weight corresponding to the first output channel in the weight cache block. For the second computing channel, the first operands of all multipliers in the multiplication array share the output of the selector, but the second operands correspond to the weight of the second output channel in the weight cache block.

[0044] This embodiment also provides a multi-core DNN accelerator system, including several DNN computing engines described in the above embodiments.

[0045] In some specific implementations, several DNN computing engines can share a compiler.

[0046] This embodiment also provides a computer-readable storage medium, on which is stored at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor, so that the processor executes part or all of the steps of the method provided in the embodiment of the present application, including but not limited to the first-layer computing mode and the non-first-layer computing mode.

[0047] Exemplarily, the processor may be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0048] In some examples, a computer program product is provided, which can be implemented in hardware, software or a combination thereof. As a non-limiting example, the computer program product can be embodied as the storage medium, or as a software product, such as an SDK (Software Development Kit).

[0049] As a non-limiting example, a computer program product is provided, the computer program product includes a computer program or a computer executable instruction, the computer program or the computer executable instruction is stored in a computer-readable storage medium. A processor of an electronic device reads the computer program or the computer executable instruction from the computer-readable storage medium, and the processor executes the computer executable instruction, so that the electronic device performs some or all steps of the method described in the embodiment of the present application.

[0050] In some examples, a computer program is provided, comprising a computer-readable code, and when the computer-readable code is run in a computer device, a processor in the computer device executes a part or all of the steps in the method.

[0051] The same or similar reference numerals correspond to the same or similar components; The terms used to describe the positional relationship in the drawings are only used for illustrative purposes and should not be construed as limiting the present application; It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0052] In different specific implementations, the method or system described in the present application can be implemented in software, hardware or a combination thereof. In addition, the order of the steps of the method can be changed, and various elements can be added, reordered, combined, omitted, modified, etc.

[0053] Obviously, the above-mentioned embodiments of the present application are merely examples for clearly illustrating the present application, and are not intended to limit the implementation methods of the present application, and are not intended to limit the present application. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. Each discrete structure / function module or unit can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part, and the structure and function of the discrete components can be implemented as a combined structure or component. It is not necessary and impossible to enumerate all the implementation methods here. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the claims of the present application.

Claims

1. A DNN computing engine, characterized in that: include: A compiler, used to obtain engine parameters; the engine parameters include data precision, input channel expansion coefficient and output channel expansion coefficient; An input feature cache block is used to read and cache the original input feature map to be convolved in the DNN network; wherein the number of the input feature cache blocks is determined according to the input channel expansion coefficient; An input feature reordering module is used to reorder the original input feature map based on im2col, and output the reordered feature map to convert the convolution operation into a matrix-vector multiplication; A first selector, used for mode switching; wherein, when the computing engine works in the first-layer computing mode, the reordered feature map is selected as the output; when the computing engine works in the non-first-layer computing mode, the first selector selects the original input feature map as the output; A weight cache block, used to read and cache the convolution layer parameters of the DNN network; wherein the number of the weight cache blocks is determined according to the output channel expansion coefficient, and the data bit width of the weight cache block is determined according to the input channel expansion coefficient and the data precision; A computing array includes a plurality of parallel computing channels, and is used to read the output of the first selector and the convolution layer parameters to perform convolution layer calculations to obtain an output feature map; wherein the number of the computing channels is determined according to the output channel expansion coefficient.

2. A DNN computing engine according to claim 1, characterized in that: The input feature rearrangement module includes a second selector, a third selector, a fourth selector, a data preparation buffer and a data buffer; wherein, The second selector is used to read the original input feature map from the input feature cache block and write it into the data preparation buffer based on a ping-pong operation; and Each of the data preparation buffers stores the original input feature map All input channels are data, that is, spliced ​​into one × The matrix of , to ensure that the rate at which the input features are rearranged does not affect the rate at which the array is computed; and, The data buffer receives the spliced ​​matrix in the data preparation buffer through the third selector, and its storage capacity is × , before The data in the reading window is connected to the calculation array through a plurality of fourth selectors to provide data for matrix multiplication; and each time the data buffer completes the calculation of a pixel, all buffers in the data buffer move forward. data; whenever there is free space in the data buffer × When there is a data space of a certain size, the data in the data preparation buffer is written into the data buffer; wherein, Represents the height of the convolution kernel; Represents the convolution kernel width; represents the number of input feature map channels about the original input feature map; represents the input channel expansion coefficient; Represents the convolution step size.

3. A DNN computing engine according to claim 2, characterized in that: The computing engine uses the convolution layer as the scheduling granularity, the behavior calculation granularity of the output feature map, and the original input feature map as the Behavioral data transmission granularity, pipeline processing is used between calculation and data transmission.

4. A DNN computing engine according to claim 3, characterized in that: Defines the time to calculate a row of the output feature map The time to transmit s rows of the original input feature map When equal, , the bandwidth allocated to the computing engine is the critical bandwidth ; When the computing engine is allocated bandwidth Above the critical bandwidth When the delay of the computing engine Read the convolutional layer parameters and the original input feature map during initialization The time consumed by the line and the time consumed by calculating the output feature map The sum of the time consumed by the rows is expressed as follows: And, when the computing engine is allocated bandwidth Not higher than the critical bandwidth When the delay of the computing engine is the sum of the time to transmit all the convolutional layer parameters and all the rows of the original input feature map and the time to calculate the last row of the output feature map, and its expression is as follows: In the formula, represents the number of output feature map channels about the output feature map; Represents the height of the original input feature map; Represents the width of the original input feature map; Indicates the data bit width.

5. A DNN computing engine according to claim 4, characterized in that: The time for calculating a row of the output feature map The expression is: And, the time for transmitting the original input feature map s rows is The expression is: In the formula, represents the output channel expansion coefficient.

6. A DNN computing engine according to claim 1, characterized in that: The computing array implements an output static data flow strategy based on registers and accumulation units at the output results, and multiplexing of intermediate output results is performed at the register level without accessing on-chip memory.

7. A DNN computing engine according to any one of claims 1 to 6, characterized in that: The calculation channel is composed of a multiplication array and an adder tree; wherein the multiplication array includes a plurality of multipliers, and the adder includes a plurality of adders responsible for adding the results of a plurality of multiplications.

8. A DNN computing engine according to claim 7, characterized in that: The engine parameters also include a speed grade; registers are inserted between each stage in the adder tree according to the speed grade.

9. A DNN computing engine according to claim 7, characterized in that: In the multiplication array of any of the computing channels, the first operands of all the multipliers are connected to the output of the first selector, and the second operands are connected to the convolution layer parameters of the corresponding output channels in the weight cache block.

10. A multi-core DNN accelerator system, characterized in that: Comprising several DNN computing engines as described in any one of claims 1-9.

Images