Static random access memory and operation method thereof

Abstract

The invention provides a static random access memory and an operation method thereof. The static random access memory comprises a first storage unit and a second storage unit, the first word line is electrically connected with the two NMOS transistors in the first storage unit, and the second word line is electrically connected with the two NMOS transistors in the second storage unit; and the first transmission gate and the second transmission gate are respectively connected between the first storage unit and the second storage unit in series so as to control connection or disconnection between the first storage unit and the second storage unit. Therefore, in the reading and writing operation process of the static random access memory, the opening or closing of the first transmission gate and the second transmission gate can be controlled according to different use states, so that the switching between high capacity and high reliability is realized, and the single event interference resistance of the static random access memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a static random access memory and an operation method thereof. Background Art

[0002] In a high-reliability application environment, an important reason that affects the reliability of integrated circuits and memories is the reliability problem caused by particle scattering, that is, particle scattering causes latch state flipping. As shown in the figure, particle 10 generates additional charge carriers (electrons and holes) in the semiconductor substrate (P-subatrete) through ionization. These charge carriers are then collected under the action of the electric field, which may cause the logic state of the transistor or storage element to flip unexpectedly, thereby causing the storage node to flip. In order to solve the storage node flip problem caused by single-particle interference, in addition to verification and other means on the system, the circuit will use reinforced circuit design and other means, such as DICE (double interlocked storage cell) circuit or redundant latch structure circuit. Although these methods have solved the problem of single-particle interference very well, the circuit structure is relatively complex and the area occupied is also large. Summary of the invention

[0003] The object of the present invention is to provide a static random access memory and an operation method thereof, so as to improve the performance of the static random access memory in resisting single particle interference and meet the high-density configuration requirements.

[0004] To achieve the above object, the present invention provides a static random access memory, comprising:

[0005] A first storage unit and a second storage unit, each of which includes four NMOS transistors and two PMOS transistors;

[0006] A first word line and a second word line, wherein the first word line is electrically connected to the two NMOS transistors in the first memory cell, and the second word line is electrically connected to the two NMOS transistors in the second memory cell;

[0007] A first transmission gate and a second transmission gate, and the first transmission gate and the second transmission gate are respectively connected in series between the first storage unit and the second storage unit to control the conduction or disconnection between the first storage unit and the second storage unit, wherein when the first transmission gate and the second transmission gate are both turned on, the first storage unit and the second storage unit are connected, and when the first transmission gate and the second transmission gate are both closed, the first storage unit and the second storage unit are disconnected.

[0008] Optionally, in the static random access memory, the first storage unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, the first transistor and the second transistor constitute a first inverter, the third transistor and the fourth transistor constitute a second inverter, and the gate of the fifth transistor and the gate of the sixth transistor are both electrically connected to the first word line.

[0009] Optionally, in the static random access memory, the first transistor, the third transistor, the fifth transistor and the sixth transistor are all NMOS transistors, and the second transistor and the fourth transistor are both PMOS transistors.

[0010] Optionally, in the static random access memory, the second storage unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, the seventh transistor and the eighth transistor constitute a third inverter, the ninth transistor and the tenth transistor constitute a fourth inverter, and the gate of the eleventh transistor and the gate of the twelfth transistor are both electrically connected to the second word line.

[0011] Optionally, in the static random access memory, the seventh transistor, the ninth transistor, the eleventh transistor and the twelfth transistor are all NMOS transistors, and the eighth transistor and the tenth transistor are all PMOS transistors.

[0012] Optionally, in the static random access memory, the first transmission gate includes a thirteenth transistor and a fourteenth transistor connected in parallel; the second transmission gate includes a fifteenth transistor and a sixteenth transistor connected in parallel.

[0013] Optionally, in the static random access memory, the thirteenth transistor and the sixteenth transistor are both PMOS transistors, and the fourteenth transistor and the fifteenth transistor are both NMOS transistors, wherein the gate of the thirteenth transistor and the gate of the sixteenth transistor jointly receive a first control signal to control the opening or closing of the thirteenth transistor and the sixteenth transistor, and the gate of the fourteenth transistor and the gate of the fifteenth transistor jointly receive a second control signal to control the opening or closing of the fourteenth transistor and the sixteenth transistor.

[0014] Optionally, in the static random access memory, when the first transmission gate and the second transmission gate are both turned on, the source of the thirteenth transistor, the drain of the fourteenth transistor, the gate of the first transistor and the gate of the second transistor are electrically connected, the drain of the thirteenth transistor, the source of the fourteenth transistor, the gate of the seventh transistor and the gate of the eighth transistor are electrically connected, the source of the sixteenth transistor, the drain of the fifteenth transistor, the gate of the third transistor, the gate of the fourth transistor, the gate of the ninth transistor and the gate of the tenth transistor are electrically connected, and the drain of the sixteenth transistor, the source of the fifteenth transistor, the gate of the tenth transistor and the gate of the ninth transistor are electrically connected.

[0015] Optionally, in the static random access memory, the static random access memory also includes a first bit line and a second bit line, the drain of the fifth transistor and the drain of the eleventh transistor are both electrically connected to the first bit line, and the drain of the sixth transistor and the drain of the twelfth transistor are both electrically connected to the second bit line.

[0016] Based on the same inventive concept, the present invention also provides an operating method of a static random access memory, comprising:

[0017] Providing a static random access memory as described above;

[0018] Performing a read operation on the static random access memory, wherein in a first state, the first transmission gate and the second transmission gate are both closed, and different word line addressing signals are applied to the first word line and the second word line, so as to respectively perform the read operation on the first storage unit and the second storage unit, and in a second state, the first transmission gate and the second transmission gate are both opened, and the same word line addressing signal is applied to the first word line and the second word line, so that the first storage unit and the second storage unit are combined into the same storage unit and the read operation is performed simultaneously;

[0019] A write operation is performed on the static random access memory, wherein, in a first state, the first transmission gate and the second transmission gate are both closed, and different word line addressing signals are applied to the first word line and the second word line to perform the write operation on the first storage unit and the second storage unit, respectively, and in a second state, the first transmission gate and the second transmission gate are both opened, and the same word line addressing signal is applied to the first word line and the second word line to merge the first storage unit and the second storage unit into the same storage unit and perform the write operation simultaneously.

[0020] In the static random access memory provided by the present invention, the static random access memory includes a first storage unit and a second storage unit, the first storage unit and the second storage unit both include four NMOS transistors and two PMOS transistors; a first word line and a second word line, the first word line is electrically connected to the two NMOS transistors in the first storage unit, and the second word line is electrically connected to the two NMOS transistors in the second storage unit; a first transmission gate and a second transmission gate, the first transmission gate and the second transmission gate are respectively connected in series between the first storage unit and the second storage unit to control the conduction or disconnection between the first storage unit and the second storage unit, wherein the first transmission gate and the second transmission gate are both turned on, the first storage unit and the second storage unit are turned off, and the first storage unit and the second storage unit are disconnected. Since the first transmission gate and the second transmission gate are provided between the first storage unit and the second storage unit, during the operation process of reading and writing the static random access memory, the first transmission gate and the second transmission gate can be controlled to be turned on or off according to different use states, thereby controlling the conduction or disconnection between the first storage unit and the second storage unit, thereby realizing switching between high capacity and high reliability, and improving the performance of the static random access memory against single particle interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the principle of single particle interference in static random access memory;

[0022] Figure 2 It is a schematic diagram of the circuit principle of the static random access memory provided by an embodiment of the present invention;

[0023] Figure 3 It is a flowchart of an operation method of a static random access memory provided by an embodiment of the present invention;

[0024] The reference numerals are described as follows:

[0025] 10-particle; 100-first storage unit; 200-second storage unit; 300-first transmission gate; 400-second transmission gate. DETAILED DESCRIPTION

[0026] The static random access memory and its operation method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] Figure 2 FIG. 1 is a schematic diagram of the circuit principle of a static random access memory provided by an embodiment of the present invention. Figure 2As shown, the static random access memory provided by this embodiment includes a first storage unit 100 , a second storage unit 200 , a first word line WL1 , a second word line WL2 , a first transmission gate 300 , and a second transmission gate 400 .

[0028] Specifically, the first storage unit 100 is a 6T storage unit, that is, the first storage unit 100 is composed of six transistors, wherein the first storage unit 100 includes four NMOS transistors and two PMOS transistors. Further, the first storage unit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6, wherein the first transistor M1, the third transistor M3, the fifth transistor M5 and the sixth transistor M6 are all NMOS transistors, and the second transistor M2 and the fourth transistor M4 are all PMOS transistors.

[0029] In the example, in the first storage unit 100, the first transistor M1 and the second transistor M2 form a first inverter, the gate of the first transistor M1 can receive an input signal, the drain of the first transistor M1 is electrically connected to the gate of the second transistor M2, the source of the first transistor M1 is grounded, and the source of the second transistor M2 is electrically connected to the power supply voltage VDD.

[0030] The third transistor M3 and the fourth transistor M4 form a second inverter, and the input end of the second inverter receives the output signal from the first inverter. In this way, the first inverter and the second inverter work in a cross-coupling manner, that is, the gate of the first transistor M1 is connected to the output end (drain) of the second transistor M2, and the gate of the second transistor M2 is connected to the output end of the first transistor M1, so that the first inverter and the second inverter can maintain the state of the internal transistors with each other without an external power supply.

[0031] In this embodiment, the fifth transistor M5 and the sixth transistor M6 are used as switches in the first storage unit 100 to control the connection between the first storage unit 100 and the first bit line BL and the second bit line BLB, thereby realizing data reading and writing operations.

[0032] like Figure 2As shown, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are both electrically connected to the first word line WL1, for controlling the access of the first storage unit 100. The drain of the fifth transistor M5 is electrically connected to the first bit line BL, and the source of the fifth transistor M5 is electrically connected to the drain of the first transistor M1 and the gate of the second transistor M2. The drain of the sixth transistor M6 is connected to the second bit line BLB, and the source of the sixth transistor M6 is connected to the drain of the second transistor M2 and the gate of the third transistor M3.

[0033] The second storage unit 200 is a 6T (Transistor) storage unit, that is, the second storage unit 200 is composed of six transistors, wherein the second storage unit 200 includes four NMOS transistors and two PMOS transistors. Further, the second storage unit 200 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a twelfth transistor M12, wherein the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11 and the twelfth transistor M12 are all NMOS transistors, and the eighth transistor M8 and the tenth transistor M10 are all PMOS transistors.

[0034] In this embodiment, the seventh transistor M7 and the eighth transistor M8 constitute a third inverter, the gate of the seventh transistor M7 can receive an input signal, the drain of the seventh transistor M7 is electrically connected to the gate of the eighth transistor M8, and the source of the seventh transistor M7 and the source of the ninth transistor M9 are electrically connected to the power supply voltage VDD.

[0035] The ninth transistor M9 and the tenth transistor M10 form a fourth inverter, and the input end of the fourth inverter receives the output signal from the third inverter. In this way, the third inverter and the fourth inverter work in a cross-coupling manner, that is, the gate of the seventh transistor M7 is connected to the output end (drain) of the eighth transistor M8, and the gate of the eighth transistor M8 is connected to the output end of the seventh transistor M7, so that the third inverter and the fourth inverter can maintain the state of the internal transistors with each other without an external power supply.

[0036] The eleventh transistor M11 and the twelfth transistor M12 are used as switches to control the connection between the second storage unit 200 and the first bit line BL and the second bit line BLB, thereby realizing the reading and writing operations of data.

[0037] In this embodiment, the gate of the eleventh transistor M11 and the gate of the twelfth transistor M12 are both electrically connected to the second word line WL2, for controlling access to the second storage unit 200. The drain of the eleventh transistor M11 is electrically connected to the first bit line BL, and the source of the eleventh transistor M11 is electrically connected to the drain of the seventh transistor M7 and the gate of the second transistor M2. The drain of the twelfth transistor M12 is connected to the second bit line BLB, and the source of the twelfth transistor M12 is connected to the drain of the eighth transistor M8 and the gate of the ninth transistor M9.

[0038] like Figure 2 As shown, the first transmission gate 300 and the second transmission gate 400 are respectively connected in series between the first storage unit 100 and the second storage unit 200, that is, the first transmission gate 300 and the second transmission gate 400 are arranged between the storage node of the first storage unit 100 and the storage unit of the second storage unit 200 to control the conduction or disconnection between the first storage unit 100 and the second storage unit 200. Wherein, if the first transmission gate 300 and the second transmission gate 400 are both turned on, the first storage unit 100 and the second storage unit 200 are connected, and if the first transmission gate 300 and the second transmission gate 400 are both turned off, the first storage unit 100 and the second storage unit 200 are disconnected. The first transmission gate 300 and the second transmission gate 400 can be connected in parallel.

[0039] Specifically, Figure 2 As shown, the first transmission gate 300 includes a thirteenth transistor M13 and a fourteenth transistor M14 connected in parallel, the thirteenth transistor M13 is a PMOS transistor, and the fourteenth transistor M14 is an NMOS transistor. The source of the thirteenth transistor M13 is electrically connected to the drain of the fourteenth transistor M14, and the drain of the thirteenth transistor M13 is electrically connected to the source of the fourteenth transistor M14.

[0040] Continue to refer Figure 2 As shown, the connection point where the source of the thirteenth transistor M13 and the drain of the fourteenth transistor M14 are electrically connected is electrically connected to the gate of the first transistor M1 and the gate of the second transistor M2. The connection point where the drain of the thirteenth transistor M13 and the source of the fourteenth transistor M14 are electrically connected is electrically connected to the gate of the eighth transistor M8 and the gate of the seventh transistor M7.

[0041] In this embodiment, the second transmission gate 400 includes a fifteenth transistor M15 and a sixteenth transistor M16 connected in parallel, the fifteenth transistor M15 is an NMOS transistor, and the sixteenth transistor M16 is a PMOS transistor. The source of the fifteenth transistor M15 is electrically connected to the drain of the sixteenth transistor M16, and the drain of the fifteenth transistor M15 is electrically connected to the source of the sixteenth transistor M16. The connection point where the source of the fifteenth transistor M15 is electrically connected to the drain of the sixteenth transistor M16 is electrically connected to the gate of the third transistor M3 and the gate of the fourth transistor M4, and the connection point where the drain of the fifteenth transistor M15 is electrically connected to the source of the sixteenth transistor M16 is electrically connected to the gate of the tenth transistor M10 and the gate of the ninth transistor M9.

[0042] In this embodiment, the gate of the thirteenth transistor M13 and the gate of the sixteenth transistor M16 jointly receive the first control signal CTRL to control the opening or opening of the thirteenth transistor M13 and the sixteenth transistor M16, and the gate of the fourteenth transistor M14 and the gate of the fifteenth transistor M15 jointly receive the second control signal CTRLB to control the opening or opening of the fourteenth transistor M14 and the sixteenth transistor M16.

[0043] Specifically, when the first transmission gate 300 and the second transmission gate 400 are both turned on, the highest address bit or the lowest address bit is invalid, the source of the thirteenth transistor M13, the drain of the fourteenth transistor M14, the gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected, the drain of the thirteenth transistor M13, the source of the fourteenth transistor, the gate of the seventh transistor M7 and the gate of the eighth transistor M8 are electrically connected, the source of the sixteenth transistor M16, the drain of the fifteenth transistor M15, the gate of the third transistor M3, the gate of the fourth transistor M4, the gate of the ninth transistor M9 and the gate of the tenth transistor M10 are electrically connected, and the drain of the sixteenth transistor M16, the source of the fifteenth transistor M15, the gate of the tenth transistor M10 and the gate of the ninth transistor M9 are electrically connected.

[0044] The first transmission gate 300 and the second transmission gate 400 are turned on, which means that the thirteenth transistor M13 and the sixteenth transistor M16 are both in the on state, and the fourteenth transistor M14 and the fifteenth transistor M15 are both in the on state. In this way, in the case of high reliability application, the first word line WL1 and the second word line WL2 are controlled by the same word line addressing signal, and the first word line WL1 and the second word line WL2 are combined into one first storage unit 100 and the second storage unit 200 are used as a whole, and the storage capacity thereof is halved, and the internal storage nodes of the first storage unit 100 and the second storage unit 200 are interlocked through the first transmission gate 300 and the second transmission gate 400, so as to play a role in resisting single particle interference.

[0045] When the first transmission gate 300 and the second transmission gate 400 are both closed, the first storage unit 100 is disconnected from the second storage unit 200, the lowest address bit or the highest address bit is valid, and the first storage unit 100 and the second storage unit 200 can be used as two separate storage units, thereby achieving high-density application and high-capacity storage. In other words, since the first transmission gate 300 and the second transmission gate 400 are provided between the first storage unit 100 and the second storage unit 200, during the read and write operation of the static random access memory, the first transmission gate 300 and the second transmission gate 400 can be controlled to be turned on or off according to different use states (high-density application state or high-reliability application state), thereby achieving switching between high capacity and high reliability.

[0046] Among them, the first control signal CTRL and the second control signal CTRLB can be generated after logical operation according to the application type and the specified address bit, corresponding to the first word line WL1 addressing signal of the first word line WL1 and the second word line WL2 addressing signal of the second word line WL2, so that in high-density applications, the first control signal CTRL and the second control signal CTRLB are used to close the first transmission gate 300 and the second transmission gate 400, and the specified address bit is enabled, so that the first word line WL1 and the second word line WL2 can be controlled respectively, so as to realize the use of the 16T (i.e., including sixteen transistors) storage unit (the first storage unit 100 and the second storage unit 200) as two separate 6T (i.e., including six transistors) storage units.

[0047] The fact that the first transmission gate 300 and the second transmission gate 400 are both closed means that the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 are all in the off state.

[0048] In addition, the overall circuit structure of the static random access memory provided by this embodiment is relatively simple and easy to implement, thereby saving the area occupied by the static random access memory.

[0049] Figure 3 FIG. 1 is a flow chart of an operation method of a static random access memory provided by an embodiment of the present invention. Figure 3 As shown, this embodiment also provides an operation method of a static random access memory, including:

[0050] Step S1: providing a static random access memory;

[0051] Step S2: performing a read operation on the static random access memory, wherein, in a first state, the first transmission gate and the second transmission gate are both closed, and different word line addressing signals are applied to the first word line and the second word line to perform the read operation on the first storage unit and the second storage unit, respectively, and in a second state, the first transmission gate and the second transmission gate are both opened, and the same word line addressing signal is applied to the first word line and the second word line to merge the first storage unit and the second storage unit into the same storage unit and perform the read operation simultaneously.

[0052] Step S3: performing a write operation on the static random access memory, wherein, in a first state, the first transmission gate and the second transmission gate are both closed, and different word line addressing signals are applied to the first word line and the second word line to perform the write operation on the first storage unit and the second storage unit, respectively, and in a second state, the first transmission gate and the second transmission gate are both opened, and the same word line addressing signal is applied to the first word line and the second word line to merge the first storage unit and the second storage unit into the same storage unit (merged into a whole) and perform the write operation simultaneously.

[0053] In this embodiment, the first state refers to the static random access memory needs to meet the application requirements of high density (or high capacity). The second state refers to the static random access memory needs to meet the application requirements of high reliability, thereby playing a role in resisting single particle interference, thereby improving the performance of the static random access memory in resisting single particle interference.

[0054] In summary, in the static random access memory and the operation method thereof provided by the present invention, the static random access memory includes a first storage unit and a second storage unit, the first storage unit and the second storage unit both include four NMOS transistors and two PMOS transistors; a first word line and a second word line, the first word line is electrically connected to the two NMOS transistors in the first storage unit, and the second word line is electrically connected to the two NMOS transistors in the second storage unit; a first transmission gate and a second transmission gate, the first transmission gate and the second transmission gate are connected in parallel, and the first transmission gate and the second transmission gate are respectively connected in series between the first storage unit and the second storage unit to control the conduction or disconnection between the first storage unit and the second storage unit, wherein the first transmission gate and the second transmission gate are turned on to conduct the first storage unit and the second storage unit, and the first transmission gate and the second transmission gate are turned off to disconnect the first storage unit and the second storage unit. Since the first transmission gate and the second transmission gate are provided between the first storage unit and the second storage unit, during the read and write operation of the static random access memory, the first transmission gate and the second transmission gate can be controlled to be turned on or off according to different usage states, thereby realizing switching between high capacity and high reliability.

[0055] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A static random access memory, characterized in that: include: A first storage unit and a second storage unit, each of which includes four NMOS transistors and two PMOS transistors; A first word line and a second word line, wherein the first word line is electrically connected to the two NMOS transistors in the first memory cell, and the second word line is electrically connected to the two NMOS transistors in the second memory cell; A first transmission gate and a second transmission gate, wherein the first transmission gate and the second transmission gate are respectively connected in series between the first storage unit and the second storage unit to control conduction or disconnection between the first storage unit and the second storage unit, wherein when the first transmission gate and the second transmission gate are both turned on, the first storage unit and the second storage unit are connected, and when the first transmission gate and the second transmission gate are both turned off, the first storage unit and the second storage unit are disconnected.

2. The static random access memory according to claim 1, wherein: The first storage unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, the first transistor and the second transistor constitute a first inverter, the third transistor and the fourth transistor constitute a second inverter, and the gate of the fifth transistor and the gate of the sixth transistor are both electrically connected to the first word line.

3. The static random access memory according to claim 2, wherein: The first transistor, the third transistor, the fifth transistor and the sixth transistor are all NMOS transistors, and the second transistor and the fourth transistor are all PMOS transistors.

4. The static random access memory according to claim 2, wherein: The second storage unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, the seventh transistor and the eighth transistor constitute a third inverter, the ninth transistor and the tenth transistor constitute a fourth inverter, and the gate of the eleventh transistor and the gate of the twelfth transistor are both electrically connected to the second word line.

5. The static random access memory according to claim 4, wherein: The seventh transistor, the ninth transistor, the eleventh transistor and the twelfth transistor are all NMOS transistors, and the eighth transistor and the tenth transistor are all PMOS transistors.

6. The static random access memory according to claim 4, wherein: The first transmission gate includes a thirteenth transistor and a fourteenth transistor connected in parallel; the second transmission gate includes a fifteenth transistor and a sixteenth transistor connected in parallel.

7. The static random access memory according to claim 6, wherein: The thirteenth transistor and the sixteenth transistor are both PMOS transistors, and the fourteenth transistor and the fifteenth transistor are both NMOS transistors, wherein the gate of the thirteenth transistor and the gate of the sixteenth transistor jointly receive a first control signal to control the opening or closing of the thirteenth transistor and the sixteenth transistor, and the gate of the fourteenth transistor and the gate of the fifteenth transistor jointly receive a second control signal to control the opening or closing of the fourteenth transistor and the sixteenth transistor.

8. The static random access memory according to claim 5, wherein: When the first transmission gate and the second transmission gate are both turned on, the source of the thirteenth transistor, the drain of the fourteenth transistor, the gate of the first transistor and the gate of the second transistor are electrically connected, the drain of the thirteenth transistor, the source of the fourteenth transistor, the gate of the seventh transistor and the gate of the eighth transistor are electrically connected, the source of the sixteenth transistor, the drain of the fifteenth transistor, the gate of the third transistor, the gate of the fourth transistor, the gate of the ninth transistor and the gate of the tenth transistor are electrically connected, and the drain of the sixteenth transistor, the source of the fifteenth transistor, the gate of the tenth transistor and the gate of the ninth transistor are electrically connected.

9. The static random access memory according to claim 1, wherein: The static random access memory also includes a first bit line and a second bit line, the drain of the fifth transistor and the drain of the eleventh transistor are both electrically connected to the first bit line, and the drain of the sixth transistor and the drain of the twelfth transistor are both electrically connected to the second bit line.

10. A method for operating a static random access memory, characterized in that: include: Provide a static random access memory as claimed in any one of claims 1 to 9; Performing a read operation on the static random access memory, wherein in a first state, the first transmission gate and the second transmission gate are both closed, and different word line addressing signals are applied to the first word line and the second word line, so as to respectively perform the read operation on the first storage unit and the second storage unit, and in a second state, the first transmission gate and the second transmission gate are both opened, and the same word line addressing signal is applied to the first word line and the second word line, so that the first storage unit and the second storage unit are combined into the same storage unit and the read operation is performed simultaneously; A write operation is performed on the static random access memory, wherein, in a first state, the first transmission gate and the second transmission gate are both closed, and different word line addressing signals are applied to the first word line and the second word line to perform the write operation on the first storage unit and the second storage unit, respectively, and in a second state, the first transmission gate and the second transmission gate are both opened, and the same word line addressing signal is applied to the first word line and the second word line to merge the first storage unit and the second storage unit into the same storage unit and perform the write operation simultaneously.

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