Strong PUF system based on SRAM

Abstract

The invention provides a strong PUF (physical unclonable function) system based on an SRAM (static random access memory), and belongs to the technical field of digital integrated circuits and security anti-counterfeiting, the system comprises a plurality of SRAM PUF units which are connected in parallel, each SRAM PUF unit comprises eight MOS (metal oxide semiconductor) tubes, the drain electrode of the first MOS tube, the drain electrode of the second MOS tube, the grid electrode of the third MOS tube, the grid electrode of the fourth MOS tube and the drain electrode of the fifth MOS tube are connected at one point, and the drain electrode of the first MOS tube, the drain electrode of the second MOS tube, the grid electrode of the third MOS tube and the drain electrode of the fifth MOS tube are connected at the other point. The drain electrode of the third MOS tube, the drain electrode of the fourth MOS tube, the grid electrode of the first MOS tube, the grid electrode of the second MOS tube and the drain electrode of the sixth MOS tube are connected to one point, the source electrode of the first MOS tube, the source electrode of the third MOS tube and the drain electrode of the seventh MOS tube are connected to one point, the source electrode of the second MOS tube, the source electrode of the fourth MOS tube and the drain electrode of the eighth MOS tube are connected to one point, the source electrode of the seventh MOS tube is connected with VDD, and the source electrode of the eighth MOS tube is connected with GND.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuits and security anti-counterfeiting, and in particular to a strong PUF method based on SRAM. Background Art

[0002] In recent years, the Internet of Things (IoT) has developed very rapidly. The low power consumption, wide coverage, low cost and multi-connection characteristics of IoT devices often become the weak links of IoT systems. Attackers can obtain key data and even digital keys stored in the chip through physical detection, invasive and semi-invasive attack techniques, machine learning, etc., which will lead to network congestion, server paralysis and other problems, and may even cause greater economic losses. Therefore, the security of the Internet of Things has become one of the key issues restricting its rapid development. The Physical Unclonable Function (PUF) mainly uses the inevitable random differences in the chip during the manufacturing process to generate a unique "chip fingerprint" with natural anti-tampering and anti-cloning capabilities. Therefore, PUF can provide a low-cost and high-security authentication and key generation method for the Internet of Things, which can effectively solve the security problems of the Internet of Things.

[0003] According to the number of challenge response pairs, PUF can be divided into strong PUF and weak PUF. Weak PUF can only generate a small number of challenge response pairs (CRPs) for device key generation. Strong PUF can generate a large number of challenge response pairs and is widely used in lightweight authentication. SRAM PUF is a weak PUF based on the Static Random Access Memory (SRAM) structure.

[0004] However, since SRAM PUF is a weak PUF structure, it is significantly limited in scenarios where a large number of stimulus-response pairs need to be generated. Compared with other types of PUF structures, the response magnitude of SRAM PUF is lower, and each SRAM PUF can only generate a 1-bit response. In many applications, the system usually requires multi-bit responses to support more complex security functions or stronger security. In order to meet this demand, it is necessary to build multiple SRAM PUF structures and connect them in series to form a larger PUF array. However, this method not only increases the cost of the system, but also increases power consumption, limiting the practicality of SRAM PUF in large-scale applications. Therefore, there are technical problems in the prior art of high cost, high power consumption and low practicality in generating a large number of stimulus responses. Summary of the invention

[0005] In view of this, it is necessary to provide a strong PUF system based on SRAM to solve the technical problems of high cost, high power consumption and low practicality in generating a large number of stimulus responses in the prior art.

[0006] In order to solve the above technical problems, on the one hand, the present invention provides a strong PUF system based on SRAM, comprising: Multiple SRAM PUF cells connected in parallel with each other; Among them, the SRAM PUF unit includes: eight MOS tubes; The drain of the first MOS tube, the drain of the second MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube and the drain of the fifth MOS tube are connected to one point; The drain of the third MOS tube, the drain of the fourth MOS tube, the gate of the first MOS tube, the gate of the second MOS tube and the drain of the sixth MOS tube are connected to one point; The source of the first MOS tube, the source of the third MOS tube and the drain of the seventh MOS tube are connected to one point; The source of the second MOS tube, the source of the fourth MOS tube and the drain of the eighth MOS tube are connected to one point; The source of the seventh MOS tube is connected to VDD; The source of the eighth MOS tube is connected to GND.

[0007] In a possible implementation, the multiple SRAM PUF units connected in parallel include: The source of the fifth MOS transistor of the first SRAM PUF unit is connected to the source of the fifth MOS transistor of the second SRAM PUF unit.

[0008] In a possible implementation manner, the multiple SRAM PUF units connected in parallel to each other further include: The source of the sixth MOS transistor of the first SRAM PEF unit is connected to the source of the sixth MOS transistor of the second SRAM PUF unit.

[0009] In a possible implementation, the system further includes: a first control signal unit, wherein the first control signal unit is connected to the gate of the seventh MOS tube.

[0010] In a possible implementation, the system further includes: a second control signal unit, wherein the second control signal unit is connected to the drain of the eighth MOS tube.

[0011] In one possible implementation, The second control signal unit is connected to the gate of the fifth MOS tube.

[0012] In one possible implementation, The second control signal unit is connected to the gate of the sixth MOS tube.

[0013] In a possible implementation, the system further includes: a first output signal unit, wherein the first output signal unit is connected to the source of the fifth MOS tube.

[0014] In a possible implementation, the system further includes: a second output signal unit, wherein the second output signal unit is connected to the source of the sixth MOS tube.

[0015] In a possible implementation manner, the sixth MOS transistor is an NMOS transistor.

[0016] The beneficial effects of the present invention are as follows: the SRAM-based strong PUF system provided by the present invention comprises: a plurality of SRAM PUF units connected in parallel to each other, the purpose of which is to use a plurality of SRAM storage units in parallel to form a strong PUF structure, the parallel structure makes full use of the differences between the SRAM storage units, and enhances the number of PUF stimulus responses; wherein the SRAM PUF unit comprises: eight MOS tubes; the drain of the first MOS tube, the drain of the second MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube and the drain of the fifth MOS tube are connected to one point; the drain of the third MOS tube, the drain of the fourth MOS tube, the gate of the first MOS tube, the gate of the second MOS tube and the drain of the sixth MOS tube are connected to one point; the source of the first MOS tube, the source of the third MOS tube and the drain of the seventh MOS tube are connected to one point; the source of the second MOS tube, the source of the fourth MOS tube and the drain of the eighth MOS tube are connected to one point; the source of the seventh MOS tube is connected to VDD; the source of the eighth MOS tube is connected to GND. The fifth MOS tube and the sixth MOS tube serve as switches for each SRAM cell, and are used to select whether the cell is connected in parallel with other SRAM cells. This select-and-use method effectively reduces the power consumption of the entire circuit and improves the practicality of the system structure, because the SRAM cell is connected to the parallel structure only when needed, otherwise the cell is in a dormant state. In addition, the seventh MOS tube and the eighth MOS tube are not only used to reduce the power consumption of the PUF, but also to input an enable level to the PUF to generate a response. When a certain SRAM cell needs to be stimulated, the enable level will be input into the corresponding SRAM structure, triggering its response generation process. When a certain SRAM cell is not needed, the enable level will not be input, which ensures that the unselected SRAM cell does not waste energy. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of an embodiment of a SRAM-based strong PUF system provided by the present invention; Figure 2 A diagram showing the main structure of an SRAM PUF transistor of an embodiment of a SRAM-based strong PUF system provided by the present invention; Figure 3 A basic logical structure diagram of an SRAM PUF of an embodiment of a SRAM-based strong PUF system provided by the present invention; Figure 4 A diagram of a four-level parallel strong physical unclonable function structure of an SRAM structure of an embodiment of an SRAM-based strong PUF system provided by the present invention. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0020] In the description of the embodiments of the present application, unless otherwise specified, “plurality” means two or more than two.

[0021] The terms "including" and "having" and any variations thereof in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or equipment comprising a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules not clearly listed or inherent to these processes, methods, products or equipment.

[0022] The naming or numbering of the steps in the embodiments of the present invention does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.

[0023] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] The present invention provides a strong PUF system based on SRAM, which is described below respectively.

[0025] Figure 1 A schematic diagram of the structure of an embodiment of a strong PUF system based on SRAM provided by the present invention, Figure 2 The main structure diagram of the SRAM PUF transistor of an embodiment of the SRAM-based strong PUF system provided by the present invention and Figure 3 The basic logical structure diagram of an SRAM PUF of an embodiment of the SRAM-based strong PUF system provided by the present invention includes: Multiple SRAM PUF cells connected in parallel with each other; Among them, the SRAM PUF unit includes: eight MOS (Metal Oxide Semiconductor Field Effect Transistor); The drain of the first MOS transistor 101, the drain of the second MOS transistor 102, the gate of the third MOS transistor 103, the gate of the fourth MOS transistor 104 and the drain of the fifth MOS transistor 105 are connected to one point; The drain of the third MOS transistor 103, the drain of the fourth MOS transistor 104, the gate of the first MOS transistor 101, the gate of the second MOS transistor 102 and the drain of the sixth MOS transistor 106 are connected to one point; The source of the first MOS transistor 101, the source of the third MOS transistor 103 and the drain of the seventh MOS transistor 107 are connected to one point; The source of the second MOS transistor 102, the source of the fourth MOS transistor 104 and the drain of the eighth MOS transistor 108 are connected to one point; The source of the seventh MOS tube 107 is connected to VDD (drain power supply voltage); The source of the eighth MOS tube 108 is connected to GND (ground).

[0026] It can be understood that the SRAM-based strong PUF system provided by the present invention utilizes the differences between multiple SRAM storage units to enhance the number of PUF stimulus responses.

[0027] Compared with the traditional SRAM PUF structure, multiple SRAM PUF basic units are connected in parallel on its basis, as shown in the following figure: Figure 1 As shown in the figure. The structure consists of n SRAM PUF basic units in parallel. The number of units n can be freely selected according to actual needs. When each basic unit is added, the number of stimulus response pairs will show an exponential growth characteristic. This means that as the number of basic units increases, more unique response combinations can be obtained, thereby upgrading the traditional weak SRAM PUF structure to a strong PUF structure. When multiple SRAM PUF basic units are connected in parallel, the switch state of each basic unit is combined into our stimulus signal (n'bS1, S2, S3...Sn), but the stimulus signal (n'bS1, S2, S3...Sn) cannot be all 0. All 0 means that there is no SRAM PUF unit connected in the parallel structure, and no stimulus can be generated. We determine the final stable state by comparing the stable state and output drive capability of various units in the parallel structure. If the stable states between units are consistent, the final state is their common output; if the stable states are different, the state with stronger output drive capability is used as the final state. For example, assuming that there are two SRAM PUF units in the initial state, excluding the case where all are 0, 2^2-1=3 different stimulus response pairs can be generated. If the stable states of the two SRAM PUF units are both (R=1, R=0), the final stable state is (R=1, R=0); if the stable states of the two SRAM PUF units are both (R=0, R=1), the final stable state is (R=0, R=1). If the stable states of the two SRAM PUF units are different, one is (R=1, R=0) and the other is (R=0, R=1), the final stable state is determined by their output drive capabilities. If the output drive capability of the stable state (R=1, R=0) is stronger, the final stable state will be (R=1, R=0); conversely, if the output drive capability of the stable state (R=0, R=1) is stronger, the final stable state will be (R=0, R=1). When the number of SRAM PUF units is increased to three, 2^3-1=7 different stimulus-response pairs can be generated, excluding the case where all are 0. If the stable states of the three SRAM PUF units are the same, the final state is their common output; if the stable states are different, the state with stronger output driving capability is used as the final state. Therefore, by only adding a small number of SRAM PUF units, the number of stimulus-response pairs can be significantly increased, making SRAM PUF more universal in various practical applications.

[0028] Each SRAM unit includes eight MOS transistors, including three PMOS transistors, namely: a first MOS transistor 101, a third MOS transistor 103 and a seventh MOS transistor 107; and five NMOS transistors, namely: a second MOS transistor 102, a fourth MOS transistor 104, a fifth MOS transistor 105, a sixth MOS transistor 106 and an eighth MOS transistor 108.

[0029] It can be further understood that PUF can be divided into strong PUF and weak PUF according to the number of challenge response pairs. Weak PUF can only generate a small number of challenge response pairs (CRPs) for device key generation. Strong PUF can generate a large number of challenge response pairs and is widely used in lightweight authentication. SRAM PUF is a weak PUF based on the Static Random Access Memory (SRAM) structure. Its transistor main structure is as follows: Figure 2 shown.

[0030] It can be further understood that due to random variations, (Vth, P1) may be less than (Vth, P2). Therefore, during the power-on (Vdd rising) phase, P1 will start to conduct earlier than P2, causing R to be logically in a high state and preventing P2 from conducting. Therefore, the power-on state of the unit is R=1. If the mismatch between (Vth, P1) and (Vth, P2) is larger, the power-on priority of the unit will be stronger, making the probability of another state after power-on smaller. Specifically, Figure 3 shown.

[0031] In some embodiments of the present invention, the plurality of SRAM PUF units connected in parallel to each other include: The source of the fifth MOS transistor 105 of the first SRAM PUF unit is connected to the source of the fifth MOS transistor 105 of the second SRAM PUF unit.

[0032] It can be understood that the SRAM-based strong PUF system provided by the present invention is composed of n SRAM PUF basic units in parallel. Preferably, when n is 2, the source of the fifth MOS tube 105 of the first SRAM PUF unit is connected to the source of the fifth MOS tube 105 of the second SRAM PUF unit, and the fifth MOS tube 105 serves as a switch for each SRAM unit to select whether the unit is connected in parallel with other SRAM units. When Sn is connected to a high level, the source and drain of the fifth MOS tube 105 of the first SRAM PUF unit and the fifth MOS tube 105 of the second SRAM PUF unit are connected, so that SRAM-n is connected to the parallel structure. When SRAM-n is not selected to be connected to the parallel structure, the fifth MOS tube 105 of the first SRAM PUF unit and the fifth MOS tube 105 of the second SRAM PUF unit are in a non-conducting state. SRAM-n is in an independent working state. This on-demand method effectively reduces the power consumption of the entire circuit.

[0033] In some embodiments of the present invention, the plurality of SRAM PUF units connected in parallel to each other further include: The source of the sixth MOS transistor 106 of the first SRAM PEF unit is connected to the source of the sixth MOS transistor 106 of the second SRAM PUF unit.

[0034] It can be understood that the SRAM-based strong PUF system provided by the present invention is composed of n SRAM PUF basic units in parallel. Preferably, when n is 2, the source of the sixth MOS tube 106 of the first SRAM PUF unit is connected to the source of the sixth MOS tube 106 of the second SRAM PUF unit, and the sixth MOS tube 106 serves as a switch for each SRAM unit to select whether the unit is connected in parallel with other SRAM units. When Sn is connected to a high level, the source and drain of the sixth MOS tube 106 of the first SRAM PUF unit and the sixth MOS tube 106 of the second SRAM PUF unit are connected, so that SRAM-n is connected to the parallel structure. When SRAM-n is not selected to be connected to the parallel structure, the sixth MOS tube 106 of the first SRAM PUF unit and the sixth MOS tube 106 of the second SRAM PUF unit are in a non-conducting state. SRAM-n is in an independent working state. This on-demand method effectively reduces the power consumption of the entire circuit.

[0035] In some embodiments of the present invention, the system further includes: a first control signal unit, wherein the first control signal unit is connected to the gate of the seventh MOS transistor 107 .

[0036] It can be understood that the first control signal unit generates a control signal Sn, and the gate of the seventh MOS tube 107 is connected to the first control unit. The seventh MOS tube 107 is not only used to reduce the power consumption of the PUF, but also used to input an enable level to the PUF to generate a response. When a certain SRAM cell needs to be stimulated, the enable level will be input into the corresponding SRAM structure to trigger its response generation process. When a certain SRAM cell is not needed, the enable level will not be input, which ensures that the unselected SRAM cell does not waste energy.

[0037] In some embodiments of the present invention, the system further includes: a second control signal unit, and the second control signal unit is connected to the drain of the eighth MOS transistor 108 .

[0038] It can be understood that the second control signal unit generates a control signal Sn, and the drain of the eighth MOS tube 108 is connected to the second control signal unit. The eighth MOS tube 108 is not only used to reduce the power consumption of the PUF, but also used to input an enable level to the PUF to generate a response. When a certain SRAM cell needs to be stimulated, the enable level will be input into the corresponding SRAM structure to trigger its response generation process. When a certain SRAM cell is not needed, the enable level will not be input, which ensures that the unselected SRAM cell does not waste energy.

[0039] In some embodiments of the present invention, the second control signal unit is connected to the gate of the fifth MOS transistor 105 .

[0040] It is understandable that the fifth MOS tube 105 also assumes the function of discharging the MOS tube. After completing a set of stimulus inputs and obtaining a response, the MOS tube needs to be restored to its initial state for the next set of stimulus inputs. Therefore, these switching devices not only control the connection state of the SRAM unit, but also ensure the normal operation of the PUF and the smooth progress of the response generation process.

[0041] In some embodiments of the present invention, the second control signal unit is connected to the gate of the sixth MOS transistor 106 .

[0042] It is understandable that the sixth MOS tube 106 also assumes the function of discharging the MOS tube. After completing a set of stimulus inputs and obtaining a response, the MOS tube needs to be restored to its initial state for the next set of stimulus inputs. Therefore, these switching devices not only control the connection state of the SRAM unit, but also ensure the normal operation of the PUF and the smooth progress of the response generation process.

[0043] In some embodiments of the present invention, the system further includes: a first output signal unit, wherein the first output signal unit is connected to the source of the fifth MOS transistor 105 .

[0044] It can be understood that the first output signal unit generates the control signal R, and the first output signal unit is connected to the source of the fifth MOS transistor 105 .

[0045] In some embodiments of the present invention, the system further includes: a second output signal unit, and the second output signal unit is connected to the source of the sixth MOS transistor 106 .

[0046] It can be understood that the first output signal unit generates the control signal Rin, and the first output signal unit is connected to the source of the sixth MOS transistor 106 .

[0047] Figure 4 A four-level parallel strong physical unclonable function structure diagram of an SRAM structure of an embodiment of a strong PUF system based on SRAM provided by the present invention includes: The invention is explained by a specific embodiment. Figure 4 As shown, Figure 4It is a four-stage parallel Strong SRAM PUF structure. Compared with the traditional single SRAM PUF structure, the present invention connects three SRAM PUF basic units in parallel on its basis. When multiple SRAM PUF basic units are connected in parallel, the switch state of each basic unit is combined into our excitation signal (n'bS1, S2, S3...Sn). The present invention determines the final stable state by comparing the stable state and output drive capability of various units in the parallel structure. If the stable states between the units are consistent, the final state is their common output; if the stable states are different, the state with stronger output drive capability is used as the final state. Assume that there are 4 SRAM PUF units, and they are connected in parallel as follows: SRAM_1, SRAM_2, SRAM_3 and SRAM_4. When the input excitation is (4'b0011), SRAM_3 and SRAM_4 are connected in parallel, which means that their outputs are connected together. After power-on for a period of time, it is assumed that SRAM_3 enters a stable state (R=0, R=1), and SRAM_4 also enters a stable state (R=0, R=1). This means that the output value of SRAM_3 is 0, and the output value after inversion is 1, while the output values ​​of SRAM_4 are also 0 and 1 respectively. Therefore, according to the setting of this embodiment, the final stable state is (R=0, R=1). If the stable states of SRAM_3 and SRAM_4 are (R=1, R=0) respectively, then the final stable state will be (R=1, R=0). When the stable states of SRAM_3 and SRAM_4 are different, the final stable state is determined according to their output drive capabilities. If the output drive capability of SRAM_3 is stronger, then the final stable state will be (R=0, R=1); conversely, if the output drive capability of SRAM_4 is stronger, then the final stable state will be (R=1, R=0). In order to prevent the response generated by the previous set of stimuli from affecting the process of responding to the next set of stimuli, before we input the next set of stimuli, we need to set (S1, S2, S3, S4) to 4'b0000 and turn off each basic unit to return the level maintained in the MOS tube to zero.

[0048] When more SRAM structures are connected in parallel, if the final stable state of each SRAM is the same, then the final state will be the same as the stable state of each SRAM. This shows that the final stable state in the parallel structure is jointly determined by the stable states of each SRAM unit.

[0049] However, if the final stable state of the SRAM in the parallel structure is different, this embodiment needs to comprehensively consider the driving capabilities of each SRAM unit to determine the final stable state. Specifically, this embodiment determines the final stable state by comparing the sum of the driving capabilities of all SRAM units with a final stable state of (R=0, R=1) with the sum of the driving capabilities of all SRAM units with a final stable state of (R=1, R=0). Such a comparison can help determine which final state has a stronger driving capability in the entire parallel structure. The final stable state will be determined by the state with a stronger driving capability, and such a comprehensive consideration can improve the stability and reliability of the system when facing different SRAM unit stable states. When more basic units are connected in parallel, the excitation response of the PUF increases exponentially, which makes the traditional weak PUF structure evolve into a strong PUF. By connecting more basic units in parallel, the uncertainty and complexity of the excitation signal increase. The number of combinations of the switching states of each basic unit increases exponentially, effectively increasing the entropy value of the PUF output response and improving the unpredictability of the PUF.

[0050] The advantage of this strong PUF structure is that it increases the security of the system. Specifically, by connecting multiple basic units in parallel, each basic unit has its own unique initial state and response mode. Strong PUF is able to generate more output patterns, thereby increasing the reliability and complexity of PUF. The exponentially growing response space is essential to resist various attacks and create an unclonable "silicon fingerprint".

[0051] Through the above technology, the present invention achieves the goal of transforming weak PUF into strong PUF, improving the reliability of SRAM PUF circuit and improving the ability to resist machine learning. Compared with the traditional SRAM PUF circuit, the parallel SRAM PUF circuit increases the number of stimulus response pairs. Compared with the traditional SRAM PUF circuit, the number of stimulus response pairs is enriched, the reliability is improved, and the key information can be better protected.

[0052] In some embodiments of the present invention, the sixth MOS tube is an NMOS tube. It can be understood that a PMOS tube is a MOS tube with an N-type substrate and a P-channel, which transports current by the flow of holes; an NMOS tube is a MOS tube with a low doping concentration, on which two N+ regions with high doping concentration are made (there are a large number of electron sources in the N+ region that provide free electrons for the flow of current), and two electrodes are drawn out with metal aluminum, which are respectively used as the drain D and the source S. Then a very thin silicon dioxide insulating layer is covered on the surface of the semiconductor, and an aluminum electrode is installed on the insulating layer between the drain and the source as the gate G. An electrode B is also drawn out on the substrate, which constitutes an N-channel enhancement MOS tube.

[0053] The SRAM-based strong PUF system provided by the present invention comprises: a plurality of SRAM PUF units connected in parallel to each other, the purpose of which is to use a plurality of SRAM storage units in parallel to form a strong PUF structure, the parallel structure makes full use of the differences between the SRAM storage units, and enhances the number of PUF stimulus responses; wherein the SRAM PUF unit comprises: eight MOS tubes; the drain of the first MOS tube, the drain of the second MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube and the drain of the fifth MOS tube are connected to one point; the drain of the third MOS tube, the drain of the fourth MOS tube, the gate of the first MOS tube, the gate of the second MOS tube and the drain of the sixth MOS tube are connected to one point; the source of the first MOS tube, the source of the third MOS tube and the drain of the seventh MOS tube are connected to one point; the source of the second MOS tube, the source of the fourth MOS tube and the drain of the eighth MOS tube are connected to one point; the source of the seventh MOS tube is connected to VDD; and the source of the eighth MOS tube is connected to GND. The fifth MOS tube and the sixth MOS tube serve as switches for each SRAM cell, and are used to select whether the cell is connected in parallel with other SRAM cells. This select-and-use method effectively reduces the power consumption of the entire circuit and improves the practicality of the system structure, because the SRAM cell is connected to the parallel structure only when needed, otherwise the cell is in a dormant state. In addition, the seventh MOS tube and the eighth MOS tube are not only used to reduce the power consumption of the PUF, but also to input an enable level to the PUF to generate a response. When a certain SRAM cell needs to be stimulated, the enable level will be input into the corresponding SRAM structure, triggering its response generation process. When a certain SRAM cell is not needed, the enable level will not be input, which ensures that the unselected SRAM cell does not waste energy.

[0054] The above embodiments are only used to illustrate the design ideas and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The protection scope of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or decorations made according to the principles and design ideas disclosed by the present invention are within the protection scope of the present invention.

Claims

1. A strong PUF system based on SRAM, characterized in that: include: Multiple SRAM PUF cells connected in parallel with each other; Among them, the SRAM PUF unit includes: eight MOS tubes; The drain of the first MOS tube, the drain of the second MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube and the drain of the fifth MOS tube are connected to one point; The drain of the third MOS tube, the drain of the fourth MOS tube, the gate of the first MOS tube, the gate of the second MOS tube and the drain of the sixth MOS tube are connected to one point; The source of the first MOS tube, the source of the third MOS tube and the drain of the seventh MOS tube are connected to one point; The source of the second MOS tube, the source of the fourth MOS tube and the drain of the eighth MOS tube are connected to one point; The source of the seventh MOS tube is connected to VDD; The source of the eighth MOS tube is connected to GND.

2. The SRAM-based strong PUF system according to claim 1, characterized in that: The multiple SRAM PUF units connected in parallel to each other include: The source of the fifth MOS transistor of the first SRAM PUF unit is connected to the source of the fifth MOS transistor of the second SRAM PUF unit.

3. The SRAM-based strong PUF system according to claim 2, characterized in that: The plurality of SRAM PUF units connected in parallel to each other further include: The source of the sixth MOS transistor of the first SRAM PEF unit is connected to the source of the sixth MOS transistor of the second SRAM PUF unit.

4. The SRAM-based strong PUF system according to claim 1, characterized in that: The system further includes: a first control signal unit, wherein the first control signal unit is connected to the gate of the seventh MOS tube.

5. The SRAM-based strong PUF system according to claim 4, characterized in that: The system further includes: a second control signal unit, and the second control signal unit is connected to the drain of the eighth MOS tube.

6. The SRAM-based strong PUF system according to claim 5, characterized in that: The second control signal unit is connected to the gate of the fifth MOS tube.

7. The SRAM-based strong PUF system according to claim 5, characterized in that: The second control signal unit is connected to the gate of the sixth MOS tube.

8. The SRAM-based strong PUF system according to claim 5, characterized in that: The system further includes: a first output signal unit, wherein the first output signal unit is connected to the source of the fifth MOS tube.

9. The SRAM-based strong PUF system according to claim 8, characterized in that: The system further includes: a second output signal unit, and the second output signal unit is connected to the source of the sixth MOS tube.

10. The SRAM-based strong PUF system according to claim 9, characterized in that: The sixth MOS tube is an NMOS tube.

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