Preparation method of gate oxide layer of silicon carbide chip

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a silicon carbide chip gate oxide layer preparation method comprising the following steps: step 1, pretreatment and surface preparation; carrying out flattening treatment on the surface of the silicon carbide chip by utilizing a chemical mechanical polishing technology, and removing surface impurities and microscopic non-uniformity; generating a flattened silicon carbide surface; step 2, cleaning and surface activation; surface oxides are removed by adopting a method of soaking in a hydrofluoric acid solution, so that the surface becomes hydrophilic; and a hydrophilic silicon carbide surface is formed. Through the steps of pretreatment and surface preparation, cleaning and surface activation, preliminary formation of the oxide layer, deposition of the vapor deposition control layer, accurate thickness control of the oxide layer, quality evaluation of the oxide layer, surface modification and active center introduction and post-treatment of the terminal oxide layer, the uniformity and thickness of the gate oxide layer can be controlled; and the nanoscale precision of the thickness of the gate oxide layer is controlled, so that the microscopic performance and the stability are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and more specifically, to a method for preparing a gate oxide layer of a silicon carbide chip. Background Art

[0002] Compared with silicon-based devices, silicon carbide power devices have higher breakdown field strength and better thermal conductivity, and have attracted much attention. Among them, silicon carbide gate-controlled power chips such as MOSFET and IGBT have gradually attracted attention due to their advantages such as high power density, fast switching speed, and high thermal conductivity. The gate oxide layer preparation methods of conventional gate-controlled devices mainly include direct high-temperature thermal oxidation of the silicon carbide surface and direct chemical vapor deposition.

[0003] However, the existing method for preparing the gate oxide layer of a silicon carbide chip is direct chemical vapor deposition, which lacks a mechanism for controlling the growth rate and uniformity of the oxide layer, resulting in the inability to control the growth rate and uniformity of the gate oxide layer. There is also a lack of precise control of the deposition rate and time of the oxide layer, resulting in the inability to accurately control the thickness of the oxide layer. When modifying the surface of the oxide layer, it is impossible to effectively enhance the functionality of the device and form a functionally modified oxide layer surface. When the oxide layer is thermally annealed, the stability and oxidation resistance of the oxide layer cannot be improved according to the environment and requirements, resulting in low quality of the oxide layer. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the present invention provides a method for preparing a gate oxide layer of a silicon carbide chip, which has the advantages of controlling the uniformity and thickness of the gate oxide layer and controlling the thickness of the gate oxide layer with nanometer-level precision, thereby improving microscopic performance and stability.

[0005] To achieve the above object, the present invention provides the following technical solution: a method for preparing a gate oxide layer of a silicon carbide chip, comprising the following steps:

[0006] Step 1: Pretreatment and surface preparation: Use chemical mechanical polishing technology to flatten the surface of the silicon carbide chip, remove surface impurities and microscopic unevenness, and generate a flat silicon carbide surface;

[0007] Step 2: Cleaning and surface activation: Using the method of immersing in a hydrofluoric acid solution to remove the surface oxides, making the surface hydrophilic, and forming a hydrophilic silicon carbide surface;

[0008] Step 3: Initial formation of oxide layer: placing the processed silicon carbide chip into a dry oxidation furnace, and forming a preliminary oxide layer on the surface of silicon carbide by thermal oxidation method; forming an initial oxide layer structure;

[0009] Step 4: Vapor deposition control layer deposition: using chemical vapor deposition technology to deposit a control layer to control the growth rate and uniformity of the subsequent oxide layer; generating a silicon carbide surface covered with the control layer;

[0010] Step 5: Precise oxide layer thickness control: Deposit an oxide layer on the control layer by electron beam physical vapor deposition technology, and achieve sub-nanometer oxide layer thickness by precisely controlling the deposition rate and time; form a precisely controlled oxide layer;

[0011] Step 6: Oxide layer quality assessment: Use atomic force microscopy and transmission electron microscopy techniques to assess the surface roughness and crystalline structure of the oxide layer; determine the quality and uniformity of the oxide layer;

[0012] Step 7: Surface modification and introduction of active centers: using the sol-gel method to introduce metal centers, modify the oxide layer surface, and enhance the functionality of the device; forming a functionally modified oxide layer surface;

[0013] Step 8: Post-treatment of the terminal oxide layer: Through thermal annealing, the stability and anti-oxidation performance of the oxide layer are further improved; a stable and high-quality terminal oxide layer is formed;

[0014] Step 9: Final evaluation and device performance testing: Use a capacitance tester to test the dielectric constant, leakage current, and electron mobility of the gate oxide layer on the silicon carbide chip; verify that the oxide layer meets the design requirements and improve the electrical performance and stability of the device.

[0015] As a preferred technical solution of the method for preparing the gate oxide layer of a silicon carbide chip of the present invention, pretreatment and surface preparation; using chemical mechanical polishing technology to flatten the surface of the silicon carbide chip to remove surface impurities and microscopic unevenness; the specific steps of generating a flattened silicon carbide surface are:

[0016] Step 1.1: Chemical mechanical polishing treatment; using a chemical mechanical polisher, combined with a silicon substrate, using rotation and grinding technology to remove surface residual materials and micro-unevenness; generating a flat silicon carbide surface;

[0017] Step 1.2: Surface cleaning: In an ultrasonic cleaning tank, use deionized water and organic solvent to completely remove surface impurities and residual substances to form a clean silicon carbide surface;

[0018] Step 1.3: Surface activation treatment: soaking in hydrofluoric acid solution to remove the surface oxide layer through chemical reaction and increase the surface hydrophilicity; generate a hydrophilic silicon carbide surface;

[0019] Step 1.4: Drying treatment: Dry the processed chip in a high-temperature drying oven to ensure that the surface is completely dry and clean; forming a clean and dry silicon carbide surface.

[0020] As a preferred technical solution of the method for preparing the gate oxide layer of a silicon carbide chip of the present invention, cleaning and surface activation; using a method of immersing in a hydrofluoric acid solution to remove the surface oxide and make the surface hydrophilic; the specific steps of forming a hydrophilic silicon carbide surface are:

[0021] Step 2.1: Preheating the oxidation furnace; start the oxidation furnace and preheat it, set the temperature and atmosphere to prepare for the oxidation process; the oxidation furnace reaches the set temperature and stable atmosphere conditions;

[0022] Step 2.2: Thermal oxidation process: placing the pre-treated silicon carbide chip in an oxidation furnace, and forming an initial oxide layer in a high temperature and oxygen environment through thermal oxidation technology; generating a preliminary oxide layer structure;

[0023] Step 2.3: Oxide layer quality check; measure the thickness and uniformity of the oxide layer using an ellipsometer; confirm the quality and uniformity of the initial oxide layer;

[0024] Step 2.4: Cooling treatment: After the oxidation is completed, gradually lower the temperature of the oxidation furnace to room temperature to avoid changes and deformation of the oxide layer structure; forming a stable oxide layer surface.

[0025] As a preferred technical solution of the method for preparing a gate oxide layer of a silicon carbide chip of the present invention, the oxide layer is initially formed; the treated silicon carbide chip is placed in a dry oxidation furnace, and a preliminary oxide layer is formed on the surface of the silicon carbide by a thermal oxidation method; the specific steps of forming the initial oxide layer structure pair are:

[0026] Step 3.1: Chemical vapor deposition pretreatment: In the CVD reaction chamber, the chip surface is pretreated to remove residues and organic pollutants to form a clean reaction surface;

[0027] Step 3.2: CVD control layer deposition: depositing a control layer by thermal decomposition chemical vapor deposition to control the growth rate and uniformity of the subsequent oxide layer; generating a silicon carbide surface covered with the control layer;

[0028] Step 3.3: Control layer quality check: Use X-ray diffraction technology to evaluate the crystal structure and chemical composition of the control layer; confirm the quality and structure of the control layer;

[0029] Step 3.4: Post-processing of the control layer: annealing the control layer in an inert atmosphere to improve its crystallinity and chemical stability; and forming a stable control layer surface.

[0030] As a preferred technical solution of the method for preparing the gate oxide layer of a silicon carbide chip of the present invention, vapor deposition control layer deposition; using chemical vapor deposition technology, a control layer is deposited to control the growth rate and uniformity of the subsequent oxide layer; the specific steps of generating the silicon carbide surface covered by the control layer are:

[0031] Step 4.1: Electron beam physical vapor deposition pretreatment: In a vacuum chamber, the control layer is surface cleaned and pretreated to ensure a smooth surface and no organic residue, forming a clean reaction surface;

[0032] Step 4.2: Precise oxide layer deposition; depositing an oxide layer on the control layer at a sub-nanometer precisely controlled rate and time by electron beam thermal evaporation technology; forming a sub-nanometer precisely controlled oxide layer;

[0033] Step 4.3: Oxide layer thickness measurement: Use an ellipsometer to measure the thickness and surface morphology of the oxide layer; determine the precise thickness and surface quality of the oxide layer;

[0034] Step 4.4: Oxide layer uniformity inspection; Using a microscope, inspect the oxide layer for uniformity and defect-freeness; Confirm the uniformity and quality of the oxide layer.

[0035] As a preferred technical solution of the method for preparing the gate oxide layer of a silicon carbide chip of the present invention, the oxide layer thickness is precisely controlled; the oxide layer is deposited on the control layer by electron beam physical vapor deposition technology, and the thickness of the oxide layer is sub-nanometer by precisely controlling the deposition rate and time; the specific steps of forming the precisely controlled oxide layer are:

[0036] Step 5.1: Set basic conditions; in the electron beam physical vapor deposition EBPVD system, ensure that the deposition chamber and substrate surface are clean and reach the required vacuum level;

[0037] Step 5.2: Precisely control the deposition rate; adjust the power and position of the electron beam to control the deposition rate of the oxide layer. Through monitoring and feedback mechanisms, ensure that the deposition rate is precisely controlled in the sub-nanometer range;

[0038] Step 5.3: Timed deposition: Set the deposition time to deposit the oxide layer, and precise time control ensures that the thickness of the oxide layer meets the specifications;

[0039] Step 5.4: Online monitoring and adjustment; Use surface scanning technology to measure the thickness of the oxide layer in real time, and make necessary adjustments based on the measurement results to ensure that the oxide layer thickness in each area is uniform.

[0040] As a preferred technical solution of the method for preparing the gate oxide layer of a silicon carbide chip of the present invention, the quality of the oxide layer is evaluated; the surface roughness and crystal structure of the oxide layer are evaluated using atomic force microscopy and transmission electron microscopy technology; the specific steps for determining the quality and uniformity of the oxide layer are:

[0041] Step 6.1: Atomic force microscopy (AFM) to evaluate surface roughness; Use AFM technology to measure the roughness of the oxide layer surface, analyze the obtained images and data, and evaluate the flatness and surface quality of the oxide layer;

[0042] Step 6.2: Transmission electron microscopy (TEM) to evaluate the crystalline structure: Use TEM technology to perform high-resolution microstructural analysis of the oxide layer to examine its crystal structure, grain size, and possible defects.

[0043] Step 6.3: Data analysis and comparison: Compare the AFM and TEM results with the design specifications and previous standards to ensure that the quality and uniformity of the oxide layer meet the expected requirements.

[0044] As a preferred technical solution of the method for preparing the gate oxide layer of a silicon carbide chip of the present invention, surface modification and introduction of active centers; using a sol-gel method to introduce metal centers, modify the surface of the oxide layer, and enhance the functionality of the device; the specific steps of forming the functionally modified oxide layer surface are:

[0045] Steps: 7.1: Sol-gel method selection and preparation; prepare sol and gel solutions according to the set chemical formula and process parameters to facilitate subsequent surface modification and active center introduction;

[0046] Step 7.2: Surface pretreatment and modification: applying sol-gel solution on the surface of the oxide layer to achieve chemical modification of the surface by immersion; controlling the treatment time and temperature to ensure the uniformity and stability of the modified layer;

[0047] Step 7.3: Introduction of active centers: adding metal precursors to the sol-gel system to chemically react with the surface of the oxide layer to introduce the desired functional groups;

[0048] Step 7.4: Evaluation of modification effects; Use FT IR surface analysis technology to confirm the composition and structural characteristics of the surface modification and evaluate its impact on the oxide layer interface and overall performance.

[0049] As a preferred technical solution of the method for preparing the gate oxide layer of a silicon carbide chip of the present invention, the terminal oxide layer is post-processed; the stability and anti-oxidation performance of the oxide layer are further improved by thermal annealing; the specific steps of forming a stable and high-quality terminal oxide layer are:

[0050] Step 8.1: Select post-treatment method; select thermal annealing treatment according to the composition of the oxide layer and the expected performance requirements;

[0051] Step 8.2: Perform a post-treatment process; perform a thermal annealing treatment under controlled atmosphere conditions, adjusting the treatment temperature, time and environment to promote the stabilization of the internal structure of the oxide layer and the rearrangement of the lattice;

[0052] Step 8.3: Quality verification and analysis; Use Raman spectroscopy structural analysis technology to confirm the impact of the post-treatment process on the oxide layer structure and crystal properties; Ensure that the stability and antioxidant properties of the oxide layer are improved after post-treatment.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] The present invention adopts chemical vapor deposition technology to deposit a control layer, thereby controlling the growth rate and uniformity of the subsequent oxide layer and generating a silicon carbide surface covered by the control layer; then, an oxide layer is deposited on the control layer by electron beam physical vapor deposition technology, and a sub-nanometer oxide layer thickness is achieved by precisely controlling the deposition rate and time, thereby forming a precisely controlled oxide layer, thereby achieving control over the uniformity and thickness of the gate oxide layer; by adopting a sol-gel method, a metal center is introduced to modify the oxide layer surface, thereby enhancing the functionality of the device and forming a functionally modified oxide layer surface; by thermal annealing treatment, the stability and oxidation resistance of the oxide layer are further improved, thereby forming a stable and high-quality terminal oxide layer, thereby achieving nanometer-level precision control over the thickness of the gate oxide layer and improving the microscopic performance and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a flow chart of the main steps of the present invention;

[0056] Figure 2 A detailed flow chart of step 1 of the present invention;

[0057] Figure 3 Refine the flow chart for step 2 of the present invention;

[0058] Figure 4 Refine the flow chart for step 3 of the present invention;

[0059] Figure 5 Refine the flow chart for step 4 of the present invention;

[0060] Figure 6 Refine the flow chart for step 5 of the present invention;

[0061] Figure 7 Refine the flow chart for step 6 of the present invention;

[0062] Figure 8Refine the flow chart for step 7 of the present invention;

[0063] Fig. 9 The flowchart of step 8 of the present invention is refined. DETAILED DESCRIPTION

[0064] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] like Figures 1 to 9 As shown, the present invention provides a method for preparing a gate oxide layer of a silicon carbide chip, comprising the following steps:

[0066] Step 1: Pretreatment and surface preparation: Use chemical mechanical polishing technology to flatten the surface of the silicon carbide chip, remove surface impurities and microscopic unevenness, and generate a flat silicon carbide surface;

[0067] Step 2: Cleaning and surface activation: Using the method of immersing in a hydrofluoric acid solution, the surface oxide is removed to make the surface hydrophilic, thereby forming a hydrophilic silicon carbide surface;

[0068] Step 3: Initial formation of oxide layer: placing the processed silicon carbide chip into a dry oxidation furnace, and forming a preliminary oxide layer on the surface of silicon carbide by thermal oxidation method; forming an initial oxide layer structure;

[0069] Step 4: Vapor deposition control layer deposition: using chemical vapor deposition technology to deposit a control layer to control the growth rate and uniformity of the subsequent oxide layer; generating a silicon carbide surface covered with the control layer;

[0070] Step 5: Precise oxide layer thickness control: Deposit an oxide layer on the control layer by electron beam physical vapor deposition technology, and achieve sub-nanometer oxide layer thickness by precisely controlling the deposition rate and time; form a precisely controlled oxide layer;

[0071] Step 6: Oxide layer quality assessment: Use atomic force microscopy and transmission electron microscopy techniques to assess the surface roughness and crystalline structure of the oxide layer; determine the quality and uniformity of the oxide layer;

[0072] Step 7: Surface modification and introduction of active centers: using the sol-gel method to introduce metal centers, modify the oxide layer surface, and enhance the functionality of the device; forming a functionally modified oxide layer surface;

[0073] Step 8: Post-treatment of the terminal oxide layer: Through thermal annealing, the stability and anti-oxidation performance of the oxide layer are further improved; a stable and high-quality terminal oxide layer is formed;

[0074] Step 9: Final evaluation and device performance testing: Use a capacitance tester to test the dielectric constant, leakage current, and electron mobility of the gate oxide layer on the silicon carbide chip; verify that the oxide layer meets the design requirements and improve the electrical performance and stability of the device.

[0075] Among them, pre-treatment and surface preparation; using chemical mechanical polishing technology to flatten the surface of the silicon carbide chip to remove surface impurities and microscopic unevenness; the specific steps of generating a flattened silicon carbide surface are:

[0076] Step 1.1: Chemical mechanical polishing treatment; using a chemical mechanical polisher, combined with a silicon substrate, using rotation and grinding technology to remove surface residual materials and micro-unevenness; generating a flat silicon carbide surface;

[0077] Step 1.2: Surface cleaning: In an ultrasonic cleaning tank, use deionized water and organic solvent to completely remove surface impurities and residual substances to form a clean silicon carbide surface;

[0078] Step 1.3: Surface activation treatment: soaking in hydrofluoric acid solution to remove the surface oxide layer through chemical reaction and increase the surface hydrophilicity; generate a hydrophilic silicon carbide surface;

[0079] Step 1.4: Drying treatment: Dry the processed chip in a high-temperature drying oven to ensure that the surface is completely dry and clean; forming a clean and dry silicon carbide surface.

[0080] Among them, cleaning and surface activation; using the method of immersing in a hydrofluoric acid solution to remove surface oxides and make the surface hydrophilic; the specific steps of forming a hydrophilic silicon carbide surface are:

[0081] Step 2.1: Preheating the oxidation furnace; start the oxidation furnace and preheat it, set the temperature and atmosphere to prepare for the oxidation process; the oxidation furnace reaches the set temperature and stable atmosphere conditions;

[0082] Step 2.2: Thermal oxidation process: placing the pre-treated silicon carbide chip in an oxidation furnace, and forming an initial oxide layer in a high temperature and oxygen environment through thermal oxidation technology; generating a preliminary oxide layer structure;

[0083] Step 2.3: Oxide layer quality check; measure the thickness and uniformity of the oxide layer using an ellipsometer; confirm the quality and uniformity of the initial oxide layer;

[0084] Step 2.4: Cooling treatment: After the oxidation is completed, gradually lower the temperature of the oxidation furnace to room temperature to avoid changes and deformation of the oxide layer structure; forming a stable oxide layer surface.

[0085] Among them, the oxide layer is initially formed; the treated silicon carbide chip is placed in a dry oxidation furnace, and a preliminary oxide layer is formed on the surface of the silicon carbide by a thermal oxidation method; the specific steps of forming the initial oxide layer structure pair are:

[0086] Step 3.1: Chemical vapor deposition pretreatment: In the CVD reaction chamber, the chip surface is pretreated to remove residues and organic pollutants to form a clean reaction surface;

[0087] Step 3.2: CVD control layer deposition: depositing a control layer by thermal decomposition chemical vapor deposition to control the growth rate and uniformity of the subsequent oxide layer; generating a silicon carbide surface covered with the control layer;

[0088] Step 3.3: Control layer quality check: Use X-ray diffraction technology to evaluate the crystal structure and chemical composition of the control layer; confirm the quality and structure of the control layer;

[0089] Step 3.4: Post-processing of the control layer: annealing the control layer in an inert atmosphere to improve its crystallinity and chemical stability; and forming a stable control layer surface.

[0090] Among them, vapor deposition control layer deposition; using chemical vapor deposition technology, a control layer is deposited to control the growth rate and uniformity of the subsequent oxide layer; the specific steps of generating the silicon carbide surface covered by the control layer are:

[0091] Step 4.1: Electron beam physical vapor deposition pretreatment: In a vacuum chamber, the control layer is surface cleaned and pretreated to ensure a smooth surface and no organic residue, forming a clean reaction surface;

[0092] Step 4.2: Precise oxide layer deposition; depositing an oxide layer on the control layer at a sub-nanometer precisely controlled rate and time by electron beam thermal evaporation technology; forming a sub-nanometer precisely controlled oxide layer;

[0093] Step 4.3: Oxide layer thickness measurement: Use an ellipsometer to measure the thickness and surface morphology of the oxide layer; determine the precise thickness and surface quality of the oxide layer;

[0094] Step 4.4: Oxide layer uniformity inspection; Using a microscope, inspect the oxide layer for uniformity and defect-freeness; Confirm the uniformity and quality of the oxide layer.

[0095] Among them, the oxide layer thickness is precisely controlled; the oxide layer is deposited on the control layer by electron beam physical vapor deposition technology, and the thickness of the oxide layer at the sub-nanometer level is achieved by precisely controlling the deposition rate and time; the specific steps of forming the precisely controlled oxide layer are:

[0096] Step 5.1: Set basic conditions; in the electron beam physical vapor deposition EBPVD system, ensure that the deposition chamber and substrate surface are clean and reach the required vacuum level;

[0097] Step 5.2: Precisely control the deposition rate; adjust the power and position of the electron beam to control the deposition rate of the oxide layer. Through monitoring and feedback mechanisms, ensure that the deposition rate is precisely controlled in the sub-nanometer range;

[0098] Step 5.3: Timed deposition: Set the deposition time to deposit the oxide layer, and precise time control ensures that the thickness of the oxide layer meets the specifications;

[0099] Step 5.4: Online monitoring and adjustment; Use surface scanning technology to measure the thickness of the oxide layer in real time, and make necessary adjustments based on the measurement results to ensure that the oxide layer thickness in each area is uniform.

[0100] Among them, the quality assessment of the oxide layer; the surface roughness and crystal structure of the oxide layer are assessed using atomic force microscopy and transmission electron microscopy techniques; the specific steps for determining the quality and uniformity of the oxide layer are:

[0101] Step 6.1: Atomic force microscopy (AFM) to evaluate surface roughness; Use AFM technology to measure the roughness of the oxide layer surface, analyze the obtained images and data, and evaluate the flatness and surface quality of the oxide layer;

[0102] Step 6.2: Transmission electron microscopy (TEM) to evaluate the crystalline structure: Use TEM technology to perform high-resolution microstructural analysis of the oxide layer to examine its crystal structure, grain size, and possible defects.

[0103] Step 6.3: Data analysis and comparison: Compare the AFM and TEM results with the design specifications and previous standards to ensure that the quality and uniformity of the oxide layer meet the expected requirements.

[0104] Among them, surface modification and introduction of active centers; using the sol-gel method to introduce metal centers, modify the surface of the oxide layer, and enhance the functionality of the device; the specific steps for forming the functionally modified oxide layer surface are:

[0105] Steps: 7.1: Sol-gel method selection and preparation; prepare sol and gel solutions according to the set chemical formula and process parameters to facilitate subsequent surface modification and active center introduction;

[0106] Step 7.2: Surface pretreatment and modification: applying sol-gel solution on the surface of the oxide layer to achieve chemical modification of the surface by immersion; controlling the treatment time and temperature to ensure the uniformity and stability of the modified layer;

[0107] Step 7.3: Introduction of active centers: adding metal precursors to the sol-gel system to chemically react with the surface of the oxide layer to introduce the desired functional groups;

[0108] Step 7.4: Evaluation of modification effects; Use FT IR surface analysis technology to confirm the composition and structural characteristics of the surface modification and evaluate its impact on the oxide layer interface and overall performance.

[0109] Among them, the terminal oxide layer is post-processed; the stability and anti-oxidation performance of the oxide layer are further improved by thermal annealing; the specific steps for forming a stable and high-quality terminal oxide layer are:

[0110] Step 8.1: Select post-treatment method; select thermal annealing treatment according to the composition of the oxide layer and the expected performance requirements;

[0111] Step 8.2: Perform a post-treatment process; perform a thermal annealing treatment under controlled atmosphere conditions, adjusting the treatment temperature, time and environment to promote the stabilization of the internal structure of the oxide layer and the rearrangement of the lattice;

[0112] Step 8.3: Quality verification and analysis; Use Raman spectroscopy structural analysis technology to confirm the impact of the post-treatment process on the oxide layer structure and crystal properties; Ensure that the stability and antioxidant properties of the oxide layer are improved after post-treatment.

[0113] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0114] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for preparing a gate oxide layer of a silicon carbide chip, characterized in that: The following steps are involved: Step 1: Pretreatment and surface preparation: Use chemical mechanical polishing technology to flatten the surface of the silicon carbide chip to remove surface impurities and microscopic unevenness; Producing a flattened silicon carbide surface; Step 2: Cleaning and surface activation; The surface oxide is removed by immersing in a hydrofluoric acid solution, making the surface hydrophilic, thereby forming a hydrophilic silicon carbide surface; Step 3: Initial formation of oxide layer: placing the processed silicon carbide chip into a dry oxidation furnace, and forming a preliminary oxide layer on the surface of silicon carbide by thermal oxidation method; forming an initial oxide layer structure; Step 4: Vapor deposition control layer deposition; Using chemical vapor deposition technology, a control layer is deposited to control the growth rate and uniformity of the subsequent oxide layer; generating a silicon carbide surface covered with a control layer; Step 5: Precise oxide layer thickness control: Deposit an oxide layer on the control layer by electron beam physical vapor deposition technology, and achieve sub-nanometer oxide layer thickness by precisely controlling the deposition rate and time; form a precisely controlled oxide layer; Step 6: Oxide layer quality assessment: Use atomic force microscopy and transmission electron microscopy techniques to assess the surface roughness and crystalline structure of the oxide layer; determine the quality and uniformity of the oxide layer; Step 7: Surface modification and introduction of active centers; Using the sol-gel method, metal centers are introduced to modify the oxide layer surface and enhance the functionality of the device; a functionally modified oxide layer surface is formed; Step 8: Post-treatment of terminal oxide layer; Through thermal annealing treatment, the stability and anti-oxidation performance of the oxide layer are further improved; a stable and high-quality terminal oxide layer is formed; Step 9: Final evaluation and device performance testing: Use a capacitance tester to test the dielectric constant, leakage current, and electron mobility of the gate oxide layer on the silicon carbide chip; verify that the oxide layer meets the design requirements and improve the electrical performance and stability of the device.

2. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: Pretreatment and surface preparation: Use chemical mechanical polishing technology to flatten the surface of the silicon carbide chip to remove surface impurities and microscopic unevenness; the specific steps to generate a flat silicon carbide surface are: Step 1.1: Chemical mechanical polishing treatment; using a chemical mechanical polisher, combined with a silicon substrate, using rotation and grinding technology to remove surface residual materials and micro-unevenness; generating a flat silicon carbide surface; Step 1.2: Surface cleaning: In an ultrasonic cleaning tank, use deionized water and organic solvent to completely remove surface impurities and residual substances to form a clean silicon carbide surface; Step 1.3: Surface activation treatment: soaking in hydrofluoric acid solution to remove the surface oxide layer through chemical reaction and increase the surface hydrophilicity; Generate a hydrophilic silicon carbide surface; Step 1.4: Drying; The processed chips are dried in a high-temperature drying oven to ensure that the surface is completely dry and clean; forming a clean and dry silicon carbide surface.

3. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: Cleaning and surface activation: Using the method of immersing in a hydrofluoric acid solution to remove surface oxides and make the surface hydrophilic; the specific steps for forming a hydrophilic silicon carbide surface are: Step 2.1: Preheating the oxidation furnace; start the oxidation furnace and preheat it, set the temperature and atmosphere to prepare for the oxidation process; the oxidation furnace reaches the set temperature and stable atmosphere conditions; Step 2.2: Thermal oxidation process; The pre-treated silicon carbide chip is placed in an oxidation furnace to form an initial oxide layer in a high temperature and oxygen environment through thermal oxidation technology; Generate a preliminary oxide layer structure; Step 2.3: Oxide layer quality check; measure the thickness and uniformity of the oxide layer using an ellipsometer; confirm the quality and uniformity of the initial oxide layer; Step 2.4: Cooling treatment: After the oxidation is completed, gradually lower the temperature of the oxidation furnace to room temperature to avoid changes and deformation of the oxide layer structure; forming a stable oxide layer surface.

4. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: The oxide layer is initially formed; the treated silicon carbide chip is placed in a dry oxidation furnace, and a preliminary oxide layer is formed on the surface of the silicon carbide by a thermal oxidation method; the specific steps for forming the initial oxide layer structure are: Step 3.1: Chemical vapor deposition pretreatment: In the CVD reaction chamber, the chip surface is pretreated to remove residues and organic pollutants to form a clean reaction surface; Step 3.2: CVD control layer deposition: depositing a control layer by thermal decomposition chemical vapor deposition to control the growth rate and uniformity of the subsequent oxide layer; generating a silicon carbide surface covered with the control layer; Step 3.3: Control layer quality check: Use X-ray diffraction technology to evaluate the crystal structure and chemical composition of the control layer; confirm the quality and structure of the control layer; Step 3.4: Control layer post-processing; Under an inert atmosphere, the control layer is annealed to improve its crystallinity and chemical stability, thereby forming a stable control layer surface.

5. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: Vapor deposition control layer deposition: using chemical vapor deposition technology to deposit a control layer to control the growth rate and uniformity of the subsequent oxide layer; The specific steps for generating a silicon carbide surface covered with a control layer are: Step 4.1: Electron beam physical vapor deposition pretreatment: In a vacuum chamber, the control layer is surface cleaned and pretreated to ensure a smooth surface and no organic residue, forming a clean reaction surface; Step 4.2: Precise oxide layer deposition; By using electron beam thermal evaporation technology, an oxide layer is deposited on the control layer at a sub-nanometer precisely controlled rate and time; forming an oxide layer precisely controlled at the sub-nanometer level; Step 4.3: Oxide layer thickness measurement: Use an ellipsometer to measure the thickness and surface morphology of the oxide layer; determine the precise thickness and surface quality of the oxide layer; Step 4.4: Oxide layer uniformity inspection; Using a microscope, inspect the oxide layer for uniformity and defect-freeness; Confirm the uniformity and quality of the oxide layer.

6. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: Precise oxide layer thickness control: The oxide layer is deposited on the control layer by electron beam physical vapor deposition technology, and the sub-nanometer oxide layer thickness is achieved by precisely controlling the deposition rate and time; the specific steps for forming a precisely controlled oxide layer are: Step 5.1: Set basic conditions; in the electron beam physical vapor deposition EBPVD system, ensure that the deposition chamber and substrate surface are clean and reach the required vacuum level; Step 5.2: Precisely control the deposition rate; adjust the power and position of the electron beam to control the deposition rate of the oxide layer. Through monitoring and feedback mechanisms, ensure that the deposition rate is precisely controlled in the sub-nanometer range; Step 5.3: Timed deposition; Set the deposition time to deposit the oxide layer. Precise time control ensures that the thickness of the oxide layer meets the specifications. Step 5.4: Online monitoring and adjustment; Use surface scanning technology to measure the thickness of the oxide layer in real time, and make necessary adjustments based on the measurement results to ensure that the oxide layer thickness in each area is uniform.

7. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: Oxide layer quality assessment: The surface roughness and crystalline structure of the oxide layer are assessed using atomic force microscopy and transmission electron microscopy techniques. The specific steps to determine the quality and uniformity of the oxide layer are: Step 6.1: Atomic force microscopy (AFM) to evaluate surface roughness; Use AFM technology to measure the roughness of the oxide layer surface, analyze the obtained images and data, and evaluate the flatness and surface quality of the oxide layer; Step 6.2: Transmission electron microscopy (TEM) to evaluate the crystalline structure: Use TEM technology to perform high-resolution microstructural analysis of the oxide layer to examine its crystal structure, grain size, and possible defects. Step 6.3: Data analysis and comparison: Compare the AFM and TEM results with the design specifications and previous standards to ensure that the quality and uniformity of the oxide layer meet the expected requirements.

8. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: Surface modification and introduction of active centers: using the sol-gel method to introduce metal centers, modify the oxide layer surface, and enhance the functionality of the device; the specific steps for forming a functionally modified oxide layer surface are: Steps: 7.1: Sol-gel method selection and preparation; prepare sol and gel solutions according to the set chemical formula and process parameters to facilitate subsequent surface modification and active center introduction; Step 7.2: Surface pretreatment and modification; Apply sol-gel solution on the surface of the oxide layer to achieve chemical modification of the surface by immersion; control the treatment time and temperature to ensure the uniformity and stability of the modified layer; Step 7.3: introduction of active centers; Adding metal precursors to the sol-gel system to chemically react with the surface of the oxide layer to introduce the desired functional groups; Step 7.4: Evaluation of modification effects; Use FTIR surface analysis technology to confirm the composition and structural characteristics of the surface modification and evaluate its impact on the oxide layer interface and overall performance.

9. The method for preparing a gate oxide layer of a silicon carbide chip according to claim 1, characterized in that: Post-treatment of the terminal oxide layer: Through thermal annealing, the stability and anti-oxidation performance of the oxide layer are further improved; the specific steps to form a stable and high-quality terminal oxide layer are: Step 8.1: Select post-treatment method; select thermal annealing treatment according to the composition of the oxide layer and the expected performance requirements; Step 8.2: Perform a post-treatment process; perform a thermal annealing treatment under controlled atmosphere conditions, adjusting the treatment temperature, time and environment to promote the stabilization of the internal structure of the oxide layer and the rearrangement of the lattice; Step 8.3: Quality verification and analysis; Use Raman spectroscopy structural analysis technology to confirm the impact of the post-treatment process on the oxide layer structure and crystal properties; Ensure that the stability and antioxidant properties of the oxide layer are improved after post-treatment.

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