Super junction IGBT (Insulated Gate Bipolar Translator) device structure and process method

Abstract

The invention discloses a super-junction IGBT device structure and a process method, according to the super-junction IGBT device structure, a dummy gate with a small CD value is added between device gate trenches, during etching of a gate trench with a high aspect ratio, due to a load effect, the trench etching rate of the dummy gate with the small CD value is smaller than the etching rate of the gate trench of a device with a large CD value, and the trench etching rate of the dummy gate with the small CD value is smaller than the etching rate of the gate trench of the device with the large CD value. The etching depth of the trench of the dummy gate is reduced by reducing the CD value of the dummy gate. The depth of the trench of the dummy gate does not penetrate through the p-body layer, so that Cgd is not affected. The method has the advantages that the peak voltage of Vg and Vds when the device is turned on is reduced, and the soft turn-on of the device is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a super junction IGBT device structure. Background Art

[0002] The super junction (SJ) structure is a structure of alternating N-type columns and P-type columns. Super junction devices use low-resistivity epitaxial layers to significantly reduce the on-resistance of the device. In the super junction structure, the distribution of N-type impurities in the N-type columns, the distribution of P-type impurities in the P-type columns, and the matching of the distribution of N-type impurities in the alternating N-type columns and the distribution of P-type impurities in the P-type columns will affect the characteristics of the super junction semiconductor device, including its reverse breakdown voltage, avalanche current tolerance, and turn-off characteristics. General super junction semiconductor devices adopt a design that achieves the best charge balance between the alternating N-type columns and P-type columns to obtain the maximum reverse breakdown voltage.

[0003] The SJ structure can significantly improve the conduction performance of MOS devices while reducing the chip area. Combining the SJ structure with IGBT can produce SJ-IGBT devices. Compared with traditional IGBT devices, SJ-IGBT devices have higher drift region doping concentrations, which can reduce the forward conduction voltage drop of the device and achieve a better compromise between the forward conduction voltage drop and turn-off loss. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a super junction IGBT device structure.

[0005] Another technical problem to be solved by the present invention is to provide a process method for manufacturing the super junction IGBT device structure.

[0006] In order to solve the above problems, a process method of a super junction IGBT device structure according to the present invention comprises: Providing a semiconductor substrate, and forming a super junction N-type epitaxial layer on the semiconductor substrate; forming a super junction structure of the IGBT device in the super junction N-type epitaxial layer; forming another epitaxial layer on the surface of the super junction N-type epitaxial layer; forming a hard mask layer on the entire surface of the epitaxial layer; Performing photolithography and etching processes to define a device gate forming region and a dummy gate region of the IGBT device structure on the hard mask layer; The epitaxial layer and the super junction N-type epitaxial layer below the epitaxial layer are etched using the hard mask layer as a shield to form a trench of the device gate and a trench of the Dummy gate.

[0007] The semiconductor substrate includes a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, and a gallium nitride substrate.

[0008] Furthermore, the super junction structure includes a plurality of P columns formed in the super junction N-type epitaxial layer and a P / N alternatingly arranged super junction structure formed by the super junction N-type epitaxial layer between the plurality of P columns; the super junction structure adopts an etching and filling method, firstly etching in the super junction N-type epitaxial layer to form a plurality of parallel deep trenches, and then filling the plurality of parallel deep trenches with a P-type epitaxial layer to form P columns, forming the super junction structure with the super junction N-type epitaxial layer.

[0009] Furthermore, the super junction structure adopts an ion implantation method to implant P-type impurity ions into the super junction N-type epitaxial layer to form a plurality of parallel P columns, which form the super junction structure with the super junction N-type epitaxial layer.

[0010] Furthermore, the hard mask layer is silicon oxide or silicon nitride.

[0011] Furthermore, the CD value of the groove of the device gate is greater than the CD value of the groove of the dummy gate, so that during synchronous etching, due to the load effect, the depth of the groove of the device gate formed is greater than the depth of the groove of the dummy gate.

[0012] Furthermore, the depth of the trench of the device gate is greater than that of the epitaxial layer and penetrates into the super junction N-type epitaxial layer, and the depth of the trench of the Dummy gate does not exceed the thickness of the epitaxial layer.

[0013] Furthermore, the process method also includes subsequent steps, including ion implantation in the front epitaxial layer to form a P-type body region of the super junction IGBT device, and then N-type impurity ion implantation to form an N+ source region; forming a gate dielectric layer and depositing and filling polysilicon in the trenches of the device gate and the trenches of the Dummy gate to form the device gate and the Dummy gate; depositing an interlayer dielectric and etching a contact hole to lead out the source.

[0014] A super junction IGBT device structure described in the present invention comprises: A semiconductor substrate is provided with a super junction N-type epitaxial layer; an epitaxial layer is further provided on the super junction N-type epitaxial layer, and the epitaxial layer has a P-type body region of the super junction IGBT device; and a source region of the super junction IGBT device is located above the P-type body region; A super junction structure is provided in the super junction N-type epitaxial layer; The super junction IGBT device has a plurality of trench-type device gates, the trenches of the device gates pass through the epitaxial layer, and the bottoms thereof are located in the super junction N-type epitaxial layer; The super junction IGBT device also has a trench-type Dummy gate; the CD value of the Dummy gate is smaller than the CD value of the device gate, and the bottom of the trench of the Dummy gate is located in the epitaxial layer, and its depth is not greater than the epitaxial layer; The Dummy gate is located between the device gates; The semiconductor substrate serves as the collector of the super junction IGBT device, and an electrode is led out from the back side of the semiconductor substrate.

[0015] Furthermore, the super junction structure is composed of the super junction N-type epitaxial layer and a plurality of parallel P columns located in the super junction N-type epitaxial layer, and the P columns and the super junction N-type epitaxial layer are alternately arranged to form a super junction structure.

[0016] The present invention proposes an innovative super junction IGBT device structure, in which a Dummy gate with a small CD is added between the device gate grooves. In the etching of the gate groove with a high aspect ratio, due to the load effect, the groove etching rate of the Dummy gate with a small CD value is less than the etching rate of the device gate groove with a large CD. Therefore, the etching depth of the Dummy gate groove can be reduced by reducing the CD value of the Dummy gate. The depth of the groove of the Dummy gate does not pass through the p-body layer, so it does not affect Cgd. Its advantage is: reduce the peak voltage of Vg and Vds when the device is turned on, and realize device soft turning on. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1 to 6 It is a schematic diagram of the process steps of the device of the present invention.

[0018] 1 is the substrate, 2 is the super junction N-type epitaxial layer, 3 is the P-pillar, 4 is the epitaxial layer EPI (P-type body region), 5 is the device gate, 6 is the Dummy gate, 7 is the source region, 8 is the gate dielectric layer, 9 is the interlayer dielectric, and 10 is the contact hole. DETAILED DESCRIPTION

[0019] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0020] The present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements from beginning to end. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0021] The present invention provides a super junction IGBT device, which aims to improve the switching characteristics of the IGBT device. By adding a small-sized Dummy gate, Cgs can be increased while Cgd remains unchanged.

[0022] Main technical idea: Add a Dummy gate with a small CD value between the device gates, that is, Dummy gate CD<Gate CD. The depth of the Dummy gate does not pass through the p-body layer and will not affect the Cgd of the device; The technical effect is to reduce the peak voltages of Vg and Vds when the device is turned on, thereby achieving soft turning on of the device.

[0023] The super junction IGBT device of the present invention is as follows Figure 6As shown, a silicon substrate has a super junction N-type epitaxial layer; the super junction N-type epitaxial layer also has an epitaxial layer, the epitaxial layer has a P-type body region (P-body, formed by ion implantation) of the super junction IGBT device; the N+ source region of the super junction IGBT device is located above the P-type body region. The super junction N-type epitaxial layer has a super junction structure; the super junction structure is formed by a P / N alternating arrangement structure formed by a plurality of parallel P-type epitaxial columns located in the super junction N-type epitaxial layer and a plurality of super junction N-type epitaxial layers between the P-type epitaxial columns.

[0024] The epitaxial layer has the P-type body layer and N+ source region of the super junction IGBT device. The super junction IGBT device has multiple trench-type device gates. The trench of the device gate passes through the epitaxial layer, and the bottom thereof is located in the super junction N-type epitaxial layer; the trench-type Dummy gate is located between the device gates. The CD value and the trench depth of the Dummy gate are both smaller than those of the device gate. The bottom of the trench of the Dummy gate is located in the epitaxial layer, and its depth is not greater than that of the epitaxial layer; the trench of the device gate is located in the super junction N-type epitaxial layer.

[0025] The semiconductor substrate serves as the collector of the super junction IGBT device, and an electrode is led out from the back side of the semiconductor substrate.

[0026] The surface of the epitaxial layer also has an oxide layer and an interlayer dielectric layer, wherein the oxide layer is used as a gate dielectric layer inside the trench and extends to cover the surface of the epitaxial layer. A contact hole structure is provided in the interlayer dielectric layer to lead out the N+ source region.

[0027] The super junction IGBT device described in the present invention can be manufactured using the following process. The present invention only provides a feasible process method, but it does not represent the only process method.

[0028] First, a super junction N-type epitaxial layer is formed on a silicon substrate.

[0029] The super junction structure of the IGBT device is formed in the super junction N-type epitaxial layer. The super junction process can adopt a trench filling method or other formation processes. Taking the trench filling method as an example, a plurality of parallel deep trenches are etched in the super junction N-type epitaxial layer, and then a P-type epitaxial layer is filled in the deep trench to form the P column part of the super junction structure. The formed P column and the super junction N-type epitaxial layer between the P column constitute a super junction structure in which P and N are alternately arranged.

[0030] Another epitaxial layer is formed on the surface of the super junction N-type epitaxial layer, such as Figure 1The epitaxial layer mainly forms the P-body region (P-Body) and N+ source region of the IGBT device, which are formed by ion implantation.

[0031] A hard mask layer is formed on the entire epitaxial layer surface, such as a silicon oxide layer or a silicon nitride layer with a certain thickness. Figure 2 shown.

[0032] Perform photolithography and etching processes to define a device gate formation region and a dummy gate formation region of the IGBT device structure on the hard mask layer, such as Figure 3 shown.

[0033] The epitaxial layer and the super junction N-type epitaxial layer below the epitaxial layer are etched using the hard mask layer as a shield to form the groove of the device gate and the groove of the Dummy gate. In this etching step, the CD value of the groove of the Dummy gate is smaller than the CD value of the groove of the device gate. During synchronous etching, the load effect in etching is utilized. The smaller the CD value, the slower the etching rate. The depth of the groove of the device gate formed is greater than the depth of the groove of the Dummy gate. After etching is completed, the depth of the groove of the device gate reaches the super junction N-type epitaxial layer, while the depth of the groove of the Dummy gate does not exceed the thickness of the epitaxial layer, such as Figure 4 This will not affect the Cgd of the device.

[0034] Remove the hard mask layer, such as Figure 5 As shown. Ion implantation forms the P-type body region and N+ source region. Thermal oxidation forms a gate dielectric layer, such as a thermal oxide layer, and then polysilicon is filled in the trenches (including the device gate trench and the dummy gate trench) and etched back to form the device gate and a smaller dummy gate.

[0035] The process method also includes subsequent steps of depositing interlayer dielectric, etching contact holes to lead out the source, and performing back process to deposit back metal on the back of the silicon substrate to lead out the collector. Figure 6 shown.

[0036] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A process method for a super junction IGBT device structure, characterized in that: Include: Providing a semiconductor substrate, and forming a super junction N-type epitaxial layer on the semiconductor substrate; forming a super junction structure of the IGBT device in the super junction N-type epitaxial layer; forming another epitaxial layer on the surface of the super junction N-type epitaxial layer; forming a hard mask layer on the entire surface of the epitaxial layer; Performing photolithography and etching processes to define a device gate forming region and a dummy gate region of the IGBT device structure on the hard mask layer; The epitaxial layer and the super junction N-type epitaxial layer below the epitaxial layer are etched using the hard mask layer as a shield to form a trench of the device gate and a trench of the Dummy gate.

2. The process for the super junction IGBT device structure according to claim 1, characterized in that: The semiconductor substrate includes a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, and a gallium nitride substrate.

3. The process for the super junction IGBT device structure according to claim 1, characterized in that: The super junction structure includes a plurality of P columns formed in the super junction N-type epitaxial layer and a P / N alternatingly arranged super junction structure formed by the super junction N-type epitaxial layer between the plurality of P columns; the super junction structure adopts an etching and filling method, firstly etching in the super junction N-type epitaxial layer to form a plurality of parallel deep trenches, and then filling the plurality of parallel deep trenches with a P-type epitaxial layer to form P columns, forming the super junction structure with the super junction N-type epitaxial layer.

4. The process for the super junction IGBT device structure according to claim 1, characterized in that: The super junction structure adopts ion implantation method, and P type impurity ions are implanted into the super junction N type epitaxial layer to form multiple parallel P columns, which form the super junction structure with the super junction N type epitaxial layer.

5. The process for the super junction IGBT device structure according to claim 1, characterized in that: The hard mask layer is silicon oxide or silicon nitride.

6. The process for the super junction IGBT device structure according to claim 1, characterized in that: The CD value of the groove of the device gate is greater than the CD value of the groove of the dummy gate, so that during synchronous etching, due to the load effect, the depth of the groove of the device gate formed is greater than the depth of the groove of the dummy gate.

7. The process for the super junction IGBT device structure according to claim 6, characterized in that: The depth of the trench of the device gate is greater than the epitaxial layer and penetrates into the super junction N-type epitaxial layer, and the depth of the trench of the Dummy gate does not exceed the thickness of the epitaxial layer.

8. The process for the super junction IGBT device structure according to claim 1, characterized in that: The process method also includes subsequent steps, including ion implantation in the front epitaxial layer to form a P-type body region of the super junction IGBT device, and then N-type impurity ion implantation to form an N+ source region; forming a gate dielectric layer and depositing and filling polysilicon in the trench of the device gate and the trench of the Dummy gate to form the device gate and the Dummy gate; An interlayer dielectric is deposited, and a contact hole is etched to lead out the source electrode.

9. A super junction IGBT device structure, characterized in that: The super junction IGBT device comprises: A semiconductor substrate is provided with a super junction N-type epitaxial layer; an epitaxial layer is further provided on the super junction N-type epitaxial layer, and the epitaxial layer has a P-type body region of the super junction IGBT device; and a source region of the super junction IGBT device is located above the P-type body region; A super junction structure is provided in the super junction N-type epitaxial layer; The super junction IGBT device has a plurality of trench-type device gates, the trenches of the device gates pass through the epitaxial layer, and the bottoms thereof are located in the super junction N-type epitaxial layer; The super junction IGBT device also has a trench-type Dummy gate; the CD value of the Dummy gate is smaller than the CD value of the device gate, and the bottom of the trench of the Dummy gate is located in the epitaxial layer, and its depth is not greater than the epitaxial layer; The Dummy gate is located between the device gates; The semiconductor substrate serves as the collector of the super junction IGBT device, and an electrode is led out from the back side of the semiconductor substrate.

10. The super junction IGBT device structure according to claim 9, characterized in that: The super junction structure is composed of the super junction N-type epitaxial layer and a plurality of parallel P columns located in the super junction N-type epitaxial layer. The P columns and the super junction N-type epitaxial layer are alternately arranged to form a super junction structure.

11. The super junction IGBT device structure according to claim 9, characterized in that: In the super junction IGBT device, the Dummy gate with a smaller CD size can reduce the peak voltages of Vg and Vds when the device is turned on, thereby achieving soft turning on of the device.

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