Test method and device and storage medium
By using multiple reference current gears in wafer testing to determine the critical current value and safe current window area of the differential chip, the problems of low test efficiency and high misjudgment rate are solved, and the efficiency and accuracy of wafer testing are improved. Ensure that more chips are correctly judged to be valid.
Patent Information
- Application Number
- CN202411285730.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2024-12-27
AI Technical Summary
During wafer testing, the test efficiency is low and the misjudgment rate is high, resulting in chips with good performance being wrongly judged as invalid due to overly strict testing methods.
The differential chip is tested through multiple reference current gears to determine the critical current value and safe current window area, and then the effectiveness of the differential chip is judged, which is different from the traditional single-ended testing method.
Improve testing efficiency and flexibility, reduce chip overkill caused by testing methods, improve the yield of wafer testing, and ensure that the reliability performance chips are not wrongly judged as invalid.
Smart Images
Figure CN119208174A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of wafer testing technology, and in particular to a testing method, device and storage medium. Background Art
[0002] During the wafer testing process, baking tests are often required. The main purpose is to improve the quality, reliability and performance of the wafer to ensure that the wafer and the chips on it can meet the expected performance standards in subsequent manufacturing and use. Baking can remove moisture from the surface of the wafer, improve the stability of electrical performance, and repair or regenerate the damaged oxide layer to ensure the electrical performance and stability of the components. By exposing possible problems during the baking process, manufacturers can solve potential defects before the wafer leaves the manufacturing plant, thereby reducing the failure rate in subsequent processes. After undergoing strict baking temperatures and a certain baking time, storage products often encounter changes in the state of some stored data. In the wafer test results, chips with good performance pass the test and need to be retained, and chips with poor performance fail the test and need to be discarded. However, there are still chips with good performance in the test results that fail to pass the test due to problems such as the test method. Overly strict test methods are the key factor leading to the above problems. Summary of the invention
[0003] In view of this, the present application provides a testing method, device and storage medium to solve the technical problems of low wafer testing efficiency and misjudgment.
[0004] Specifically, the technical solution of the present invention is as follows:
[0005] A testing method for testing the effectiveness of a differential chip, comprising: performing a functional test on a wafer based on a reference current, the wafer comprising a plurality of differential chips, wherein the reference current comprises a plurality of reference current gears; determining a critical current value of the differential chip based on the test result; determining a safe current window area based on the critical current value and a preset reliable period; and determining the effectiveness of the differential chip based on the critical current value and the safe current window area.
[0006] Optionally, the differential chip includes multiple memory cell pairs, the memory cell pairs include a first memory cell and a second memory cell, the first memory cell is used to store data state "1", and the second memory cell is used to store data state "0"; performing current testing on the wafer based on a reference current includes: testing multiple first memory cells or multiple second memory cells in the differential chip based on the reference current.
[0007] Optionally, determining the critical current value of the memory cell pair based on the test result includes: determining the first critical current value based on the data state change of the first memory cell; or determining the second critical current value based on the data state change of the second memory cell;
[0008] The absolute value of the first critical current value is greater than the absolute value of the second critical current value.
[0009] Optionally, based on the data state change of the first storage unit, a first critical current value is determined, including: when a test result of a reference current of a first current position determines that there is a data state change in the first storage unit, and a test result of a reference current of a second current position determines that there is no data state change in the first storage unit, determining the reference current of the second current position to be a first critical current, wherein the first current position and the second current position are adjacent.
[0010] Optionally, based on the data state change of the second storage unit, a second critical current value is determined, including: when the test result of the reference current of the third current position determines that there is a change in the data state stored in the second storage unit, and the test result of the reference current of the fourth current position determines that there is no change in the data state stored in the second storage unit, the reference current of the fourth current position is determined to be the second critical current, wherein the third current position and the fourth current position are adjacent.
[0011] Optionally, the preset reliable cycle is determined based on the number of times the differential chip is erased or written or the performance change of the differential chip after baking.
[0012] Optionally, the validity of the differential chip is determined based on the critical current value and the safety current window area, including: determining a test current based on the critical current value and the safety current window area; testing the differential chip based on the test current; determining that the differential chip is invalid when the state of stored data in the differential chip changes; and determining that the differential chip is valid when the state of stored data in the differential chip does not change.
[0013] In a second aspect, a chip processing method is provided, comprising: baking the manufactured differential chip; and testing the baked differential chip using the testing method of the first aspect.
[0014] In a third aspect, a computer device / equipment / system is provided, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the testing method of the first aspect.
[0015] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program / instruction is stored, and when the computer program / instruction is executed by a processor, the steps of the testing method of the first aspect are implemented.
[0016] Compared with the prior art, the present invention has at least one of the following beneficial effects:
[0017] 1. This application utilizes the differential characteristics of the differential chip to be tested, tests multiple differential chips on a wafer through a reference current, determines the critical current value of the differential chip based on the test results to determine the safe current window area, and then tests the effectiveness of the differential chip. This is different from the traditional single-ended test judgment method of performing reference current tests on chips one by one. The judgment method of using an external reference current for test comparison improves test efficiency and test flexibility.
[0018] 2. This application uses reference currents at different current levels, combined with actual test processes and chip applications, to determine the safe current window area and then conduct effectiveness analysis, which to a certain extent avoids excessive damage to chips due to problems with the test method, resulting in differential chips that meet reliability performance being determined to be invalid, thereby improving wafer test yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The preferred implementation modes will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present invention.
[0020] Figure 1 A schematic diagram of a single-ended card control test process provided in some embodiments of the present application is shown;
[0021] Figure 2 An example flow chart of a testing method provided in some embodiments of the present application is shown;
[0022] Figure 3 A differential chip storage unit distribution diagram provided in some embodiments of the present application is shown;
[0023] Figure 4 A flow chart of a method for determining the validity of a differential chip provided in some embodiments of the present application is shown. DETAILED DESCRIPTION
[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.
[0025] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".
[0026] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0027] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0028] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0029] In the process of wafer testing, baking aging is often required. The main purpose of baking aging is to improve the performance, stability and reliability of electronic components (usually chips or wafers) and accelerate the deterioration of data retention by heat treating the samples before testing. This process may involve the use of high temperature to drive away moisture, repair damaged oxide layers, remove organic matter and accelerate deterioration of data retention, etc., to ensure that the components can achieve the expected performance indicators during the testing phase and subsequent practical applications. In the wafer testing process of memory, there are generally process differences or drifts that cause different threshold voltage distributions in the devices contained in the wafer. In the chip manufacturing process, in order to improve the efficiency of chip batch manufacturing and improve the efficiency of performance testing after chip manufacturing, wafers are first manufactured and then cut. When manufacturing memory chips, there are multiple chips with differential structures for storing data on the wafer. The differential chip includes multiple memory cell pairs, each of which can store data state "1" or data state "0", thereby realizing the storage of complete data. Two adjacent storage cells jointly maintain 1 bit of data. For example, two adjacent storage cells are in two storage states. The storage data state "1" indicates that a storage cell pair of the differential chip is programmed or erased, and the storage data state "0" indicates that a storage cell pair of the differential chip is erased or programmed. The storage data state corresponding to erasure and programming is just a definition, and can also be defined in reverse. When erasing or programming, from a physical perspective, the differential chip is powered on. For example, when the threshold voltage for erasure is reached, the storage cell pair of the differential chip is in the erased state, and when the threshold voltage for programming is reached, the storage cell pair of the differential chip is in the programmed state.
[0030] In the prior art, after the wafer baking test, the determination of whether the chip data retention fails is often tested by a single-ended card control method. Figure 1, which shows a schematic diagram of the single-ended card control test process provided in some embodiments of the present application, using the sensing amplifiers SA1 and SA2 to test the two storage cells in a storage cell pair respectively, VTE is the threshold voltage when the differential chip in the wafer is in the erased state, VTP is the threshold voltage when the differential chip is in the programmed state, the above difference exists in a wafer, and the distribution of VTP or VTE corresponding to the differential chip of the wafer is presented in the test results. Regardless of the state of the amplifier being erased or programmed, VT is in the form of VTE or VTP, and after a fixed voltage is applied to the gate, the current of the storage cell under the voltage threshold is compared with the preset reference current IREF. For example, when the current of the storage cell is greater than the reference current, it means that the storage cell pair is in the programmed state at this time, and the readout is 0; when the current of the storage cell is less than the reference current, it means that the storage cell pair is in the erased state, and the readout is 1, but as long as one storage cell fails, the storage cell pair is judged to be failed. The above test process has low test efficiency, and because the memory cell is tested individually, the setting of testing through the reference current IREF has certain limitations, and it is easy to test and determine that the chip that should be identified as reliable is an invalid chip. Therefore, the present application provides a test method to solve the problem of high chip failure rate caused by excessive card control during differential chip testing.
[0031] In some embodiments of this application, please refer to Figure 2 , which shows an example flow chart of a testing method provided by some embodiments of the present application, which is used to test the effectiveness of a differential chip, and at least includes the steps of:
[0032] S210, performing a functional test on a wafer based on a reference current, where the wafer includes a plurality of differential chips, and the reference current includes a plurality of reference current gears;
[0033] S220, determining a critical current value of the differential chip based on the test result;
[0034] S230, determining a safe current window region based on a critical current value and a preset reliable period;
[0035] S240 , determining the validity of the differential chip based on the critical current value and the safe current window area.
[0036] Specifically, in the process of functional testing the wafer by using a reference current, the reference current includes multiple reference current gears, the wafer includes multiple differential chips, the reference current of multiple reference current gears can test one or more differential chips multiple times, and the reference current gears of the reference current selected between different differential chips can be the same or different. For example, the first reference current gear of the reference current is used to test multiple differential chips on the wafer at the same time, and the reference currents of multiple differential chips are the same, or the first reference current gear and the second reference current gear of the reference current are used to test multiple differential chips on the wafer, and the reference currents passed by the differential chips may be the same or different. When the differential chip is storing data, the data state thereof needs to remain unchanged after programming or erasing operations to ensure the reliability of data storage. For example, when the differential chip is tested using the current gear of the preset reference current, the data state on it changes, indicating that the performance of the differential chip is unreliable, and it is confirmed to be a failed chip; when the data state on it does not change, it means that the performance of the differential chip is reliable, and it is confirmed to be a valid chip. Therefore, the wafer can be tested for current multiple times through multiple reference current gears to find the current position where all differential chips are determined to be valid, and the current is determined as the critical current value to determine a reasonable safe current window area. The differential chip that stores data may age during continuous use by the user. When it ages to a certain extent, it may cause unreliability of the data stored on it, such as the state of storing data "1" changes to the state of storing data "0", resulting in data errors and affecting user information security. Therefore, when manufacturing differential chips, it is necessary to design the service life of the differential chip according to the manufacturing process, materials, and usage requirements, in order to pursue a longer service life and a more reliable technical effect during use. Therefore, aging tests, such as baking tests, current and voltage tests, and actual service life big data analysis, can be used to find the limit of the service life of the differential chip and the attenuation current window limit. Through the above method, combined with the critical current value, the safe current window area of the differential chip is determined to ensure that the differential chip has a reliable margin when data offset occurs during the use cycle. For example, when the current range of 1 microampere to 5 microamperes is the safe current window area, even if the differential chip offsets due to product aging and the current passing through the differential chip becomes 4 microamperes, data can still be stored reliably. Therefore, in addition to determining the critical current value and the safe current window area, it is also necessary to determine whether the safe current window area is appropriate. If the reference current in the determined safe current window area causes the differential chip to fail the test, it means that the differential chip is unreliable and is determined to be a failed chip.
[0037] In some embodiments of the present disclosure, the differential chip includes multiple memory cell pairs, the memory cell pairs include a first memory cell and a second memory cell, the first memory cell is used to store data state "1", and the second memory cell is used to store data state "0"; current testing is performed on the wafer based on a reference current, including: testing multiple first memory cells or multiple second memory cells in the differential chip based on the reference current.
[0038] During the wafer testing process, the differential chip includes a plurality of first storage units and a plurality of second storage units at the same time. Figure 3 , which shows a differential chip memory cell distribution diagram provided in some embodiments of the present application. In order to improve the test efficiency, a reference current may be used to perform a current test on a plurality of first memory cells or a plurality of second memory cells. Figure 3 A plurality of first storage units constitute a first storage unit set C1, a plurality of second storage units constitute a second storage unit set C2, Figure 3 The distribution formation is only for illustration, and can be expressed as a waveform, a scatter plot, or a bar chart. When multiple storage units effectively store data, different threshold voltages may exist due to differences in manufacturing processes and materials, thus forming two distributions of the first storage unit set C1 and the second storage unit set C2. However, in general, the distribution of storage units of the same type is relatively concentrated, so continuous progressive testing can be performed by reasonably setting the reference current gear of the reference current. The current value difference of different reference current gears can be the same or different, and is set according to specific test requirements. For example, the current value of the first gear is 20 microamperes, the current value of the second gear is 19 microamperes, and the current value of the third gear is 18 microamperes, and the current difference between adjacent gears is the same, or the current value of the fourth gear is 15 microamperes, which is different from the current difference of other adjacent gears.
[0039] In some embodiments of the present disclosure, step S220 determines the critical current value of the storage cell pair based on the test results, including: determining a first critical current value based on a change in the data state of the first storage cell; or determining a second critical current value based on a change in the data state of the second storage cell; wherein the absolute value of the first critical current value is greater than the absolute value of the second critical current value.
[0040] Continue to refer Figure 3, the first storage unit can store the data state "1", and the second storage unit can store the data state "0". For example, when the reference current is used to test the first storage unit set C1, the distribution of the first storage unit set C1 is tested in a continuously progressive form. According to the preset reference current level, when the first reference current a1 determines that the data state of the first storage unit in the differential chip has changed ("1" changes to "0"); the second reference current a2 determines that the data state of the first storage unit in the differential chip has not changed ("1" remains unchanged), the second reference current a2 can be determined to be the first critical current value, wherein the first reference current a1 is greater than the second reference current a2. Alternatively, when the reference current is used to test the second storage unit set C2, the distribution of the second storage unit set C2 is tested in a continuously progressive form. According to the preset reference current gear, when the third reference current b1 determines that the data state of the first storage unit in the differential chip has changed ("0" changes to "1"); when the fourth reference current b2 determines that the data state of the second storage unit in the differential chip has changed ("0" remains unchanged), the fourth reference current b2 can be determined to be the second critical current value, wherein the third reference current b1 is less than the fourth reference current b2. Since the first storage unit stores the data state "1" and the second storage unit stores the data state "0", the current value required for programming or erasing the first storage unit is greater than that of the second storage unit. Therefore, the current of the first critical current value is larger, and the test is performed using the reference current of the high gear, and the current of the second critical current value is smaller, and the test is performed using the reference current of the low gear.
[0041] In some embodiments of the present disclosure, the preset reliable cycle is determined based on the number of times the differential chip is erased and written or the performance change of the differential chip after baking. During the use of the differential chip after manufacturing, since data needs to be stored on it, and the user needs to continuously erase or write in the differential chip to complete data processing, the continuous erasing and writing process will affect the service life of the differential chip, causing the differential current window to change and attenuate. For example, if the differential chip can maintain valid data storage for 100,000 times, the data at the 100,001st erase or write may be recorded as "0" instead of "1", affecting normal use. After the manufacturer produces the differential chip, it can determine a more reliable erase and write life range based on the actual user usage through big data analysis. For example, the user manual often defines the life times and years of the differential chip, and the differential chip manufactured by the manufacturer needs to meet and exceed the above times and years. During manufacturing, the offset of the differential chip at the end of the use cycle is determined based on this interval, and the current that can still maintain the storage validity of the differential chip after the offset is determined to help determine the endpoint current value of the safe current window area corresponding to the critical current value in the safe current window area. For example, continue to refer to Figure 3 , after determining the first critical current a2, determine the endpoint current value m1 of the safe current window area based on the above method to form a safe current window area S1. At the same time, after the differential chip has undergone aging test processes such as baking, it can simulate the attenuation phenomenon of the differential chip caused by the above actual use, and speed up the above process, such as the change of the current window in the performance change after baking, so that it is easier to determine the endpoint current value of the safe current window area. For example, the current value of the first critical current a2 is 10 microamperes, and the current interval is set to 4 microamperes based on the preset reliable cycle. Combined with the first critical current value a2, the safe current window area S1 is determined to be 10-6 microamperes. Continue to refer to Figure 3 After determining the second critical current b2, the endpoint current value m2 of the safe current window region is determined based on the above method to form the safe current window region S2. For example, if the current value of the second critical current b2 is 1 microampere, the current interval is set to 3 microamperes based on the preset reliable cycle, and combined with the second critical current value b2, the safe current window region S2 is determined to be 1-4 microamperes.
[0042] In some embodiments of the present disclosure, reference Figure 4 , which shows a flow chart of a method for determining the validity of a differential chip provided in some embodiments of the present application. It at least includes the steps of:
[0043] S410: Determine a test current based on a critical current value and a safe current window area;
[0044] S420: testing the differential chip based on the test current; when the state of the stored data in the differential chip changes, determining that the differential chip is invalid; when the state of the stored data in the differential chip does not change, determining that the differential chip is valid.
[0045] When a valid differential chip is tested by a current in the safe current window area, if the storage data state of the differential chip does not change, it means that the differential chip is a valid chip. Therefore, the test current is determined based on the critical current value and the safe current window area, the current value of the test current is determined in the safe current window area, and the differential chip is tested using the test current to determine whether the differential chip is a valid chip. Compared with the method in which the single-ended card control requires that the storage unit storing the data state "1" and the storage unit storing the data state "0" all meet the requirements before determining that the differential chip is valid, the above determination method only requires the storage unit storing the data state "1" or the storage unit storing the data state "0" to pass the test to determine that the differential chip has passed the test, which to a certain extent avoids the situation in which the chip is overkilled due to problems with the test method, so that the differential chip that meets the reliability performance is determined to be invalid, thereby improving the wafer test yield.
[0046] Based on the same technical concept, the present application also provides a chip processing method, including: baking the manufactured differential chip; and testing the baked differential chip using the testing method provided in the above embodiment.
[0047] Based on the same technical concept, the present application also provides a computer device / equipment / system, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the testing method of the first aspect.
[0048] Based on the same technical concept, the present application also provides a computer-readable storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the testing method of the first aspect are implemented.
[0049] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A testing method, characterized in that: Used to test the effectiveness of differential chips, including: Performing a functional test on a wafer based on a reference current, wherein the wafer includes a plurality of differential chips, wherein the reference current includes a plurality of reference current gears; Determining a critical current value of the differential chip based on the test result; Determine a safe current window region based on the critical current value and a preset reliable period; The validity of the differential chip is determined based on the critical current value and the safe current window area.
2. The testing method according to claim 1, characterized in that: The differential chip includes a plurality of memory cell pairs, wherein the memory cell pairs include a first memory cell and a second memory cell, wherein the first memory cell is used to store a data state "1", and the second memory cell is used to store a data state "0"; The functional test of the wafer based on the reference current includes: A plurality of the first storage cells or a plurality of the second storage cells in the differential chip are tested based on the reference current.
3. The testing method according to claim 2, characterized in that: The step of determining the critical current value of the memory cell pair based on the test result includes: determining a first critical current value based on a data state change of the first storage unit; or, determining a second critical current value based on a data state change of the second storage unit; Wherein, the absolute value of the first critical current value is greater than the absolute value of the second critical current value.
4. The testing method according to claim 3, characterized in that: The determining of a first critical current value based on a data state change of the first storage unit includes: When the test result of the reference current of the first current level determines that there is a change in the state of the data stored in the first storage unit, and the test result of the reference current of the second current level determines that there is no change in the state of the data stored in the first storage unit, the reference current of the second current level is determined to be the first critical current, wherein the first current level and the second current level are adjacent.
5. The testing method according to claim 3, characterized in that: The determining of the second critical current value based on the data state change of the second storage unit includes: When the test result of the reference current of the third current gear determines that there is a change in the state of the data stored in the second storage unit, and the test result of the reference current of the fourth current gear determines that there is no change in the state of the data stored in the second storage unit, the reference current of the fourth current gear is determined to be the second critical current, wherein the third current gear and the fourth current gear are adjacent.
6. The testing method according to any one of claims 1 to 5, characterized in that: The preset reliable period is determined based on the number of times the differential chip is erased or written or the performance change of the differential chip after baking.
7. The testing method according to any one of claims 1 to 5, characterized in that: The determining the validity of the differential chip based on the critical current value and the safe current window area includes: Determining a test current based on the critical current value and the safe current window area; testing the differential chip based on the test current; When the state of the stored data in the differential chip changes, determining that the differential chip is invalid; When the state of the stored data in the differential chip does not change, it is determined that the differential chip is valid.
8. A chip processing method, characterized in that: include: Baking the completed differential chip; The test method according to any one of claims 1 to 7 tests the baked differential chip.
9. A computer device / equipment / system comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the testing method according to any one of claims 1 to 7.
10. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the testing method according to any one of claims 1 to 7 are implemented.