Semiconductor package

Abstract

There is provided a semiconductor package including: a package substrate; a redistribution structure including a single-layer insulating layer over the package substrate and a plurality of horizontal redistribution structures embedded in the insulating layer and arranged side by side in a first horizontal direction parallel to an upper surface of the package substrate and in a second horizontal direction perpendicular to the first horizontal direction; an external connection terminal disposed below the redistribution structure; and a semiconductor chip disposed on the redistribution structure and including a chip body and a chip connection terminal disposed below the chip body; wherein each of the plurality of horizontal redistribution structures includes a via hole passing through the insulating layer, and a trace pattern integrally formed with the via hole, and inclined and elongated with respect to the first horizontal direction and the second horizontal direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2021-0082885 filed in the Korean Intellectual Property Office on June 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor package, and more particularly, to a semiconductor package including a redistribution structure. Background Art

[0004] With the development of the electronics industry and the needs of users, electronic devices have become smaller and lighter. As electronic devices become smaller and lighter, semiconductor packages used in electronic devices must also become smaller and lighter, while having high reliability, high performance, and large capacity. In addition, when the semiconductor package has high performance and high capacity, the power consumption of the semiconductor package also increases. Therefore, there is an increasing demand for semiconductor packages having a structure that responds to the size and performance of the semiconductor package and stably supplies power to the semiconductor package. Summary of the invention

[0005] Aspects of the present disclosure provide a semiconductor package capable of reducing process costs and easily controlling warpage.

[0006] According to one aspect of the present disclosure, a semiconductor package is provided, comprising: a packaging substrate; a redistribution structure comprising: an insulating layer disposed on a first side of the packaging substrate; a plurality of horizontal redistribution structures disposed in the insulating layer and arranged adjacent to each other in a first horizontal direction and a second horizontal direction, the first horizontal direction and the second horizontal direction being parallel to an upper surface of the packaging substrate, and the second horizontal direction being perpendicular to the first horizontal direction; an external connection terminal disposed on a first side of the redistribution structure; and a semiconductor chip disposed on the redistribution structure, the semiconductor chip comprising a chip body and a chip connection terminal disposed on the first side of the chip body; wherein each of the plurality of horizontal redistribution structures comprises: a via passing through the insulating layer; a tracing pattern formed integrally with the via and extending at an angle to the first horizontal direction and the second horizontal direction; a first bonding pad disposed on the insulating layer, formed integrally with the via and formed at a first position on the tracing pattern; and a second bonding pad formed at a second position on the tracing pattern different from the first position and bonded to the chip connection terminal.

[0007] According to another aspect of the present disclosure, there is provided a semiconductor package, comprising: a package substrate; a redistribution structure, comprising: an insulating layer, disposed on a first side of the package substrate; a plurality of horizontal redistribution structures, disposed in the insulating layer and arranged adjacent to each other in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of vertical redistribution structures; and an external connection terminal, disposed on a first side of the redistribution structure; a first semiconductor chip, disposed on the redistribution structure, the semiconductor chip comprising a first chip body, and a first chip connection terminal disposed on a first side of the first chip body; and a second semiconductor chip, disposed in the first horizontal direction adjacent to the first semiconductor chip. The chips are separated from each other and include a second chip body and a second chip connection terminal arranged on a first side of the second chip body; wherein the plurality of vertical redistribution structures completely overlap with the first semiconductor chip in a vertical direction, and wherein each of the plurality of horizontal redistribution structures includes: a via passing through the insulating layer; a tracing pattern, which is integrally formed with the via and extends at an angle to the first horizontal direction and the second horizontal direction; a first bonding pad, which is arranged on the insulating layer, integrally formed with the via and formed at a first position on the tracing pattern; and a second bonding pad, which is formed at a second position on the tracing pattern different from the first position and is bonded to the second chip connection terminal.

[0008] According to another aspect of the present disclosure, there is provided a semiconductor package, comprising: a package substrate; a redistribution structure comprising: an insulating layer disposed on a first side of the package substrate; a plurality of horizontal redistribution structures disposed in the insulating layer and arranged side by side in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of vertical redistribution structures; external connection terminals disposed below the redistribution structures; a first semiconductor chip disposed on the redistribution structures, the semiconductor chip comprising a first chip body and a first chip connection terminal disposed on a first side of the first chip body; and a second semiconductor chip spaced apart from the first semiconductor chip in the first horizontal direction and comprising a second chip body and a second chip connection terminal disposed on a first side of the first chip body. A second chip connection terminal is arranged on a first side of the second chip body; wherein the plurality of horizontal redistribution structures further include: a first horizontal redistribution structure, overlapping with a vertex of the second semiconductor chip in a plan view, and extending at a first angle relative to a second horizontal direction; a second horizontal redistribution structure, spaced apart from the first horizontal redistribution structure in the first horizontal direction, and extending at a second angle different from the first angle relative to the second horizontal direction; and a third horizontal redistribution structure, spaced apart from the first horizontal redistribution structure in the second horizontal direction, and extending at a third angle different from the first angle relative to the second horizontal direction, wherein the plurality of vertical redistribution structures completely overlap with the first semiconductor chip in the vertical direction.

[0009] According to another aspect of the present disclosure, a method for manufacturing a semiconductor package is provided, the method comprising: forming an insulating layer on an adhesive film attached to a carrier substrate, and patterning the insulating layer to form a plurality of holes; applying a seed layer on the plurality of holes; forming a plurality of reference patterns between the plurality of holes on the insulating layer; filling the spaces between the plurality of reference patterns and the plurality of holes with a metal material to form a plurality of horizontal redistribution structures and a plurality of vertical redistribution structures; and after removing the plurality of reference patterns, bonding a first chip connection terminal of a first semiconductor chip to the plurality of vertical redistribution structures, and bonding a second chip connection terminal of a second semiconductor chip to the plurality of horizontal redistribution structures; wherein each of the plurality of horizontal redistribution structures comprises: a via passing through the insulating layer; a tracing pattern, formed integrally with the via and extending at an angle to a first horizontal direction and a second horizontal direction; a first bonding pad, disposed on the insulating layer, formed integrally with the via and formed at a first position on the tracing pattern; and a second bonding pad, formed at a second position on the tracing pattern different from the first position and bonded to the second chip connection terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A is a plan view of a redistribution structure of a semiconductor package according to an embodiment;

[0012] Figure 1B yes Figure 1A An enlarged view of part P1;

[0013] Figure 1C is along Figure 1A A cross-sectional view taken along line AA';

[0014] Figure 1D is along Figure 1A A cross-sectional view taken along line BB';

[0015] Figure 2A is a plan view of a redistribution structure of a semiconductor package according to an embodiment;

[0016] Figure 2B yes Figure 2A An enlarged view of part P2;

[0017] Figure 2C is along Figure 2A A cross-sectional view taken along line CC';

[0018] Figure 3A is a plan view of a redistribution structure of a semiconductor package according to an embodiment;

[0019] Figure 3Byes Figure 3A An enlarged view of part P3;

[0020] Figure 3C is along Figure 3A A cross-sectional view taken along line D-D';

[0021] Figure 4A is a plan view of a redistribution structure of a semiconductor package according to an embodiment;

[0022] Figure 4B is along Figure 4A A cross-sectional view taken along line EE';

[0023] Figure 5A and Figure 5B is a cross-sectional view of a semiconductor package according to an embodiment;

[0024] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor package according to an embodiment; and

[0025] Figures 7 to 16 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0027] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the order of operations described herein is merely an example and is not limited to those order of operations set forth herein, but can be significantly changed after understanding the disclosure of the present application, except for operations that must be performed in a certain order. In addition, for greater clarity and brevity, the description of features known after understanding the disclosure of the present application may be omitted.

[0028] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0029] Throughout the specification, when a component is described as being "connected to" or "coupled to" another component, it may be directly "connected to" or "coupled to" the other component, or there may be one or more other components intervening. Conversely, when an element is described as being "directly connected to" or "directly coupled to" another element, there may be no other elements intervening. Likewise, similar expressions such as "between" and "directly between" and "adjacent to" and "immediately adjacent to" should also be understood in this same manner. As used herein, the term "and / or" includes any one of the items listed in the association and any combination of any two or more.

[0030] Although terms such as "first", "second", and "third" may be used herein to describe various components, assemblies, regions, layers, or portions, these components, assemblies, regions, layers, or portions should not be limited by these terms. Instead, these terms are only used to distinguish one component, component, region, layer, or portion from another component, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first component, component, region, layer, or portion mentioned in the examples may also be referred to as the second component, component, region, layer, or portion.

[0031] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include plural forms. The terms "comprise", "include" and "have" indicate the presence of the features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by a person of ordinary skill in the art to which the present disclosure belongs, and as understood based on the understanding of the disclosure of the present application. Terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the disclosure of the relevant technology and the present application, and should not be interpreted as ideal or overly formal meanings, unless explicitly defined as such herein. In this article, the use of the term "may" for an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) indicates that there is at least one example or embodiment in which such a feature is included or implemented, and all examples are not limited thereto.

[0033] However, the present disclosure is not necessarily configured to be limited to the embodiments described below, and may be implemented in various other forms. The following embodiments are not provided to fully form the present disclosure, but to fully convey the scope of the present disclosure to those skilled in the art.

[0034] Figure 1A is a plan view of a redistribution structure of a semiconductor package according to an embodiment, and Figure 1B yes Figure 1A An enlarged view of portion P1. Figure 1C is along Figure 1A A cross-sectional view taken along line AA', and Figure 1D is along Figure 1A A cross-sectional view taken along line BB'.

[0035] refer to Figures 1A to 1D According to the embodiment, the semiconductor package 10 may include a package substrate 101, a redistribution structure 110 located above the package substrate 101, a first semiconductor chip 120 disposed on the redistribution structure 110, and a second semiconductor chip 130 disposed on the redistribution structure 110. The second semiconductor chip 130 is spaced apart from the first semiconductor chip 120 in a first horizontal direction (X direction). The semiconductor package 10 may include a plurality of external connection terminals. The plurality of external connection terminals may include a plurality of first external connection terminals 140 disposed on the lower surface of the redistribution structure 110, and a plurality of second external connection terminals 160 disposed on the lower surface of the package substrate 101.

[0036] According to an embodiment, the package substrate 101 may be in the form of a flat plate or a panel. The package substrate 101 may include an upper surface and a lower surface opposite to the upper surface. Each of the upper surface and the lower surface of the package substrate 101 may be flat. However, the present disclosure is not limited thereto. Hereinafter, each of a first horizontal direction (X direction) and a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction) may be defined as a direction parallel to the upper surface of the package substrate 101, and a vertical direction (Z direction) may be defined as a direction perpendicular to the upper surface of the package substrate 101. The package substrate 101 may include, but is not limited to, a printed circuit board (PCB).

[0037] The second external connection terminal 160 may be arranged on the lower surface of the package substrate 101. The second external connection terminal 160 may be configured to electrically connect the package substrate 101 and physically connect it to an external device. The second external connection terminal 160 may have a solder ball, a conductive bump, or a flip chip connection structure with a grid array (e.g., a pin grid array, a ball grid array, or a contact grid array). However, the present disclosure is not limited thereto, and therefore, the second external connection terminal 160 may include other types of connections.

[0038] According to an embodiment, the redistribution structure 110 may include an insulating layer 111, a plurality of vertical redistribution structures 115 disposed in the insulating layer 111 and arranged side by side in a first horizontal direction (X direction) and a second horizontal direction (Y direction), a plurality of horizontal redistribution structures 117, and a central redistribution structure 118 disposed in the middle of the plurality of horizontal redistribution structures 117 in the second horizontal direction (Y direction). According to an embodiment, the insulating layer 111 may be a single-layer structure. For example, the insulating layer 111 may be a single-layer insulating layer. A plurality of vertical redistribution structures 115 may be embedded in the insulating layer 111. For example, a plurality of vertical redistribution structures 115 may be arranged adjacent to each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). According to an embodiment, the first fan-in region FI1a may be disposed in the first region of the redistribution structure 110, and the second fan-in region FI2a may be disposed in the second region of the redistribution structure 110. In a plan view, the first region and the second region may be adjacent to each other in the first horizontal direction (X direction). For example, as Figure 1AAs shown, one side of the redistribution structure 110 is a first fan-in area FI1a, and the other side opposite to the side is a second fan-in area FI2a, and these sides are arranged in a first horizontal direction (X direction) in a plan view. In the first fan-in area FI1a of the redistribution structure 110, a plurality of vertical redistribution structures 115 can be arranged side by side in the first horizontal direction (X direction) and the second horizontal direction (Y direction), and in the second fan-in area FI2a of the redistribution structure 110, a plurality of horizontal redistribution structures 117 can be arranged side by side in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Each of the plurality of horizontal redistribution structures 117 may include a horizontal redistribution via 1171, a tracing pattern 1175, a first bonding pad 1173, and a second bonding pad 1177. The horizontal redistribution via 1171 may pass through the insulating layer 111. The tracing pattern 1175 may be formed integrally with the horizontal redistribution via 1171 and extend at an angle relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction). The first bonding pad 1173 may be disposed on the insulating layer 111, integrally formed with the horizontal redistribution via 1171, and formed at a first position on the tracing pattern 1175. The second bonding pad 1177 may be disposed at a second position on the tracing pattern 1175 and connected to the second chip connection terminal 134. For example, the second bonding pad 1177 may be bonded to the second chip connection terminal 134. For example, the first bonding pad 1173 may be disposed at one end of the tracing pattern 1175, and the second bonding pad 1177 may be disposed at the other end of the tracing pattern 1175 (e.g., opposite to the one end). Each of the vertical level of the upper surface of the first bonding pad 1173 in the vertical direction (Z direction) and the vertical level of the upper surface of the second bonding pad 1177 in the vertical direction (Z direction) may be the same as the vertical level of the upper surface of the tracer pattern 1175 in the vertical direction (Z direction). The second bonding pad 1177 may have a cylindrical shape, and the length in the vertical direction may be longer than the diameter of the second bonding pad 1177. In addition, as Figure 1D As shown, the first bonding pad 1173 may be located farther away from the center of the second semiconductor chip 130 than the second bonding pad 1177. The distance from the edge of the second semiconductor chip 130 to the first bonding pad 1173 of the horizontal redistribution structure 117 may be a distance d1. In a plan view, the first bonding pad 1173 of the horizontal redistribution structure 117 may be outside the second semiconductor chip 130. In this way, the second semiconductor chip 130 may not overlap with the first bonding pad 1173 of the horizontal redistribution structure 117. The multiple horizontal redistribution structures 117 and the multiple vertical redistribution structures 115 are described in detail below.

[0039] According to an embodiment, the semiconductor package 10 may further include a seed layer 113 disposed on a lower surface and a side surface of each vertical redistribution via 1151 of the vertical redistribution structure 115, and on a lower surface and a side surface of each horizontal redistribution via 1171 of the horizontal redistribution structure 117. For example, the seed layer is formed to cover a lower surface and a side surface of each vertical redistribution via 1151 of the vertical redistribution structure 115, and a lower surface and a side surface of each horizontal redistribution via 1171 of the horizontal redistribution structure 117. For example, the seed layer conformally covers a lower surface and a side surface of each vertical redistribution via 1151 of the vertical redistribution structure 115, and a lower surface and a side surface of each horizontal redistribution via 1171 of the horizontal redistribution structure 117. The seed layer 113 may include a titanium / copper (Ti / Cu) alloy, and may prevent a metal material of the vertical redistribution via 1151 and a metal material of the horizontal redistribution via 1171 from diffusing into the insulating layer 111 .

[0040] For example, the insulating layer 111 may include an insulating material, which may include, but is not limited to, silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or a combination thereof.

[0041] According to an embodiment, the first semiconductor chip 120 may be located in the first fan-in region FI1a on the redistribution structure 110 . The first semiconductor chip 120 may include a first chip body 121 , a first chip pad 122 , a first vertical connection conductor 123 , and a first chip connection terminal 124 .

[0042] The first chip body 121 may include an integrated circuit. The integrated circuit may be any type of integrated circuit including a memory circuit, a logic circuit, or a combination thereof. The memory circuit may include, but is not limited to, a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a flash memory circuit, an electrically erasable programmable read-only memory (EEPROM) circuit, a phase change random access memory (PRAM) circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (RRAM) circuit, or a combination thereof. The logic circuit may include, but is not limited to, a central processing unit (CPU) circuit, a graphics processing unit (GPU) circuit, a controller circuit, an application specific integrated circuit (ASIC) circuit, an application processor (AP) circuit, or a combination thereof.

[0043] The integrated circuit may include a substrate. The substrate may include a semiconductor material, for example, a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, or a combination thereof. Group IV semiconductor materials may include, but are not limited to, silicon (Si), germanium (Ge), or a combination thereof. Group III-V semiconductor materials may include, but are not limited to, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or a combination thereof. Group II-VI semiconductor materials may include, but are not limited to, zinc telluride (ZnTe), cadmium sulfide (CdS), or a combination thereof.

[0044] The first chip pad 122 may be disposed on the lower surface of the first chip body 121 along the lower surface of the first chip body 121. The first chip pad 122 may provide a connection between the first chip body 121 and the first vertical connection conductor 123. The first chip pad 122 may include a conductive material including, but not limited to, Cu, aluminum (Al), silver (Ag), gold (Au), tungsten (W), Ti, or a combination thereof.

[0045] The first vertical connecting conductor 123 can be arranged between the first chip pad 122 and the first chip connection terminal 124. The upper surface of the first vertical connecting conductor 123 can be connected to the first chip pad 122, and the lower surface of the first vertical connecting conductor 123 can be connected to the first chip connection terminal 124. For example, the upper surface of the first vertical connecting conductor 123 can be physically connected or bonded to the first chip pad 122, and the lower surface of the first vertical connecting conductor 123 can be physically connected or bonded to the first chip connection terminal 124. The first vertical connecting conductor 123 may include, for example, a conductive material such as Cu, Al, Ag, Au, W, Ti or a combination thereof. The first chip connection terminal 124 can be used to achieve self-alignment between the first vertical connecting conductor 123 and the vertical redistribution pad 1153. The first chip connection terminal 124 can be bonded to the first vertical connection conductor 123 and the vertical redistribution pad 1153 in a molten state, wherein a line passing through the center of the first vertical connection conductor 123 may not overlap with a line passing through the center of the corresponding vertical redistribution pad 1153, respectively. However, in the process of solidifying the first chip connection terminal 124 in a molten state, due to the surface tension of the first chip connection terminal 124, a line passing through the center of the vertical redistribution pad 1153 may overlap with a line passing through the center of the first vertical connection conductor 123, respectively. That is, the first chip connection terminal 124 can align the first vertical connection conductor 123 so that the center of the first vertical connection conductor 123 coincides with the center of the vertical redistribution pad 1153 without error.

[0046] According to an embodiment, the second semiconductor chip 130 may be located in the second fan-in region FI2a on the redistribution structure 110. The second semiconductor chip 130 may include a plurality of stacked chips 131, through silicon vias 132, second vertical connection conductors 133, and second chip connection terminals 134. That is, the second semiconductor chip 130 may include a high bandwidth memory (HBM).

[0047] A plurality of chips 131 may be connected to each other through silicon vias 132. The silicon vias 132 may pass through each of the plurality of chips 131. The silicon vias 132 may include at least one of a metal or a metal nitride. For example, the silicon vias 132 may include at least one of Ti, tantalum (Ta), Al, Au, Cu, nickel (Ni), W, titanium nitride (TiN), or tantalum nitride (TaN). However, the present disclosure is not limited thereto, and therefore, the silicon vias 132 may include other materials. Each of the plurality of chips 131 may include a logic semiconductor chip or a memory semiconductor chip. However, all of the plurality of chips 131 do not need to be of the same type. For example, the bottom chip among the plurality of chips 131 may be a logic semiconductor chip, and the other chips may be memory semiconductor chips. The logic semiconductor chip may include, but is not limited to, an AP, a CPU, or a controller. The memory chip may include, but is not limited to, a DRAM, SRAM, PRAM, MRAM, RRAM, a flash memory, or an EEPROM.

[0048] The second vertical connecting conductor 133 may be disposed between the lowermost chip among the plurality of chips 131 and the second chip connecting terminal 134. A lower surface of the second vertical connecting conductor 133 is bonded to the second chip connecting terminal 134. The second vertical connecting conductor 133 may include, but is not limited to, a conductive material including Cu, Al, Ag, Au, W, Ti, or a combination thereof.

[0049] According to an embodiment, the semiconductor package 10 may include a mold layer 150 on the insulating layer 111 to seal the first semiconductor chip 120, the second semiconductor chip 130, the plurality of vertical redistribution structures 115, and the plurality of horizontal redistribution structures 117. According to an embodiment, the mold layer 150 may be disposed on the side surfaces of the vertical redistribution pads 1153, the side surfaces of the tracing patterns 1175, and the upper and side surfaces of the first bonding pads 1173. For example, the mold layer 150 may cover the side surfaces of the vertical redistribution pads 1153, the side surfaces of the tracing patterns 1175, the upper and side surfaces of the first bonding pads 1173. The mold layer 150 may include, but is not limited to, a thermosetting resin, a thermoplastic resin, a UV curing resin, or a combination thereof. The mold layer 150 may include, but is not limited to, an epoxy resin, a silicone resin, or a combination thereof. The mold layer 150 may include, but is not limited to, an epoxy molding compound (EMC).

[0050] like Figure 1A and Figure 1B As shown, the plurality of horizontal redistribution structures 117 may be arranged symmetrically with respect to a center line intersecting the center of the second semiconductor chip 130 in a first horizontal direction (X direction) and a center line intersecting the center of the second semiconductor chip 130 in a second horizontal direction (Y direction). Figure 1A and Figure 1B As shown, the plurality of horizontal redistribution structures 117 may include a first horizontal redistribution structure 117a, a second horizontal redistribution structure 117b spaced apart from the first horizontal redistribution structure 117a in a first horizontal direction (X direction), a third horizontal redistribution structure 117c spaced apart from the first horizontal redistribution structure 117a in a second horizontal direction (Y direction), and a fourth horizontal redistribution structure 117d spaced apart from the third horizontal redistribution structure 117c in the first horizontal direction (X direction). In addition, the fourth horizontal redistribution structure 117d may be spaced apart from the second horizontal redistribution structure 117b in the second horizontal direction (Y direction). The first horizontal redistribution structure 117a and the second horizontal redistribution structure 117b may be arranged on one side relative to a center line intersecting with the center of the second semiconductor chip 130 in the second horizontal direction (Y direction).

[0051] According to an embodiment, a first angle θ1 at which the first horizontal redistribution structure 117a is inclined relative to the second horizontal direction (Y direction) may be different from a second angle θ2 at which the second horizontal redistribution structure 117b is inclined relative to the second horizontal direction (Y direction). Figure 1B As shown, since the first horizontal redistribution structure 117a is located further outside the second semiconductor chip 130 than the second horizontal redistribution structure 117b in a plan view, the first angle θ1 may be greater than the second angle θ2. However, the first angle θ1 is not necessarily limited thereto, and therefore, according to another embodiment, the first angle θ1 may be less than the second angle θ2.

[0052] The first horizontal redistribution structure 117a includes a first tracing pattern 1175a extending at a first angle θ1 relative to a second horizontal direction (Y direction), a first bonding pad 1173a formed at one end of the first tracing pattern 1175a and not overlapping with the second semiconductor chip 130 in a plan view, and a second bonding pad 1177a formed at the other end of the first tracing pattern 1175a opposite to the one end and overlapping with the second semiconductor chip 130.

[0053] The second horizontal redistribution structure 117b includes a second tracing pattern 1175b extending at a second angle θ2 relative to a second horizontal direction (Y direction), a first bonding pad 1173b formed at one end of the second tracing pattern 1175b and not overlapping with the second semiconductor chip 130 in a plan view, and a second bonding pad 1177b formed at the other end of the second tracing pattern 1175b opposite to the one end and overlapping with the second semiconductor chip 130.

[0054] The third horizontal redistribution structure 117c includes a third tracing pattern 1175c extending at a third angle θ3 relative to a second horizontal direction (Y direction), a first bonding pad 1173c formed at one end of the third tracing pattern 1175c and not overlapping with the second semiconductor chip 130 in a plan view, and a second bonding pad 1177c formed at the other end of the third tracing pattern 1175c opposite to the one end and overlapping with the second semiconductor chip 130.

[0055] The fourth horizontal redistribution structure 117d includes a fourth tracing pattern 1175d extending at a fourth angle θ4 with respect to the second horizontal direction (Y direction), a first bonding pad 1173d formed at one end of the fourth tracing pattern 1175d and overlapping the second semiconductor chip 130 in a plan view, and a second bonding pad 1177d formed at the other end of the fourth tracing pattern 1175d opposite to the one end and overlapping the second semiconductor chip 130. Since the fourth horizontal redistribution structure 117d is positioned closer to the inside of the second semiconductor chip 130 than to the outside in a plan view, both the first bonding pad 1173d of the fourth horizontal redistribution structure 117d and the second bonding pad 1177d of the fourth horizontal redistribution structure 117d may overlap the second semiconductor chip 130.

[0056] According to embodiments, vertical redistribution structure 115 and horizontal redistribution structure 117 may include at least one of Ti, Ta, Al, Au, Cu, Ni, W, TiN, or TaN.

[0057] According to the embodiment, even without multiple conductive patterns and multiple conductive vias, semiconductor package 10 can be redistributed with a single-layer horizontal redistribution structure 117, thereby reducing process costs. In addition, since redistribution structure 110 includes only a single-layer insulating layer, warpage can be easily controlled.

[0058] Figure 2A is a plan view of a redistribution structure of a semiconductor package according to an embodiment. Figure 2B yes Figure 2A is an enlarged view of part P2, and Figure 2C is along Figure 2A A cross-sectional view taken along line CC'.

[0059] refer to FIG. 2A to FIG. 2C , except that the arrangement of the plurality of horizontal redistribution structures 217 is Figures 1A to 1D In addition to the different arrangements of the multiple horizontal redistribution structures 117 shown, FIG. 2A to FIG. 2C The semiconductor package 11 shown is Figures 1A to 1D The semiconductor packages 10 shown are substantially the same or similar. Figures 1A to 1D Description of the mentioned component.

[0060] like Figure 2C As shown, the first bonding pad 2173 of the horizontal redistribution structure 217 can be positioned closer to the center of the second semiconductor chip 130 than the second bonding pad 2177. The distance from the edge of the second semiconductor chip 130 to the first bonding pad 2173 of the horizontal redistribution structure 217 can be a distance d2. In a plan view, the first bonding pad 2173 of the horizontal redistribution structure 217 can be inside the second semiconductor chip 130. In this way, the second semiconductor chip 130 can overlap with the first bonding pad 2173 of the horizontal redistribution structure 217. According to an embodiment, the fifth angle θ5 at which the first horizontal redistribution structure 217a is inclined relative to the second horizontal direction (Y direction) may be different from the sixth angle θ6 at which the second horizontal redistribution structure 217b is inclined relative to the second horizontal direction (Y direction). As Figure 2B As shown, since the first horizontal redistribution structure 217a is positioned outside the second semiconductor chip 130 in a plan view, the fifth angle θ5 may be greater than the sixth angle θ6. However, according to embodiments, the fifth angle θ5 is not necessarily limited thereto and may be less than the sixth angle θ6.

[0061] The first horizontal redistribution structure 217a includes a first tracing pattern 2175a extending at a fifth angle θ5 with respect to the second horizontal direction (Y direction), a first bonding pad 2173a formed at one end of the first tracing pattern 2175a and partially overlapping the second semiconductor chip 130 in a plan view, and a second bonding pad 2177a formed at the other end of the first tracing pattern 2175a opposite to the one end and overlapping the second semiconductor chip 130. However, according to an embodiment, the first tracing pattern 2175a may not completely overlap the second semiconductor chip 130 in a plan view.

[0062] The second horizontal redistribution structure 217b includes a second tracing pattern 2175b extending at a sixth angle θ6 relative to the second horizontal direction (Y direction), a first bonding pad 2173b formed at one end of the second tracing pattern 2175b and overlapping with the second semiconductor chip 130 in a plan view, and a second bonding pad 2177b formed at the other end of the second tracing pattern 2175b opposite to the one end and overlapping with the second semiconductor chip 130.

[0063] The third horizontal redistribution structure 217c includes a third tracing pattern 2175c extending at a seventh angle θ7 relative to the second horizontal direction (Y direction), a first bonding pad 2173c formed at one end of the third tracing pattern 2175c and not overlapping with the second semiconductor chip 130 in a plan view, and a second bonding pad 2177c formed at the other end of the third tracing pattern 2175c opposite to the one end and overlapping with the second semiconductor chip 130.

[0064] The fourth horizontal redistribution structure 217d includes a fourth tracing pattern 2175d extending at an eighth angle θ8 with respect to the second horizontal direction (Y direction), a first bonding pad 2173d formed at one end of the fourth tracing pattern 2175d and overlapping the second semiconductor chip 130 in a plan view, and a second bonding pad 2177d formed at the other end of the fourth tracing pattern 2175d opposite to the one end and overlapping the second semiconductor chip 130. Since the fourth horizontal redistribution structure 217d is positioned closer to the inside of the second semiconductor chip 130 than to the outside in a plan view, the first bonding pad 2173d of the fourth horizontal redistribution structure 217d and the second bonding pad 2177d of the fourth horizontal redistribution structure 217d can both overlap the second semiconductor chip 130. Figures 1A to 1D Compared with the plurality of first bonding pads 1173a, 1173b, 1173c and 1173d of the semiconductor package 11 shown in FIG. FIG. 2A to FIG. 2C More of the first bonding pads 2173a, 2173b, 2173c, and 2173d shown may overlap the second semiconductor chip 130. In addition, a distance d2 from an edge of the second semiconductor chip 130 to the first bonding pads 2173 of the horizontal redistribution structure 217 may be greater than a distance d1 from the edge of the second semiconductor chip 130 to the first bonding pads 1173 of the horizontal redistribution structure 117.

[0065] Figure 3A is a plan view of a redistribution structure of a semiconductor package according to an embodiment. Figure 3B yes Figure 3A An enlarged view of part P3, and Figure 3C is along Figure 3A A cross-sectional view taken along line D-D'.

[0066] refer to FIG. 3A to FIG. 3C , in addition to each of the plurality of horizontal redistribution structures 317 further including a third bonding pad 3179 , and the second semiconductor chip 130 further including a dummy vertical connection conductor 335 and a dummy chip connection terminal 336 , FIG. 3A to FIG. 3C The semiconductor package 12 shown is Figures 1A to 1D The semiconductor packages 10 shown are substantially the same or similar. Figures 1A to 1D Description of the mentioned component.

[0067] refer to FIG. 3A to FIG. 3C , the plurality of horizontal redistribution structures 317a, 317b, 317c, and 317d may further include third bonding pads 3179a, 3179b, 3179c, and 3179d formed on the trace patterns 3175a, 3175b, 3175c, and 3175d between the first bonding pads 3173a, 3173b, 3173c, and 3173d and the second bonding pads 3177a, 3177b, 3177c, and 3177d, respectively. In addition, the second semiconductor chip 130 may further include a dummy vertical connection conductor 335 disposed on the lowermost chip among the plurality of chips 131, a dummy chip connection terminal 336 may be connected to the dummy vertical connection conductor 335, and the third bonding pads 3179a, 3179b, 3179c, and 3179d may be bonded to the dummy chip connection terminal 336. For example, the dummy chip connection terminal 336 may be physically connected or bonded to the dummy vertical connection conductor 335, and the third bonding pads 3179a, 3179b, 3179c, and 3179d may be physically connected or bonded to the dummy chip connection terminal 336. Since the second semiconductor chip 130 further includes the dummy vertical connection conductor 335 and the dummy chip connection terminal 336, the heat dissipation effect of the second semiconductor chip 130 may be enhanced.

[0068] Figure 4A is a plan view of a redistribution structure of a semiconductor package according to an embodiment, and Figure 4B is along Figure 4A A cross-sectional view taken along line EE'.

[0069] refer to Figure 4A and Figure 4B In addition to the multiple horizontal redistribution structures 417 arranged in the first fan-in area FI1d, Figure 4A and Figure 4B The semiconductor package 13 shown is Figures 1A to 1D The semiconductor packages 10 shown are substantially the same or similar. Figures 1A to 1D Description of the mentioned component.

[0070] In the first fan-in region FI1d, a plurality of horizontal redistribution structures 417 may be arranged side by side in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Each of the plurality of horizontal redistribution structures 417 may include a tracing pattern 4175 extending from the second horizontal direction (Y direction), a first bonding pad 4173 formed at one end of the tracing pattern 4175, and a second bonding pad 4177 formed at the other end of the tracing pattern 4175 opposite to the one end and bonded to the second chip connection terminal 134. The plurality of horizontal redistribution structures 417 arranged in the first fan-in region FI1d may be substantially the same as the plurality of horizontal redistribution structures 417 arranged in the second fan-in region FI2d.

[0071] Figure 5A and Figure 5B is a cross-sectional view of a semiconductor package according to an embodiment. Figure 5A is with Figure 1C The corresponding cross-sectional view, and Figure 5B is with Figure 1D The corresponding cross-sectional view.

[0072] refer to Figure 5A and Figure 5B In addition to forming a plurality of insulating layers 511 and a plurality of conductive redistribution patterns 518 under the plurality of horizontal redistribution structures 517 and the plurality of vertical redistribution structures 515, Figure 5A and Figure 5B The semiconductor package 14 shown is Figures 1A to 1D The semiconductor packages 10 shown are substantially the same or similar. Figures 1A to 1D Description of the mentioned component.

[0073] The semiconductor package 14 may include a plurality of insulating layers 511 and a plurality of conductive redistribution patterns 518. Each of the plurality of vertical redistribution structures 515 may include a vertical redistribution via 5151 and a vertical redistribution pad 5153. Each of the plurality of conductive redistribution patterns 518 may include a conductive via pattern 5181 and a conductive layer 5183.

[0074] The conductive layer 5183 may extend in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and may be arranged at different vertical levels to form a multilayer structure. The conductive layer 5183 may be arranged on any one of the upper surface and the lower surface of each of the plurality of insulating layers 511. For example, the conductive layer 5183 may include a line pattern extending in a linear shape along one of the upper surface and the lower surface of any one of the plurality of insulating layers 511. The conductive via pattern 5181 may extend through at least one of the plurality of insulating layers 511 in a vertical direction (Z direction). The conductive via pattern 5181 may electrically connect the conductive layers 5183 arranged at different vertical levels, or electrically connect the conductive layer 5183 to the first external connection terminal 140. For example, the conductive layer 5183 and the conductive via pattern 5181 may include a metal, such as Cu, Al, W, Ti, Ta, In, molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), Ni, magnesium (Mg), rhenium (Re), beryllium (Be), Ga, ruthenium (Ru), or an alloy thereof.

[0075] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor package according to an embodiment. Fig. 6A is with Figure 1C The corresponding cross-sectional view, and Figure 6B is with Figure 1D The corresponding cross-sectional view.

[0076] refer to Fig. 6A and Figure 6B , except that the length of the plurality of horizontal redistribution structures 617 is different from the length of the plurality of vertical redistribution structures 615 in the vertical direction (Z direction), Fig. 6A and Figure 6B The semiconductor package 15 shown is Figures 1A to 1D The semiconductor packages 10 shown are substantially the same or similar. Figures 1A to 1D Description of the mentioned component.

[0077] like Fig. 6AAs shown, the length h1 of the plurality of vertical redistribution structures 615 in the vertical direction (Z direction) is longer than the length h2 of the plurality of horizontal redistribution structures 617 in the vertical direction (Z direction). However, according to an embodiment, the length h2 of the plurality of horizontal redistribution structures 617 in the vertical direction (Z direction) is not limited thereto, and may be longer than the length h1 of the plurality of vertical redistribution structures 615 in the vertical direction (Z direction). In this way, when the length of the plurality of vertical redistribution structures 615 in the vertical direction (Z direction) is different from the length of the plurality of horizontal redistribution structures 617 in the vertical direction (Z direction), it is easy to adjust the length of the first semiconductor chip 120 and the second semiconductor chip 130 in the vertical direction (Z direction). Each of the plurality of vertical redistribution structures 615 may include a vertical redistribution via 6151 and a vertical redistribution pad 6153.

[0078] Figures 7 to 16 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0079] refer to Figure 7 , the method of manufacturing a semiconductor package according to an embodiment may include: attaching an adhesive film FI to a carrier substrate CA. The adhesive film FI may include a film capable of fixing the insulating layer 111 (see Figure 8 ) etc. The adhesive film FI may include, but is not limited to, a heat-curing adhesive tape whose adhesive strength is weakened by heat treatment, or an ultraviolet-curing adhesive tape whose adhesive strength is weakened by UV irradiation.

[0080] refer to Figure 8 , the method for manufacturing a semiconductor package according to an embodiment may include: forming an insulating layer 111 on an adhesive film FI, and patterning the insulating layer 111 to form a plurality of holes H. The plurality of holes H may be spaces that are subsequently filled with a conductive material to form a vertical redistribution structure or a horizontal redistribution structure. The holes H in the insulating layer 111 in the first fan-in region FI1a may be spaces in which vertical redistribution vias 1151 (see Figure 1C ), and the hole H in the insulating layer 111 in the second fan-in area FI2a may be a space in which the horizontal redistribution via 1171 is to be formed (see Figure 1D ) space.

[0081] refer to Fig. 9, the method of manufacturing a semiconductor package according to an embodiment may include: applying a seed layer 113 to the insulating layer 111 and the plurality of holes H to cover the plurality of holes H. The seed layer 113 may be disposed on the plurality of holes H and on the upper surface of the insulating layer 111. The seed layer 113 may conformally cover the plurality of holes H and the upper surface of the insulating layer 111. The process of forming the seed layer 113 may be performed by an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or a physical vapor deposition (PVD) method. Alternatively, the seed layer 113 may be formed by a sputtering process.

[0082] refer to Fig.10 The method of manufacturing a semiconductor package according to an embodiment may include forming a plurality of reference patterns RP between the plurality of holes H on the insulating layer 111. The plurality of reference patterns RP may serve as a frame into which a metal material may be filled later.

[0083] refer to Fig.11 , the method of manufacturing a semiconductor package according to an embodiment may include filling a plurality of reference patterns RP and a space between a plurality of holes H with a metal material to form a plurality of horizontal redistribution structures 117 and a plurality of vertical redistribution structures 115. The process of forming the plurality of horizontal redistribution structures 117 and the plurality of vertical redistribution structures 115 may be performed by an electroplating process.

[0084] refer to Fig.12 and Fig.13 , the method of manufacturing a semiconductor package according to an embodiment may include: after removing the plurality of reference patterns RP, mounting the first semiconductor chip 120 and the second semiconductor chip 130 on the redistribution structure 110. In order to mount the first semiconductor chip 120 and the second semiconductor chip 130 on the redistribution structure 110, the first chip connection terminals 124 of the first semiconductor chip 120 may be bonded to the plurality of vertical redistribution structures 115, and the second chip connection terminals 134 of the second semiconductor chip 130 may be bonded to the plurality of horizontal redistribution structures 117, respectively.

[0085] refer to Fig.14 The method of manufacturing a semiconductor package according to an embodiment may include forming a mold layer 150 sealing the first semiconductor chip 120 and the second semiconductor chip 130 on the redistribution structure 110. The upper surface of the mold layer 150 may be located on the same plane as the upper surfaces of the first semiconductor chip 120 and the second semiconductor chip 130.

[0086] refer to Fig.15 and Fig.16In the method for manufacturing a semiconductor package according to an embodiment, after removing the carrier substrate CA and the adhesive film FI from the redistribution structure 110, the ring frame RF may be attached to the upper surface of the first semiconductor chip 120 and the second semiconductor chip 130 and the upper surface of the mold layer 150. One side of the ring frame RF may be coated with an adhesive material to adhere to the upper surface of the first semiconductor chip 120 and the second semiconductor chip 130 and a portion of the upper surface of the mold layer 150. After attaching the ring frame RF to the upper surface of the first semiconductor chip 120 and the second semiconductor chip 130 and the upper surface of the mold layer 150, the ring frame RF may be flipped so that the lower surface of the redistribution structure 110 faces the vertical direction (Z direction). Subsequently, the first external connection terminal 140 physically and electrically connected to the vertical redistribution via 1151 and the horizontal redistribution via 1171 of the horizontal redistribution structure 117 is attached to the lower surface of the redistribution structure 110. Subsequently, the package substrate 101 coupled to the second external connection terminal 160 may be attached to the first external connection terminal 140.

[0087] refer to Fig.16 The method for manufacturing a semiconductor package according to an embodiment may further include: flipping the ring frame RF so that the upper surfaces of the first semiconductor chip 120 and the second semiconductor chip 130 face the vertical direction (Z direction). Subsequently, the ring frame RF may be removed from the upper surfaces of the first semiconductor chip 120 and the second semiconductor chip 130 to complete the semiconductor package 10.

[0088] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Package substrate; Redistribution structure, including: an insulating layer disposed on the first side of the package substrate, and a plurality of horizontal redistribution structures disposed in the insulating layer and arranged adjacent to each other in a first horizontal direction and a second horizontal direction, the first horizontal direction and the second horizontal direction being parallel to the upper surface of the package substrate, and the second horizontal direction being perpendicular to the first horizontal direction; an external connection terminal disposed on a first side of the redistribution structure; and A semiconductor chip is arranged on the redistribution structure, wherein the semiconductor chip comprises a chip body and a chip connection terminal arranged on a first side of the chip body; Wherein, each of the plurality of horizontal redistribution structures comprises: a via hole passing through the insulating layer; a tracer pattern formed integrally with the via and extending at an angle to the first horizontal direction and the second horizontal direction; a first bonding pad disposed on the insulating layer, formed integrally with the via hole, and formed at a first position on the tracing pattern; and A second bonding pad is formed at a second position on the trace pattern that is different from the first position and is bonded to the chip connection terminal.

2. The semiconductor package according to claim 1, wherein The plurality of horizontal redistribution structures include: a first horizontal redistribution structure overlapping a vertex of the semiconductor chip in a plan view, and a second horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the first horizontal direction, Wherein, the first horizontal redistribution structure and the second horizontal redistribution structure are arranged on a first side with respect to a center line crossing a center of the semiconductor package in the second horizontal direction.

3. The semiconductor package according to claim 2, wherein: A first angle at which the first horizontal redistribution structure extends relative to the second horizontal direction is different from a second angle at which the second horizontal redistribution structure extends relative to the second horizontal direction.

4. The semiconductor package according to claim 1, in, The first bonding pad does not overlap the semiconductor chip in a vertical direction, and The second bonding pad completely overlaps the semiconductor chip in the vertical direction.

5. The semiconductor package according to claim 1, wherein A first height of the first bonding pad in the vertical direction and a second height of the second bonding pad in the vertical direction are the same as a third height of the trace pattern in the vertical direction.

6. The semiconductor package according to claim 1, wherein The plurality of horizontal redistribution structures are symmetrically arranged with respect to a center line crossing the center of the semiconductor chip in the first horizontal direction and a center line crossing the center of the semiconductor chip in the second horizontal direction.

7. The semiconductor package according to claim 1, wherein: The first bonding pad is located farther from a center of the semiconductor chip than the second bonding pad.

8. The semiconductor package according to claim 1, wherein The first bonding pad is located closer to a center of the semiconductor chip than the second bonding pad.

9. The semiconductor package according to claim 1, in, The second bonding pad has a cylindrical shape, and A length of the second bonding pad in a vertical direction is longer than a diameter of the second bonding pad.

10. The semiconductor package according to claim 1, in, The horizontal redistribution structure further includes a third bonding pad formed on the tracking pattern between the first bonding pad and the second bonding pad. The semiconductor chip further comprises a dummy chip connection terminal disposed on one side of the chip body, and Wherein, the third bonding pad is bonded to the dummy chip connecting terminal.

11. A semiconductor package, comprising: Package substrate; Redistribution structure, including: an insulating layer, disposed on the first side of the packaging substrate, a plurality of horizontal redistribution structures disposed in the insulating layer and arranged adjacent to each other in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction, and multiple vertical redistribution structures; an external connection terminal, disposed on a first side of the redistribution structure; A first semiconductor chip is disposed on the redistribution structure, the first semiconductor chip comprising a first chip body and a first chip connection terminal disposed on a first side of the first chip body; and a second semiconductor chip spaced apart from the first semiconductor chip in the first horizontal direction and comprising a second chip body and a second chip connection terminal disposed on a first side of the second chip body; The plurality of vertical redistribution structures completely overlap with the first semiconductor chip in a vertical direction. Wherein, each of the plurality of horizontal redistribution structures comprises: a via hole passing through the insulating layer; a tracer pattern formed integrally with the via and extending at an angle to the first horizontal direction and the second horizontal direction; a first bonding pad disposed on the insulating layer, formed integrally with the via hole, and formed at a first position on the tracing pattern; and A second bonding pad is formed at a second position on the trace pattern that is different from the first position and is bonded to the second chip connection terminal.

12. The semiconductor package according to claim 11, in, The first semiconductor chip includes a logic semiconductor chip, and The second semiconductor chip includes a high bandwidth memory HBM chip.

13. The semiconductor package according to claim 11, wherein Each of the plurality of vertical redistribution structures comprises: vertical redistribution vias passing through the insulating layer; and A vertical redistribution pad is integrally formed with an upper portion of the vertical redistribution via and is bonded to the first chip connection terminal.

14. The semiconductor package according to claim 13, in, A first length of the second bonding pad in the vertical direction is longer than a second length of the vertical redistribution pad in the vertical direction.

15. The semiconductor package according to claim 11, in, The second bonding pad has a cylindrical shape, and A length of the second bonding pad in the vertical direction is longer than a diameter of the second bonding pad.

16. The semiconductor package according to claim 11, wherein The plurality of horizontal redistribution structures further include: a first horizontal redistribution structure overlapping a vertex of the second semiconductor chip in a plan view; and a second horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the first horizontal direction, wherein the first horizontal redistribution structure and the second horizontal redistribution structure are arranged on a first side relative to a center line intersecting the center of the second semiconductor chip in the second horizontal direction, and An inclination angle of the first horizontal redistribution structure relative to the second horizontal direction is different from an inclination angle of the second horizontal redistribution structure relative to the second horizontal direction.

17. The semiconductor package according to claim 16, wherein: The plurality of horizontal redistribution structures further include: a third horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the second horizontal direction, wherein the first horizontal redistribution structure and the third horizontal redistribution structure are arranged on a second side relative to a center line intersecting the center of the second semiconductor chip in the first horizontal direction, and An inclination angle of the first horizontal redistribution structure relative to the second horizontal direction is different from an inclination angle of the third horizontal redistribution structure relative to the second horizontal direction.

18. The semiconductor package according to claim 11, in, The first bonding pad does not overlap with the second semiconductor chip in the vertical direction, and The second bonding pad completely overlaps the second semiconductor chip in the vertical direction.

19. A semiconductor package, comprising: Package substrate; Redistribution structure, including: an insulating layer, disposed on the first side of the packaging substrate, a plurality of horizontal redistribution structures disposed in the insulating layer and arranged side by side in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction, and multiple vertical redistribution structures; External connection terminals, arranged below the redistribution structure; a first semiconductor chip disposed on the redistribution structure, the first semiconductor chip comprising a first chip body and a first chip connection terminal arranged on a first side of the first chip body; and a second semiconductor chip spaced apart from the first semiconductor chip in the first horizontal direction and comprising a second chip body, and a second chip connection terminal arranged on a first side of the second chip body; Wherein, the plurality of horizontal redistribution structures further include: a first horizontal redistribution structure overlapping a vertex of the second semiconductor chip in a plan view and extending at a first angle relative to the second horizontal direction; a second horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the first horizontal direction and extending at a second angle different from the first angle relative to the second horizontal direction; and a third horizontal redistribution structure spaced apart from the first horizontal redistribution structure in the second horizontal direction and extending at a third angle different from the first angle relative to the second horizontal direction, The plurality of vertical redistribution structures completely overlap with the first semiconductor chip in a vertical direction.

20. The semiconductor package according to claim 19, wherein Each of the plurality of horizontal redistribution structures comprises: a via hole passing through the insulating layer; a tracer pattern formed integrally with the via and extending at an angle to the first horizontal direction and the second horizontal direction; a first bonding pad disposed on the insulating layer, formed integrally with the via hole, and formed at a first position of the tracing pattern; and A second bonding pad is formed at a second position of the trace pattern and bonded to the second chip connection terminal.

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